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[patches.git] / 0001-metrologic-fork.patch
CommitLineData
b77ff2bc
MF		 1From 9ecb85954275f5a62293e1416dba107058609117 Mon Sep 17 00:00:00 2001
2From: Mike Frysinger <vapier@gentoo.org>
3Date: Tue, 14 Oct 2008 18:06:33 -0400
4Subject: [PATCH] metrologic fork
5
6---
7 u-boot-1.1.6/Makefile | 22 +-
8 u-boot-1.1.6/board/Focus/Focus.c | 516 +++++++++++++++++++
9 u-boot-1.1.6/board/Focus/Makefile | 59 +++
10 u-boot-1.1.6/board/IS4980/IS4980.c | 516 +++++++++++++++++++
11 u-boot-1.1.6/board/IS4980/Makefile | 59 +++
12 u-boot-1.1.6/board/Orbit3/Makefile | 59 +++
13 u-boot-1.1.6/board/Orbit3/Orbit3.c | 516 +++++++++++++++++++
14 u-boot-1.1.6/board/VuQuest2D/Makefile | 59 +++
15 u-boot-1.1.6/board/VuQuest2D/VuQuest2D.c | 418 +++++++++++++++
16 u-boot-1.1.6/board/VuQuest2D/VuQuest2D.h | 53 ++
17 u-boot-1.1.6/board/VuQuest2D/config.mk | 15 +
18 u-boot-1.1.6/board/VuQuest2D/spi.c | 533 ++++++++++++++++++++
19 u-boot-1.1.6/board/VuQuest2D/spi_flash.c | 2 +
20 u-boot-1.1.6/board/VuQuest2D/u-boot.lds.S | 136 +++++
21 u-boot-1.1.6/board/VuQuest2D/video.c | 187 +++++++
22 u-boot-1.1.6/board/VuQuest2D/video.h | 25 +
23 u-boot-1.1.6/common/Makefile | 2 +-
24 u-boot-1.1.6/common/cmd_bdinfo.c | 40 +-
25 u-boot-1.1.6/common/cmd_bootm.c | 13 +
26 u-boot-1.1.6/common/cmd_eeprom.c | 12 +
27 u-boot-1.1.6/common/cmd_load.c | 456 +++++++++++++++++
28 u-boot-1.1.6/common/cmd_mem.c | 96 ++++
29 u-boot-1.1.6/common/interface_select.c | 526 +++++++++++++++++++
30 u-boot-1.1.6/common/main.c | 123 +++++-
31 u-boot-1.1.6/common/metro_pf.c | 318 ++++++++++++
32 u-boot-1.1.6/cpu/blackfin/i2c.c | 36 ++-
33 u-boot-1.1.6/cpu/blackfin/serial.c | 82 +++
34 u-boot-1.1.6/examples/Makefile | 14 +
35 u-boot-1.1.6/include/Metrologic_Hardware.h | 69 +++
36 .../include/asm-blackfin/blackfin-config-post.h | 50 +--
37 .../include/asm-blackfin/blackfin_clocks.h | 56 ++
38 u-boot-1.1.6/include/asm-blackfin/mem_init.h | 338 +++++++++++++
39 u-boot-1.1.6/include/configs/Focus.h | 381 ++++++++++++++
40 u-boot-1.1.6/include/configs/IS4980.h | 378 ++++++++++++++
41 u-boot-1.1.6/include/configs/Orbit3.h | 378 ++++++++++++++
42 u-boot-1.1.6/include/configs/VuQuest2D.h | 309 ++++++++++++
43 u-boot-1.1.6/include/configs/bf533-stamp.h | 47 ++-
44 u-boot-1.1.6/include/configs/bf537-srv1.h | 50 ++-
45 u-boot-1.1.6/include/configs/bf537-stamp.h | 52 ++-
46 u-boot-1.1.6/include/configs/bfin_adi_common.h | 18 +-
47 u-boot-1.1.6/include/flash.h | 3 +-
48 u-boot-1.1.6/include/metro_pf.h | 103 ++++
49 u-boot-1.1.6/lib_blackfin/board.c | 30 ++-
50 u-boot-1.1.6/uses.mak | 5 +
51 44 files changed, 7051 insertions(+), 109 deletions(-)
52 create mode 100644 u-boot-1.1.6/board/Focus/Focus.c
53 create mode 100644 u-boot-1.1.6/board/Focus/Makefile
54 create mode 100644 u-boot-1.1.6/board/IS4980/IS4980.c
55 create mode 100644 u-boot-1.1.6/board/IS4980/Makefile
56 create mode 100644 u-boot-1.1.6/board/Orbit3/Makefile
57 create mode 100644 u-boot-1.1.6/board/Orbit3/Orbit3.c
58 create mode 100644 u-boot-1.1.6/board/VuQuest2D/Makefile
59 create mode 100644 u-boot-1.1.6/board/VuQuest2D/VuQuest2D.c
60 create mode 100644 u-boot-1.1.6/board/VuQuest2D/VuQuest2D.h
61 create mode 100644 u-boot-1.1.6/board/VuQuest2D/config.mk
62 create mode 100644 u-boot-1.1.6/board/VuQuest2D/spi.c
63 create mode 100644 u-boot-1.1.6/board/VuQuest2D/spi_flash.c
64 create mode 100644 u-boot-1.1.6/board/VuQuest2D/u-boot.lds.S
65 create mode 100644 u-boot-1.1.6/board/VuQuest2D/video.c
66 create mode 100644 u-boot-1.1.6/board/VuQuest2D/video.h
67 create mode 100644 u-boot-1.1.6/common/interface_select.c
68 create mode 100644 u-boot-1.1.6/common/metro_pf.c
69 create mode 100644 u-boot-1.1.6/include/Metrologic_Hardware.h
70 create mode 100644 u-boot-1.1.6/include/asm-blackfin/blackfin_clocks.h
71 create mode 100644 u-boot-1.1.6/include/asm-blackfin/mem_init.h
72 create mode 100644 u-boot-1.1.6/include/configs/Focus.h
73 create mode 100644 u-boot-1.1.6/include/configs/IS4980.h
74 create mode 100644 u-boot-1.1.6/include/configs/Orbit3.h
75 create mode 100644 u-boot-1.1.6/include/configs/VuQuest2D.h
76 create mode 100644 u-boot-1.1.6/include/metro_pf.h
77 create mode 100644 u-boot-1.1.6/uses.mak
78
79diff --git a/u-boot-1.1.6/Makefile b/u-boot-1.1.6/Makefile
80index b3502bb..e4e761d 100644
81--- a/u-boot-1.1.6/Makefile
82+++ b/u-boot-1.1.6/Makefile
83@@ -1,3 +1,4 @@
84+include uses.mak
85 #
86 # (C) Copyright 2000-2006
87 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
88@@ -147,7 +148,7 @@ ifeq ($(ARCH),microblaze)
89 CROSS_COMPILE = mb-
90 endif
91 ifeq ($(ARCH),blackfin)
92-CROSS_COMPILE = bfin-uclinux-
93+CROSS_COMPILE = $(CROSS_COMPILE_PATH)/bfin-uclinux-
94 endif
95 ifeq ($(ARCH),avr32)
96 CROSS_COMPILE = avr32-
97@@ -191,9 +192,21 @@ endif
98 LIBS += lib_$(ARCH)/lib$(ARCH).a
99 LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
100 fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a
101+
102+ifneq ($(BOARD), IS4980)
103+ifneq ($(BOARD), Orbit3)
104+ifneq ($(BOARD), VuQuest2D)
105+ifneq ($(BOARD), Focus)
106+ifneq ($(BOARD), bf533-stamp)
107 LIBS += net/libnet.a
108 LIBS += disk/libdisk.a
109 LIBS += rtc/librtc.a
110+endif
111+endif
112+endif
113+endif
114+endif
115+
116 LIBS += dtt/libdtt.a
117 LIBS += drivers/libdrivers.a
118 LIBS += drivers/nand/libnand.a
119@@ -2264,6 +2277,9 @@ BFIN_BOARDS += cm-bf533 cm-bf537e cm-bf548 cm-bf561
120 # Misc third party boards
121 BFIN_BOARDS += bf537-minotaur bf537-srv1
122
123+# Metrologic boards
124+BFIN_BOARDS += Focus Orbit3 VuQuest2D IS4980
125+
126 $(BFIN_BOARDS:%=%_config) : unconfig
127 @$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
128 @[ "$(SRCTREE)" != "$(OBJTREE)" ] && LNPREFIX="../../include2/asm/" || LNPREFIX="" ; \
129@@ -2321,6 +2337,10 @@ clean:
130 rm -f $(obj)board/cm-bf537e/u-boot.lds
131 rm -f $(obj)board/cm-bf548/u-boot.lds
132 rm -f $(obj)board/cm-bf561/u-boot.lds
133+ rm -f $(obj)board/Focus/u-boot.lds
134+ rm -f $(obj)board/Orbit3/u-boot.lds
135+ rm -f $(obj)board/IS4980/u-boot.lds
136+ rm -f $(obj)board/VuQuest2D/u-boot.lds
137 rm -f $(obj)cpu/blackfin/bootrom-asm-offsets.[chs] $(obj).syms.u-boot.S
138 rm -f $(obj)include/bmp_logo.h
139 rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
140diff --git a/u-boot-1.1.6/board/Focus/Focus.c b/u-boot-1.1.6/board/Focus/Focus.c
141new file mode 100644
142index 0000000..d2ab196
143--- /dev/null
144+++ b/u-boot-1.1.6/board/Focus/Focus.c
145@@ -0,0 +1,516 @@
146+/*
147+ * U-boot - Focus.c
148+ *
149+ * Copyright (c) 2008 Metrologic Instruments Inc.
150+ * Copyright (c) 2005-2007 Analog Devices Inc.
151+ *
152+ * (C) Copyright 2000-2004
153+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
154+ *
155+ * See file CREDITS for list of people who contributed to this
156+ * project.
157+ *
158+ * This program is free software; you can redistribute it and/or
159+ * modify it under the terms of the GNU General Public License as
160+ * published by the Free Software Foundation; either version 2 of
161+ * the License, or (at your option) any later version.
162+ *
163+ * This program is distributed in the hope that it will be useful,
164+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
165+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
166+ * GNU General Public License for more details.
167+ *
168+ * You should have received a copy of the GNU General Public License
169+ * along with this program; if not, write to the Free Software
170+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
171+ * MA 02110-1301 USA
172+ */
173+
174+#include <common.h>
175+#include <config.h>
176+#include <command.h>
177+#include <asm/blackfin.h>
178+#include <asm/io.h>
179+#include <linux/etherdevice.h>
180+
181+#define POST_WORD_ADDR 0xFF903FFC
182+
183+int checkboard(void)
184+{
185+ printf("Board: Metrologic Focus Decode Board\n");
186+ printf(" Support: http://www.metrologic.com/\n");
187+ return 0;
188+}
189+
190+#if defined(CONFIG_BFIN_IDE)
191+
192+void cf_outb(unsigned char val, volatile unsigned char *addr)
193+{
194+ *(addr) = val;
195+ SSYNC();
196+}
197+
198+unsigned char cf_inb(volatile unsigned char *addr)
199+{
200+ volatile unsigned char c;
201+
202+ c = *(addr);
203+ SSYNC();
204+
205+ return c;
206+}
207+
208+void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
209+{
210+ int i;
211+
212+ for (i = 0; i < words; i++)
213+ *(sect_buf + i) = *(addr);
214+ SSYNC();
215+}
216+
217+void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
218+{
219+ int i;
220+
221+ for (i = 0; i < words; i++)
222+ *(addr) = *(sect_buf + i);
223+ SSYNC();
224+}
225+#endif /* CONFIG_BFIN_IDE */
226+
227+long int initdram(int board_type)
228+{
229+ DECLARE_GLOBAL_DATA_PTR;
230+#ifdef DEBUG
231+ int brate;
232+ char *tmp = getenv("baudrate");
233+ brate = simple_strtoul(tmp, NULL, 16);
234+ printf("Serial Port initialized with Baud rate = %x\n", brate);
235+ printf("SDRAM attributes:\n");
236+ printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
237+ "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
238+ 3, 3, 6, 2, 3);
239+ printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
240+ printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
241+#endif
242+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
243+ gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
244+ return CFG_MAX_RAM_SIZE;
245+}
246+
247+int board_get_enetaddr(uchar *mac_addr)
248+{
249+#ifdef CFG_NO_FLASH
250+# define USE_MAC_IN_FLASH 0
251+#else
252+# define USE_MAC_IN_FLASH 1
253+#endif
254+ if (USE_MAC_IN_FLASH) {
255+ /* we cram the MAC in the last flash sector */
256+ uchar *board_mac_addr = (uchar *)0x203F0000;
257+
258+ if (is_valid_ether_addr(board_mac_addr)) {
259+ memcpy(mac_addr, board_mac_addr, 6);
260+ return 0;
261+ }
262+ }
263+
264+ puts("Warning: Generating 'random' MAC address\n");
265+
266+ /* make something up */
267+ const char s[] = __DATE__;
268+ size_t i;
269+ u32 cycles;
270+ for (i = 0; i < 6; ++i) {
271+ asm("%0 = CYCLES;" : "=r" (cycles));
272+ mac_addr[i] = cycles ^ s[i];
273+ }
274+ mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */
275+ return 0;
276+}
277+
278+void board_reset(void)
279+{ /* FIXME: Alex Au: Don't know if we need to use this workaround... */
280+ /* workaround for weak pull ups on ssel */
281+ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
282+ bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10);
283+ bfin_write_PORTFIO_SET(PF10);
284+ udelay(1);
285+ }
286+}
287+
288+
289+
290+#ifdef CONFIG_METROLOGIC_IO_INIT
291+
292+int metrologic_io_init(void)
293+{
294+ /* Port F:
295+
296+ 0 (out) <<< Host RS232 TX >>>
297+ 1 (in) <<< Host RS232 RX >>>
298+ 2 (out) <<< I/O TX >>> / RDATA [h] (bfin_serial driver takes care of FER)
299+ 3 (in) <<< I/O RX >>> / CLKOUT (bfin_serial driver takes care of FER)
300+ 4 (out) BEEP [l]
301+ 5 (out) Target [l]
302+ 6 (out) cam_sync [l]
303+ 7 (out) PSOC RESET [l]
304+ 8 (in) <<< PPI_VSYNC >>> [later, input]
305+ 9 (in) <<< PPI_HSYNC >>> [later, input]
306+ 10 (out) <<< SPI_CS >>>
307+ 11 (out) <<< SPI_MOSI >>>
308+ 12 (in) <<< SPI_MISO >>>
309+ 13 (out) <<< SPI_CLOCK >>>
310+ 14 (out) SPI_WP [h]
311+ 15 (in) <<< PPI_Clock >>> [later, input]
312+
313+ */
314+
315+ *pPORTF_FER = PF0|PF1|PF2|PF3|PF10|PF11|PF12|PF13; /* PPI enabled in image device driver */
316+ *pPORTFIO_DIR |= PF4|PF5|PF6|PF7|PF14;
317+ *pPORTFIO_DIR &= ~(PF8|PF9|PF15);
318+ *pPORTFIO_INEN &= ~(PF4|PF5|PF6|PF7|PF14 | PF8|PF9|PF15);
319+ *pPORTFIO &= ~(PF4|PF5|PF6|PF7);
320+ *pPORTFIO |= PF14;
321+
322+ /* Port G:
323+
324+ 0 (in) <<< PPI_Data >>> [later, input]
325+ 1 (in) <<< PPI_Data >>> [later, input]
326+ 2 (in) <<< PPI_Data >>> [later, input]
327+ 3 (in) <<< PPI_Data >>> [later, input]
328+ 4 (in) <<< PPI_Data >>> [later, input]
329+ 5 (in) <<< PPI_Data >>> [later, input]
330+ 6 (in) <<< PPI_Data >>> [later, input]
331+ 7 (in) <<< PPI_Data >>> [later, input]
332+ 8 (out) FOCUS_KBWEN [l] when all I/O are set, then low
333+ 9 (out) HOSTRTS ( Leave as input / output high until polarity is known )
334+ 10 (out) FOCUS_IORTS ( Leave as input / output high until polarity is known )
335+ 11 (out) FOCUS_KBWGATE [l]
336+ 12 (out) LED Voltage Enable [h]
337+ 13 (out) LED yellow [h]
338+ 14 (out) LED white [h]
339+ 15 (out) LED Blue [h]
340+
341+ */
342+
343+ *pPORTG_FER = 0;
344+ *pPORTGIO_DIR = PG8|PG9|PG10|PG11|PG12|PG13|PG14|PG15;
345+ *pPORTGIO_INEN = 0;
346+ *pPORTGIO |= PG9|PG10|PG12|PG13|PG14|PG15;
347+ *pPORTGIO &= ~(PG8|PG11);
348+
349+ /* Port H:
350+
351+ 0 (out) KBW_PCClk [l]
352+ 1 (out) KBS_PCDATA [l]
353+ 2 (in) IBM_Reset
354+ 3 (in) DTR_IN
355+ 4 (in) PC_DET / IBM/USB_EN
356+ 5 (in) CLKIN
357+ 6 (in) IR_IN
358+ 7 (in) I/O CTS / SDATA
359+ 8 (in) HOST CTS
360+ 9 (in) BUTTON
361+ 10 (in) READ SWITCH
362+ 11 (out) FRAM_WP [h]
363+ 12 (in) IR NEAR / FAR
364+ 13 (out) Ocillator En. (Active high) [h]
365+ 14 (out) Sensor Standby (Active low-Micron) [h]
366+ 15 (out) Sensor Reset (Active High-Micron)[l]
367+
368+ */
369+
370+ *pPORTH_FER = 0;
371+ *pPORTHIO_DIR = PH0|PH1|PH11|PH13|PH14|PH15;
372+ *pPORTHIO_INEN = PH2|PH3|PH4|PH5|PH6|PH7|PH8|PH9|PH10|PH12;
373+ *pPORTHIO |= PH11|PH13|PH14;
374+ *pPORTHIO &= ~(PH0|PH1|PH15);
375+
376+ __builtin_bfin_ssync();
377+
378+#if defined(DEBUG_METRO_IO)
379+ printf("start Configure_Interface_IO()\r\n");
380+#endif
381+ Configure_Interface_IO();
382+#if defined(DEBUG_METRO_IO)
383+ printf("done Configure_Interface_IO()\r\n");
384+#endif
385+
386+ return 0;
387+
388+}
389+
390+#endif /* CONFIG_METROLOGIC_IO_INIT */
391+#if defined(CONFIG_MISC_INIT_R)
392+/* miscellaneous platform dependent initialisations */
393+int misc_init_r(void)
394+{
395+#ifndef CFG_NO_FLASH
396+ /* we use the last sector for the MAC address / POST DXE */
397+ extern flash_info_t flash_info[];
398+ flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
399+#endif
400+
401+#if defined(CONFIG_BFIN_IDE)
402+#if defined(CONFIG_BFIN_TRUE_IDE)
403+ /* Enable ATASEL when in True IDE mode */
404+ printf("Using CF True IDE Mode\n");
405+ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
406+ udelay(1000);
407+#elif defined(CONFIG_BFIN_CF_IDE)
408+ /* Disable ATASEL when we're in Common Memory Mode */
409+ printf("Using CF Common Memory Mode\n");
410+ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
411+ udelay(1000);
412+#elif defined(CONFIG_BFIN_HDD_IDE)
413+ printf("Using HDD IDE Mode\n");
414+#endif
415+ ide_init();
416+#endif /* CONFIG_BFIN_IDE */
417+ return 0;
418+}
419+#endif /* CONFIG_MISC_INIT_R */
420+
421+#ifdef CONFIG_POST
422+#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
423+/* Using sw10-PF5 as the hotkey */
424+int post_hotkeys_pressed(void)
425+{
426+ return 0;
427+}
428+#else
429+/* Using sw10-PF5 as the hotkey */
430+int post_hotkeys_pressed(void)
431+{
432+ int delay = 3;
433+ int i;
434+ unsigned short value;
435+
436+ *pPORTF_FER &= ~PF5;
437+ *pPORTFIO_DIR &= ~PF5;
438+ *pPORTFIO_INEN |= PF5;
439+
440+ printf("########Press SW10 to enter Memory POST########: %2d ", delay);
441+ while (delay--) {
442+ for (i = 0; i < 100; i++) {
443+ value = *pPORTFIO & PF5;
444+ if (value != 0) {
445+ break;
446+ }
447+ udelay(10000);
448+ }
449+ printf("\b\b\b%2d ", delay);
450+ }
451+ printf("\b\b\b 0");
452+ printf("\n");
453+ if (value == 0)
454+ return 0;
455+ else {
456+ printf("Hotkey has been pressed, Enter POST . . . . . .\n");
457+ return 1;
458+ }
459+}
460+#endif
461+#endif
462+
463+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
464+void post_word_store(ulong a)
465+{
466+ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
467+ *save_addr = a;
468+}
469+
470+ulong post_word_load(void)
471+{
472+ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
473+ return *save_addr;
474+}
475+#endif
476+
477+#ifdef CONFIG_POST
478+int uart_post_test(int flags)
479+{
480+ return 0;
481+}
482+
483+#define BLOCK_SIZE 0x10000
484+#define VERIFY_ADDR 0x2000000
485+extern int erase_block_flash(int);
486+extern int write_data(long lStart, long lCount, uchar * pnData);
487+int flash_post_test(int flags)
488+{
489+ unsigned short *pbuf, *temp;
490+ int offset, n, i;
491+ int value = 0;
492+ int result = 0;
493+ printf("\n");
494+ pbuf = (unsigned short *)VERIFY_ADDR;
495+ temp = pbuf;
496+ for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
497+ offset = (n - 7) * BLOCK_SIZE;
498+ printf("--------Erase block:%2d..", n);
499+ erase_block_flash(n);
500+ printf("OK\r");
501+ printf("--------Program block:%2d...", n);
502+ write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
503+ printf("OK\r");
504+ printf("--------Verify block:%2d...", n);
505+ for (i = 0; i < BLOCK_SIZE; i += 2) {
506+ if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
507+ *temp++) {
508+ value = 1;
509+ result = 1;
510+ }
511+ }
512+ if (value)
513+ printf("failed\n");
514+ else
515+ printf("OK %3d%%\r",
516+ (int)(
517+ (n + 1 -
518+ FLASH_START_POST_BLOCK) *
519+ 100 / (FLASH_END_POST_BLOCK -
520+ FLASH_START_POST_BLOCK)));
521+
522+ temp = pbuf;
523+ value = 0;
524+ }
525+ printf("\n");
526+ if (result)
527+ return -1;
528+ else
529+ return 0;
530+}
531+
532+/****************************************************
533+ * LED1 ---- PF6 LED2 ---- PF7 *
534+ * LED3 ---- PF8 LED4 ---- PF9 *
535+ * LED5 ---- PF10 LED6 ---- PF11 *
536+ ****************************************************/
537+int led_post_test(int flags)
538+{
539+ *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
540+ *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
541+ *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
542+ *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
543+ udelay(1000000);
544+ printf("LED1 on");
545+ *pPORTFIO |= PF6;
546+ udelay(1000000);
547+ printf("\b\b\b\b\b\b\b");
548+ printf("LED2 on");
549+ *pPORTFIO |= PF7;
550+ udelay(1000000);
551+ printf("\b\b\b\b\b\b\b");
552+ printf("LED3 on");
553+ *pPORTFIO |= PF8;
554+ udelay(1000000);
555+ printf("\b\b\b\b\b\b\b");
556+ printf("LED4 on");
557+ *pPORTFIO |= PF9;
558+ udelay(1000000);
559+ printf("\b\b\b\b\b\b\b");
560+ printf("LED5 on");
561+ *pPORTFIO |= PF10;
562+ udelay(1000000);
563+ printf("\b\b\b\b\b\b\b");
564+ printf("lED6 on");
565+ *pPORTFIO |= PF11;
566+ printf("\b\b\b\b\b\b\b ");
567+ return 0;
568+}
569+
570+/************************************************
571+ * SW10 ---- PF5 SW11 ---- PF4 *
572+ * SW12 ---- PF3 SW13 ---- PF2 *
573+ ************************************************/
574+int button_post_test(int flags)
575+{
576+ int i, delay = 5;
577+ unsigned short value = 0;
578+ int result = 0;
579+
580+ *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
581+ *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
582+ *pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
583+
584+ printf("\n--------Press SW10: %2d ", delay);
585+ while (delay--) {
586+ for (i = 0; i < 100; i++) {
587+ value = *pPORTFIO & PF5;
588+ if (value != 0) {
589+ break;
590+ }
591+ udelay(10000);
592+ }
593+ printf("\b\b\b%2d ", delay);
594+ }
595+ if (value != 0)
596+ printf("\b\bOK");
597+ else {
598+ result = -1;
599+ printf("\b\bfailed");
600+ }
601+
602+ delay = 5;
603+ printf("\n--------Press SW11: %2d ", delay);
604+ while (delay--) {
605+ for (i = 0; i < 100; i++) {
606+ value = *pPORTFIO & PF4;
607+ if (value != 0) {
608+ break;
609+ }
610+ udelay(10000);
611+ }
612+ printf("\b\b\b%2d ", delay);
613+ }
614+ if (value != 0)
615+ printf("\b\bOK");
616+ else {
617+ result = -1;
618+ printf("\b\bfailed");
619+ }
620+
621+ delay = 5;
622+ printf("\n--------Press SW12: %2d ", delay);
623+ while (delay--) {
624+ for (i = 0; i < 100; i++) {
625+ value = *pPORTFIO & PF3;
626+ if (value != 0) {
627+ break;
628+ }
629+ udelay(10000);
630+ }
631+ printf("\b\b\b%2d ", delay);
632+ }
633+ if (value != 0)
634+ printf("\b\bOK");
635+ else {
636+ result = -1;
637+ printf("\b\bfailed");
638+ }
639+
640+ delay = 5;
641+ printf("\n--------Press SW13: %2d ", delay);
642+ while (delay--) {
643+ for (i = 0; i < 100; i++) {
644+ value = *pPORTFIO & PF2;
645+ if (value != 0) {
646+ break;
647+ }
648+ udelay(10000);
649+ }
650+ printf("\b\b\b%2d ", delay);
651+ }
652+ if (value != 0)
653+ printf("\b\bOK");
654+ else {
655+ result = -1;
656+ printf("\b\bfailed");
657+ }
658+ printf("\n");
659+ return result;
660+}
661+#endif
662diff --git a/u-boot-1.1.6/board/Focus/Makefile b/u-boot-1.1.6/board/Focus/Makefile
663new file mode 100644
664index 0000000..4d03b2c
665--- /dev/null
666+++ b/u-boot-1.1.6/board/Focus/Makefile
667@@ -0,0 +1,59 @@
668+#
669+# U-boot - Makefile
670+#
671+# Copyright (c) 2005-2007 Analog Device Inc.
672+#
673+# (C) Copyright 2000-2006
674+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
675+#
676+# See file CREDITS for list of people who contributed to this
677+# project.
678+#
679+# This program is free software; you can redistribute it and/or
680+# modify it under the terms of the GNU General Public License as
681+# published by the Free Software Foundation; either version 2 of
682+# the License, or (at your option) any later version.
683+#
684+# This program is distributed in the hope that it will be useful,
685+# but WITHOUT ANY WARRANTY; without even the implied warranty of
686+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
687+# GNU General Public License for more details.
688+#
689+# You should have received a copy of the GNU General Public License
690+# along with this program; if not, write to the Free Software
691+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
692+# MA 02111-1307 USA
693+#
694+
695+include $(TOPDIR)/config.mk
696+
697+LIB = $(obj)lib$(BOARD).a
698+
699+COBJS := $(BOARD).o post-memory.o spi_flash.o cmd_bf537led.o nand.o
700+#COBJS := $(BOARD).o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
701+
702+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
703+OBJS := $(addprefix $(obj),$(COBJS))
704+SOBJS := $(addprefix $(obj),$(SOBJS))
705+
706+$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
707+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
708+
709+u-boot.lds: u-boot.lds.S
710+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
711+ mv -f $@.tmp $@
712+
713+clean:
714+ rm -f $(SOBJS) $(OBJS)
715+
716+distclean: clean
717+ rm -f $(LIB) core *.bak .depend
718+
719+#########################################################################
720+
721+# defines $(obj).depend target
722+include $(SRCTREE)/rules.mk
723+
724+sinclude $(obj).depend
725+
726+#########################################################################
727diff --git a/u-boot-1.1.6/board/IS4980/IS4980.c b/u-boot-1.1.6/board/IS4980/IS4980.c
728new file mode 100644
729index 0000000..4836853
730--- /dev/null
731+++ b/u-boot-1.1.6/board/IS4980/IS4980.c
732@@ -0,0 +1,516 @@
733+/*
734+ * U-boot - Orbit3.c
735+ *
736+ * Copyright (c) 2008 Metrologic Instruments Inc.
737+ * Copyright (c) 2005-2007 Analog Devices Inc.
738+ *
739+ * (C) Copyright 2000-2004
740+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
741+ *
742+ * See file CREDITS for list of people who contributed to this
743+ * project.
744+ *
745+ * This program is free software; you can redistribute it and/or
746+ * modify it under the terms of the GNU General Public License as
747+ * published by the Free Software Foundation; either version 2 of
748+ * the License, or (at your option) any later version.
749+ *
750+ * This program is distributed in the hope that it will be useful,
751+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
752+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
753+ * GNU General Public License for more details.
754+ *
755+ * You should have received a copy of the GNU General Public License
756+ * along with this program; if not, write to the Free Software
757+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
758+ * MA 02110-1301 USA
759+ */
760+
761+#include <common.h>
762+#include <config.h>
763+#include <command.h>
764+#include <asm/blackfin.h>
765+#include <asm/io.h>
766+#include <linux/etherdevice.h>
767+
768+#define POST_WORD_ADDR 0xFF903FFC
769+
770+int checkboard(void)
771+{
772+ printf("Board: Metrologic Genesis Decode Board\n");
773+ printf(" Support: http://www.metrologic.com/\n");
774+ return 0;
775+}
776+
777+#if defined(CONFIG_BFIN_IDE)
778+
779+void cf_outb(unsigned char val, volatile unsigned char *addr)
780+{
781+ *(addr) = val;
782+ SSYNC();
783+}
784+
785+unsigned char cf_inb(volatile unsigned char *addr)
786+{
787+ volatile unsigned char c;
788+
789+ c = *(addr);
790+ SSYNC();
791+
792+ return c;
793+}
794+
795+void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
796+{
797+ int i;
798+
799+ for (i = 0; i < words; i++)
800+ *(sect_buf + i) = *(addr);
801+ SSYNC();
802+}
803+
804+void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
805+{
806+ int i;
807+
808+ for (i = 0; i < words; i++)
809+ *(addr) = *(sect_buf + i);
810+ SSYNC();
811+}
812+#endif /* CONFIG_BFIN_IDE */
813+
814+long int initdram(int board_type)
815+{
816+ DECLARE_GLOBAL_DATA_PTR;
817+#ifdef DEBUG
818+ int brate;
819+ char *tmp = getenv("baudrate");
820+ brate = simple_strtoul(tmp, NULL, 16);
821+ printf("Serial Port initialized with Baud rate = %x\n", brate);
822+ printf("SDRAM attributes:\n");
823+ printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
824+ "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
825+ 3, 3, 6, 2, 3);
826+ printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
827+ printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
828+#endif
829+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
830+ gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
831+ return CFG_MAX_RAM_SIZE;
832+}
833+
834+int board_get_enetaddr(uchar *mac_addr)
835+{
836+#ifdef CFG_NO_FLASH
837+# define USE_MAC_IN_FLASH 0
838+#else
839+# define USE_MAC_IN_FLASH 1
840+#endif
841+ if (USE_MAC_IN_FLASH) {
842+ /* we cram the MAC in the last flash sector */
843+ uchar *board_mac_addr = (uchar *)0x203F0000;
844+
845+ if (is_valid_ether_addr(board_mac_addr)) {
846+ memcpy(mac_addr, board_mac_addr, 6);
847+ return 0;
848+ }
849+ }
850+
851+ puts("Warning: Generating 'random' MAC address\n");
852+
853+ /* make something up */
854+ const char s[] = __DATE__;
855+ size_t i;
856+ u32 cycles;
857+ for (i = 0; i < 6; ++i) {
858+ asm("%0 = CYCLES;" : "=r" (cycles));
859+ mac_addr[i] = cycles ^ s[i];
860+ }
861+ mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */
862+ return 0;
863+}
864+
865+void board_reset(void)
866+{ /* FIXME: Alex Au: Don't know if we need to use this workaround... */
867+ /* workaround for weak pull ups on ssel */
868+ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
869+ bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10);
870+ bfin_write_PORTFIO_SET(PF10);
871+ udelay(1);
872+ }
873+}
874+
875+
876+
877+#ifdef CONFIG_METROLOGIC_IO_INIT
878+
879+int metrologic_io_init(void)
880+{
881+ /* Port F:
882+
883+ 0 (out) <<< Host RS232 TX >>>
884+ 1 (in) <<< Host RS232 RX >>>
885+ 2 (out) <<< White LED (PWM) >>> [h] turns on LED
886+ 3 (Out) <<< Blue LED (PWM) >>> [h] turns on LED
887+ 4 (out) BEEP [l]
888+ 5 (out) Target [l]
889+ 6 (out) cam_sync [l]
890+ 7 (out) Force On [l]
891+ 8 (in) <<< PPI_VSYNC >>> [later, input]
892+ 9 (in) <<< PPI_HSYNC >>> [later, input]
893+ 10 (out) <<< SPI_CS >>>
894+ 11 (out) <<< SPI_MOSI >>>
895+ 12 (in) <<< SPI_MISO >>>
896+ 13 (out) <<< SPI_CLOCK >>>
897+ 14 (out) SPI_WP [h]
898+ 15 (in) <<< PPI_Clock >>> [later, input]
899+
900+ */
901+
902+ *pPORTF_FER = PF0|PF1|PF10|PF11|PF12|PF13; /* PPI enabled in image device driver */
903+ *pPORTFIO_DIR |= PF4|PF5|PF6|PF7|PF14;
904+ *pPORTFIO_DIR &= ~(PF2|PF3|PF8|PF9|PF15);
905+ *pPORTFIO_INEN &= ~(PF2|PF3|PF4|PF5|PF6|PF7|PF8|PF9|PF14|PF15);
906+ *pPORTFIO &= ~(PF4|PF5|PF6|PF7);
907+ *pPORTFIO |= PF14;
908+
909+ /* Port G:
910+
911+ 0 (in) <<< PPI_Data >>> [later, input]
912+ 1 (in) <<< PPI_Data >>> [later, input]
913+ 2 (in) <<< PPI_Data >>> [later, input]
914+ 3 (in) <<< PPI_Data >>> [later, input]
915+ 4 (in) <<< PPI_Data >>> [later, input]
916+ 5 (in) <<< PPI_Data >>> [later, input]
917+ 6 (in) <<< PPI_Data >>> [later, input]
918+ 7 (in) <<< PPI_Data >>> [later, input]
919+ 8 (out) DEC_KB_PASS_EN (Act. L) [l] (switch closed)
920+ 9 (out) HOSTRTS ( Leave as input / output high until polarity is known )
921+ *10 (out) LED_HIGH_V [h] (video low, snap-shot high) / (USB high)
922+ *11 (out) RESET IF (active H) [l]
923+ 12 (out) LED Voltage Enable [h]
924+ 13 (in) USB_KBW_BF (0=KBW;1=USB)
925+ 14 (in) BUF_PC_CLOCK_COL
926+ 15 (in) BUF_BSY_OR_LPD
927+
928+ */
929+
930+ *pPORTG_FER = 0;
931+ *pPORTGIO_DIR = PG8|PG9|PG10|PG11|PG12;
932+ *pPORTGIO_INEN = PG13|PG14|PG15;
933+ *pPORTGIO |= PG9|PG10|PG12;
934+ *pPORTGIO &= ~(PG8|PG11);
935+
936+ /* Port H:
937+
938+ *0 (in) BUF_PC_DATA_COL
939+ *1 (out) DEC_KB_CLOCK_BASE [l]*
940+ *2 (out) DEC_KB_DATA_BASE [l]*
941+ *3 (out) DEC_PC_CLOCK_BASE [l]*
942+ *4 (out) DEC_PC_DATA_BASE [l]*
943+ *5 (out) DEC_LT_PEN_BASE [l]*
944+ 6 (in) IR_IN
945+ *7 (out) DEC_REQ_UC [l]*
946+ 8 (in) HOST CTS
947+ 9 (in) BUTTON
948+ *10 (in) BUF_SPI_REQ
949+ *11 (in) BUF_EP_FULL_PAUSE
950+ *12 (out) Ocillator En. (Active high) [h]
951+ 13 (out) DC Mode (Active low) [h]
952+ *14 (out) NEAR_SEL [l]
953+ *15 (in) DEC_DTR_FULL
954+
955+ */
956+
957+ *pPORTH_FER = 0;
958+ *pPORTHIO_DIR = PH1|PH2|PH3|PH4|PH5|PH7|PH12|PH13|PH14;
959+ *pPORTHIO_INEN = ~(PH1|PH2|PH3|PH4|PH5|PH7|PH12|PH13|PH14);
960+ *pPORTHIO |= PH12|PH13;
961+ *pPORTHIO &= ~(PH1|PH2|PH3|PH4|PH5|PH7|PH14);
962+
963+ __builtin_bfin_ssync();
964+
965+#if defined(DEBUG_METRO_IO)
966+ printf("start Configure_Interface_IO()\r\n");
967+#endif
968+ Configure_Interface_IO();
969+#if defined(DEBUG_METRO_IO)
970+ printf("done Configure_Interface_IO()\r\n");
971+#endif
972+
973+ return 0;
974+
975+}
976+
977+#endif /* CONFIG_METROLOGIC_IO_INIT */
978+#if defined(CONFIG_MISC_INIT_R)
979+/* miscellaneous platform dependent initialisations */
980+int misc_init_r(void)
981+{
982+#ifndef CFG_NO_FLASH
983+ /* we use the last sector for the MAC address / POST DXE */
984+ extern flash_info_t flash_info[];
985+ flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
986+#endif
987+
988+#if defined(CONFIG_BFIN_IDE)
989+#if defined(CONFIG_BFIN_TRUE_IDE)
990+ /* Enable ATASEL when in True IDE mode */
991+ printf("Using CF True IDE Mode\n");
992+ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
993+ udelay(1000);
994+#elif defined(CONFIG_BFIN_CF_IDE)
995+ /* Disable ATASEL when we're in Common Memory Mode */
996+ printf("Using CF Common Memory Mode\n");
997+ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
998+ udelay(1000);
999+#elif defined(CONFIG_BFIN_HDD_IDE)
1000+ printf("Using HDD IDE Mode\n");
1001+#endif
1002+ ide_init();
1003+#endif /* CONFIG_BFIN_IDE */
1004+ return 0;
1005+}
1006+#endif /* CONFIG_MISC_INIT_R */
1007+
1008+#ifdef CONFIG_POST
1009+#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
1010+/* Using sw10-PF5 as the hotkey */
1011+int post_hotkeys_pressed(void)
1012+{
1013+ return 0;
1014+}
1015+#else
1016+/* Using sw10-PF5 as the hotkey */
1017+int post_hotkeys_pressed(void)
1018+{
1019+ int delay = 3;
1020+ int i;
1021+ unsigned short value;
1022+
1023+ *pPORTF_FER &= ~PF5;
1024+ *pPORTFIO_DIR &= ~PF5;
1025+ *pPORTFIO_INEN |= PF5;
1026+
1027+ printf("########Press SW10 to enter Memory POST########: %2d ", delay);
1028+ while (delay--) {
1029+ for (i = 0; i < 100; i++) {
1030+ value = *pPORTFIO & PF5;
1031+ if (value != 0) {
1032+ break;
1033+ }
1034+ udelay(10000);
1035+ }
1036+ printf("\b\b\b%2d ", delay);
1037+ }
1038+ printf("\b\b\b 0");
1039+ printf("\n");
1040+ if (value == 0)
1041+ return 0;
1042+ else {
1043+ printf("Hotkey has been pressed, Enter POST . . . . . .\n");
1044+ return 1;
1045+ }
1046+}
1047+#endif
1048+#endif
1049+
1050+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
1051+void post_word_store(ulong a)
1052+{
1053+ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
1054+ *save_addr = a;
1055+}
1056+
1057+ulong post_word_load(void)
1058+{
1059+ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
1060+ return *save_addr;
1061+}
1062+#endif
1063+
1064+#ifdef CONFIG_POST
1065+int uart_post_test(int flags)
1066+{
1067+ return 0;
1068+}
1069+
1070+#define BLOCK_SIZE 0x10000
1071+#define VERIFY_ADDR 0x2000000
1072+extern int erase_block_flash(int);
1073+extern int write_data(long lStart, long lCount, uchar * pnData);
1074+int flash_post_test(int flags)
1075+{
1076+ unsigned short *pbuf, *temp;
1077+ int offset, n, i;
1078+ int value = 0;
1079+ int result = 0;
1080+ printf("\n");
1081+ pbuf = (unsigned short *)VERIFY_ADDR;
1082+ temp = pbuf;
1083+ for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
1084+ offset = (n - 7) * BLOCK_SIZE;
1085+ printf("--------Erase block:%2d..", n);
1086+ erase_block_flash(n);
1087+ printf("OK\r");
1088+ printf("--------Program block:%2d...", n);
1089+ write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
1090+ printf("OK\r");
1091+ printf("--------Verify block:%2d...", n);
1092+ for (i = 0; i < BLOCK_SIZE; i += 2) {
1093+ if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
1094+ *temp++) {
1095+ value = 1;
1096+ result = 1;
1097+ }
1098+ }
1099+ if (value)
1100+ printf("failed\n");
1101+ else
1102+ printf("OK %3d%%\r",
1103+ (int)(
1104+ (n + 1 -
1105+ FLASH_START_POST_BLOCK) *
1106+ 100 / (FLASH_END_POST_BLOCK -
1107+ FLASH_START_POST_BLOCK)));
1108+
1109+ temp = pbuf;
1110+ value = 0;
1111+ }
1112+ printf("\n");
1113+ if (result)
1114+ return -1;
1115+ else
1116+ return 0;
1117+}
1118+
1119+/****************************************************
1120+ * LED1 ---- PF6 LED2 ---- PF7 *
1121+ * LED3 ---- PF8 LED4 ---- PF9 *
1122+ * LED5 ---- PF10 LED6 ---- PF11 *
1123+ ****************************************************/
1124+int led_post_test(int flags)
1125+{
1126+ *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
1127+ *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
1128+ *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
1129+ *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
1130+ udelay(1000000);
1131+ printf("LED1 on");
1132+ *pPORTFIO |= PF6;
1133+ udelay(1000000);
1134+ printf("\b\b\b\b\b\b\b");
1135+ printf("LED2 on");
1136+ *pPORTFIO |= PF7;
1137+ udelay(1000000);
1138+ printf("\b\b\b\b\b\b\b");
1139+ printf("LED3 on");
1140+ *pPORTFIO |= PF8;
1141+ udelay(1000000);
1142+ printf("\b\b\b\b\b\b\b");
1143+ printf("LED4 on");
1144+ *pPORTFIO |= PF9;
1145+ udelay(1000000);
1146+ printf("\b\b\b\b\b\b\b");
1147+ printf("LED5 on");
1148+ *pPORTFIO |= PF10;
1149+ udelay(1000000);
1150+ printf("\b\b\b\b\b\b\b");
1151+ printf("lED6 on");
1152+ *pPORTFIO |= PF11;
1153+ printf("\b\b\b\b\b\b\b ");
1154+ return 0;
1155+}
1156+
1157+/************************************************
1158+ * SW10 ---- PF5 SW11 ---- PF4 *
1159+ * SW12 ---- PF3 SW13 ---- PF2 *
1160+ ************************************************/
1161+int button_post_test(int flags)
1162+{
1163+ int i, delay = 5;
1164+ unsigned short value = 0;
1165+ int result = 0;
1166+
1167+ *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
1168+ *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
1169+ *pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
1170+
1171+ printf("\n--------Press SW10: %2d ", delay);
1172+ while (delay--) {
1173+ for (i = 0; i < 100; i++) {
1174+ value = *pPORTFIO & PF5;
1175+ if (value != 0) {
1176+ break;
1177+ }
1178+ udelay(10000);
1179+ }
1180+ printf("\b\b\b%2d ", delay);
1181+ }
1182+ if (value != 0)
1183+ printf("\b\bOK");
1184+ else {
1185+ result = -1;
1186+ printf("\b\bfailed");
1187+ }
1188+
1189+ delay = 5;
1190+ printf("\n--------Press SW11: %2d ", delay);
1191+ while (delay--) {
1192+ for (i = 0; i < 100; i++) {
1193+ value = *pPORTFIO & PF4;
1194+ if (value != 0) {
1195+ break;
1196+ }
1197+ udelay(10000);
1198+ }
1199+ printf("\b\b\b%2d ", delay);
1200+ }
1201+ if (value != 0)
1202+ printf("\b\bOK");
1203+ else {
1204+ result = -1;
1205+ printf("\b\bfailed");
1206+ }
1207+
1208+ delay = 5;
1209+ printf("\n--------Press SW12: %2d ", delay);
1210+ while (delay--) {
1211+ for (i = 0; i < 100; i++) {
1212+ value = *pPORTFIO & PF3;
1213+ if (value != 0) {
1214+ break;
1215+ }
1216+ udelay(10000);
1217+ }
1218+ printf("\b\b\b%2d ", delay);
1219+ }
1220+ if (value != 0)
1221+ printf("\b\bOK");
1222+ else {
1223+ result = -1;
1224+ printf("\b\bfailed");
1225+ }
1226+
1227+ delay = 5;
1228+ printf("\n--------Press SW13: %2d ", delay);
1229+ while (delay--) {
1230+ for (i = 0; i < 100; i++) {
1231+ value = *pPORTFIO & PF2;
1232+ if (value != 0) {
1233+ break;
1234+ }
1235+ udelay(10000);
1236+ }
1237+ printf("\b\b\b%2d ", delay);
1238+ }
1239+ if (value != 0)
1240+ printf("\b\bOK");
1241+ else {
1242+ result = -1;
1243+ printf("\b\bfailed");
1244+ }
1245+ printf("\n");
1246+ return result;
1247+}
1248+#endif
1249diff --git a/u-boot-1.1.6/board/IS4980/Makefile b/u-boot-1.1.6/board/IS4980/Makefile
1250new file mode 100644
1251index 0000000..4d03b2c
1252--- /dev/null
1253+++ b/u-boot-1.1.6/board/IS4980/Makefile
1254@@ -0,0 +1,59 @@
1255+#
1256+# U-boot - Makefile
1257+#
1258+# Copyright (c) 2005-2007 Analog Device Inc.
1259+#
1260+# (C) Copyright 2000-2006
1261+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1262+#
1263+# See file CREDITS for list of people who contributed to this
1264+# project.
1265+#
1266+# This program is free software; you can redistribute it and/or
1267+# modify it under the terms of the GNU General Public License as
1268+# published by the Free Software Foundation; either version 2 of
1269+# the License, or (at your option) any later version.
1270+#
1271+# This program is distributed in the hope that it will be useful,
1272+# but WITHOUT ANY WARRANTY; without even the implied warranty of
1273+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1274+# GNU General Public License for more details.
1275+#
1276+# You should have received a copy of the GNU General Public License
1277+# along with this program; if not, write to the Free Software
1278+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1279+# MA 02111-1307 USA
1280+#
1281+
1282+include $(TOPDIR)/config.mk
1283+
1284+LIB = $(obj)lib$(BOARD).a
1285+
1286+COBJS := $(BOARD).o post-memory.o spi_flash.o cmd_bf537led.o nand.o
1287+#COBJS := $(BOARD).o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
1288+
1289+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
1290+OBJS := $(addprefix $(obj),$(COBJS))
1291+SOBJS := $(addprefix $(obj),$(SOBJS))
1292+
1293+$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
1294+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
1295+
1296+u-boot.lds: u-boot.lds.S
1297+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
1298+ mv -f $@.tmp $@
1299+
1300+clean:
1301+ rm -f $(SOBJS) $(OBJS)
1302+
1303+distclean: clean
1304+ rm -f $(LIB) core *.bak .depend
1305+
1306+#########################################################################
1307+
1308+# defines $(obj).depend target
1309+include $(SRCTREE)/rules.mk
1310+
1311+sinclude $(obj).depend
1312+
1313+#########################################################################
1314diff --git a/u-boot-1.1.6/board/Orbit3/Makefile b/u-boot-1.1.6/board/Orbit3/Makefile
1315new file mode 100644
1316index 0000000..4d03b2c
1317--- /dev/null
1318+++ b/u-boot-1.1.6/board/Orbit3/Makefile
1319@@ -0,0 +1,59 @@
1320+#
1321+# U-boot - Makefile
1322+#
1323+# Copyright (c) 2005-2007 Analog Device Inc.
1324+#
1325+# (C) Copyright 2000-2006
1326+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1327+#
1328+# See file CREDITS for list of people who contributed to this
1329+# project.
1330+#
1331+# This program is free software; you can redistribute it and/or
1332+# modify it under the terms of the GNU General Public License as
1333+# published by the Free Software Foundation; either version 2 of
1334+# the License, or (at your option) any later version.
1335+#
1336+# This program is distributed in the hope that it will be useful,
1337+# but WITHOUT ANY WARRANTY; without even the implied warranty of
1338+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1339+# GNU General Public License for more details.
1340+#
1341+# You should have received a copy of the GNU General Public License
1342+# along with this program; if not, write to the Free Software
1343+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1344+# MA 02111-1307 USA
1345+#
1346+
1347+include $(TOPDIR)/config.mk
1348+
1349+LIB = $(obj)lib$(BOARD).a
1350+
1351+COBJS := $(BOARD).o post-memory.o spi_flash.o cmd_bf537led.o nand.o
1352+#COBJS := $(BOARD).o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
1353+
1354+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
1355+OBJS := $(addprefix $(obj),$(COBJS))
1356+SOBJS := $(addprefix $(obj),$(SOBJS))
1357+
1358+$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
1359+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
1360+
1361+u-boot.lds: u-boot.lds.S
1362+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
1363+ mv -f $@.tmp $@
1364+
1365+clean:
1366+ rm -f $(SOBJS) $(OBJS)
1367+
1368+distclean: clean
1369+ rm -f $(LIB) core *.bak .depend
1370+
1371+#########################################################################
1372+
1373+# defines $(obj).depend target
1374+include $(SRCTREE)/rules.mk
1375+
1376+sinclude $(obj).depend
1377+
1378+#########################################################################
1379diff --git a/u-boot-1.1.6/board/Orbit3/Orbit3.c b/u-boot-1.1.6/board/Orbit3/Orbit3.c
1380new file mode 100644
1381index 0000000..b40b20c
1382--- /dev/null
1383+++ b/u-boot-1.1.6/board/Orbit3/Orbit3.c
1384@@ -0,0 +1,516 @@
1385+/*
1386+ * U-boot - Orbit3.c
1387+ *
1388+ * Copyright (c) 2008 Metrologic Instruments Inc.
1389+ * Copyright (c) 2005-2007 Analog Devices Inc.
1390+ *
1391+ * (C) Copyright 2000-2004
1392+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1393+ *
1394+ * See file CREDITS for list of people who contributed to this
1395+ * project.
1396+ *
1397+ * This program is free software; you can redistribute it and/or
1398+ * modify it under the terms of the GNU General Public License as
1399+ * published by the Free Software Foundation; either version 2 of
1400+ * the License, or (at your option) any later version.
1401+ *
1402+ * This program is distributed in the hope that it will be useful,
1403+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1404+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1405+ * GNU General Public License for more details.
1406+ *
1407+ * You should have received a copy of the GNU General Public License
1408+ * along with this program; if not, write to the Free Software
1409+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
1410+ * MA 02110-1301 USA
1411+ */
1412+
1413+#include <common.h>
1414+#include <config.h>
1415+#include <command.h>
1416+#include <asm/blackfin.h>
1417+#include <asm/io.h>
1418+#include <linux/etherdevice.h>
1419+
1420+#define POST_WORD_ADDR 0xFF903FFC
1421+
1422+int checkboard(void)
1423+{
1424+ printf("Board: Metrologic Genesis Decode Board\n");
1425+ printf(" Support: http://www.metrologic.com/\n");
1426+ return 0;
1427+}
1428+
1429+#if defined(CONFIG_BFIN_IDE)
1430+
1431+void cf_outb(unsigned char val, volatile unsigned char *addr)
1432+{
1433+ *(addr) = val;
1434+ SSYNC();
1435+}
1436+
1437+unsigned char cf_inb(volatile unsigned char *addr)
1438+{
1439+ volatile unsigned char c;
1440+
1441+ c = *(addr);
1442+ SSYNC();
1443+
1444+ return c;
1445+}
1446+
1447+void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
1448+{
1449+ int i;
1450+
1451+ for (i = 0; i < words; i++)
1452+ *(sect_buf + i) = *(addr);
1453+ SSYNC();
1454+}
1455+
1456+void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
1457+{
1458+ int i;
1459+
1460+ for (i = 0; i < words; i++)
1461+ *(addr) = *(sect_buf + i);
1462+ SSYNC();
1463+}
1464+#endif /* CONFIG_BFIN_IDE */
1465+
1466+long int initdram(int board_type)
1467+{
1468+ DECLARE_GLOBAL_DATA_PTR;
1469+#ifdef DEBUG
1470+ int brate;
1471+ char *tmp = getenv("baudrate");
1472+ brate = simple_strtoul(tmp, NULL, 16);
1473+ printf("Serial Port initialized with Baud rate = %x\n", brate);
1474+ printf("SDRAM attributes:\n");
1475+ printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
1476+ "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
1477+ 3, 3, 6, 2, 3);
1478+ printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
1479+ printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
1480+#endif
1481+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
1482+ gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
1483+ return CFG_MAX_RAM_SIZE;
1484+}
1485+
1486+int board_get_enetaddr(uchar *mac_addr)
1487+{
1488+#ifdef CFG_NO_FLASH
1489+# define USE_MAC_IN_FLASH 0
1490+#else
1491+# define USE_MAC_IN_FLASH 1
1492+#endif
1493+ if (USE_MAC_IN_FLASH) {
1494+ /* we cram the MAC in the last flash sector */
1495+ uchar *board_mac_addr = (uchar *)0x203F0000;
1496+
1497+ if (is_valid_ether_addr(board_mac_addr)) {
1498+ memcpy(mac_addr, board_mac_addr, 6);
1499+ return 0;
1500+ }
1501+ }
1502+
1503+ puts("Warning: Generating 'random' MAC address\n");
1504+
1505+ /* make something up */
1506+ const char s[] = __DATE__;
1507+ size_t i;
1508+ u32 cycles;
1509+ for (i = 0; i < 6; ++i) {
1510+ asm("%0 = CYCLES;" : "=r" (cycles));
1511+ mac_addr[i] = cycles ^ s[i];
1512+ }
1513+ mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */
1514+ return 0;
1515+}
1516+
1517+void board_reset(void)
1518+{ /* FIXME: Alex Au: Don't know if we need to use this workaround... */
1519+ /* workaround for weak pull ups on ssel */
1520+ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
1521+ bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10);
1522+ bfin_write_PORTFIO_SET(PF10);
1523+ udelay(1);
1524+ }
1525+}
1526+
1527+
1528+
1529+#ifdef CONFIG_METROLOGIC_IO_INIT
1530+
1531+int metrologic_io_init(void)
1532+{
1533+ /* Port F:
1534+
1535+ 0 (out) <<< Host RS232 TX >>>
1536+ 1 (in) <<< Host RS232 RX >>>
1537+ 2 (out) <<< White LED (PWM) >>> [l]
1538+ 3 (Out) <<< Blue LED (PWM) >>> [l]
1539+ 4 (out) BEEP [l]
1540+ 5 (out) Target [l]
1541+ 6 (out) cam_sync [l]
1542+ 7 (out) Force On [l]
1543+ 8 (in) <<< PPI_VSYNC >>> [later, input]
1544+ 9 (in) <<< PPI_HSYNC >>> [later, input]
1545+ 10 (out) <<< SPI_CS >>>
1546+ 11 (out) <<< SPI_MOSI >>>
1547+ 12 (in) <<< SPI_MISO >>>
1548+ 13 (out) <<< SPI_CLOCK >>>
1549+ 14 (out) SPI_WP [h]
1550+ 15 (in) <<< PPI_Clock >>> [later, input]
1551+
1552+ */
1553+
1554+ *pPORTF_FER = PF0|PF1|PF10|PF11|PF12|PF13; /* PPI enabled in image device driver */
1555+ *pPORTFIO_DIR |= PF4|PF5|PF6|PF7|PF14;
1556+ *pPORTFIO_DIR &= ~(PF2|PF3|PF8|PF9|PF15);
1557+ *pPORTFIO_INEN &= ~(PF2|PF3|PF4|PF5|PF6|PF7|PF8|PF9|PF14|PF15);
1558+ *pPORTFIO &= ~(PF4|PF5|PF6|PF7);
1559+ *pPORTFIO |= PF14;
1560+
1561+ /* Port G:
1562+
1563+ 0 (in) <<< PPI_Data >>> [later, input]
1564+ 1 (in) <<< PPI_Data >>> [later, input]
1565+ 2 (in) <<< PPI_Data >>> [later, input]
1566+ 3 (in) <<< PPI_Data >>> [later, input]
1567+ 4 (in) <<< PPI_Data >>> [later, input]
1568+ 5 (in) <<< PPI_Data >>> [later, input]
1569+ 6 (in) <<< PPI_Data >>> [later, input]
1570+ 7 (in) <<< PPI_Data >>> [later, input]
1571+ *8 (out) DEC_KB_PASS_EN(N) [h]
1572+ 9 (out) HOSTRTS ( Leave as input / output high until polarity is known )
1573+ *10 (out) LED_HIGH_V [h] (video low, snap-shot high) / (USB high)
1574+ *11 (out) RESET IF (active H) [l]
1575+ 12 (out) LED Voltage Enable [h]
1576+ 13 (in) Spare ? Yellow LED ?
1577+ 14 (out) BUF_PC_DATA_COL [h]
1578+ 15 (in) IF_BUSY_LT_PEN_DATA
1579+
1580+ */
1581+
1582+ *pPORTG_FER = 0;
1583+ *pPORTGIO_DIR = PG8|PG9|PG10|PG11|PG12|PG14;
1584+ *pPORTGIO_INEN = PG15;
1585+ *pPORTGIO |= PG8|PG9|PG10|PG12|PG14;
1586+ *pPORTGIO &= ~(PG11);
1587+
1588+ /* Port H:
1589+
1590+ *0 (in) BUF_PC_DATA_COL
1591+ *1 (out) DEC_KB_CLOCK_BASE [l]*
1592+ *2 (out) DEC_KB_DATA_BASE [l]*
1593+ *3 (out) DEC_PC_CLOCK_BASE [l]*
1594+ *4 (out) DEC_PC_DATA_BASE [l]*
1595+ *5 (out) DEC_LT_PEN_BASE [l]*
1596+ 6 (in) IR_IN
1597+ *7 (out) DEC_REQ_UC [l]*
1598+ 8 (in) HOST CTS
1599+ 9 (in) BUTTON
1600+ *10 (in) BUF_SPI_REQ
1601+ *11 (in) BUF_EP_FULL_PAUSE
1602+ *12 (out) Ocillator En. (Active high) [h]
1603+ 13 (out) DC Mode (Active low) [h]
1604+ *14 (out) NEAR_SEL [l]
1605+ *15 (in) DEC_DTR_FULL
1606+
1607+ */
1608+
1609+ *pPORTH_FER = 0;
1610+ *pPORTHIO_DIR = PH1|PH2|PH3|PH4|PH5|PH7|PH12|PH13|PH14;
1611+ *pPORTHIO_INEN = ~(PH1|PH2|PH3|PH4|PH5|PH7|PH12|PH13|PH14);
1612+ *pPORTHIO |= PH12|PH13;
1613+ *pPORTHIO &= ~(PH1|PH2|PH3|PH4|PH5|PH7|PH14);
1614+
1615+ __builtin_bfin_ssync();
1616+
1617+#if defined(DEBUG_METRO_IO)
1618+ printf("start Configure_Interface_IO()\r\n");
1619+#endif
1620+ Configure_Interface_IO();
1621+#if defined(DEBUG_METRO_IO)
1622+ printf("done Configure_Interface_IO()\r\n");
1623+#endif
1624+
1625+ return 0;
1626+
1627+}
1628+
1629+#endif /* CONFIG_METROLOGIC_IO_INIT */
1630+#if defined(CONFIG_MISC_INIT_R)
1631+/* miscellaneous platform dependent initialisations */
1632+int misc_init_r(void)
1633+{
1634+#ifndef CFG_NO_FLASH
1635+ /* we use the last sector for the MAC address / POST DXE */
1636+ extern flash_info_t flash_info[];
1637+ flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
1638+#endif
1639+
1640+#if defined(CONFIG_BFIN_IDE)
1641+#if defined(CONFIG_BFIN_TRUE_IDE)
1642+ /* Enable ATASEL when in True IDE mode */
1643+ printf("Using CF True IDE Mode\n");
1644+ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
1645+ udelay(1000);
1646+#elif defined(CONFIG_BFIN_CF_IDE)
1647+ /* Disable ATASEL when we're in Common Memory Mode */
1648+ printf("Using CF Common Memory Mode\n");
1649+ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
1650+ udelay(1000);
1651+#elif defined(CONFIG_BFIN_HDD_IDE)
1652+ printf("Using HDD IDE Mode\n");
1653+#endif
1654+ ide_init();
1655+#endif /* CONFIG_BFIN_IDE */
1656+ return 0;
1657+}
1658+#endif /* CONFIG_MISC_INIT_R */
1659+
1660+#ifdef CONFIG_POST
1661+#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
1662+/* Using sw10-PF5 as the hotkey */
1663+int post_hotkeys_pressed(void)
1664+{
1665+ return 0;
1666+}
1667+#else
1668+/* Using sw10-PF5 as the hotkey */
1669+int post_hotkeys_pressed(void)
1670+{
1671+ int delay = 3;
1672+ int i;
1673+ unsigned short value;
1674+
1675+ *pPORTF_FER &= ~PF5;
1676+ *pPORTFIO_DIR &= ~PF5;
1677+ *pPORTFIO_INEN |= PF5;
1678+
1679+ printf("########Press SW10 to enter Memory POST########: %2d ", delay);
1680+ while (delay--) {
1681+ for (i = 0; i < 100; i++) {
1682+ value = *pPORTFIO & PF5;
1683+ if (value != 0) {
1684+ break;
1685+ }
1686+ udelay(10000);
1687+ }
1688+ printf("\b\b\b%2d ", delay);
1689+ }
1690+ printf("\b\b\b 0");
1691+ printf("\n");
1692+ if (value == 0)
1693+ return 0;
1694+ else {
1695+ printf("Hotkey has been pressed, Enter POST . . . . . .\n");
1696+ return 1;
1697+ }
1698+}
1699+#endif
1700+#endif
1701+
1702+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
1703+void post_word_store(ulong a)
1704+{
1705+ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
1706+ *save_addr = a;
1707+}
1708+
1709+ulong post_word_load(void)
1710+{
1711+ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
1712+ return *save_addr;
1713+}
1714+#endif
1715+
1716+#ifdef CONFIG_POST
1717+int uart_post_test(int flags)
1718+{
1719+ return 0;
1720+}
1721+
1722+#define BLOCK_SIZE 0x10000
1723+#define VERIFY_ADDR 0x2000000
1724+extern int erase_block_flash(int);
1725+extern int write_data(long lStart, long lCount, uchar * pnData);
1726+int flash_post_test(int flags)
1727+{
1728+ unsigned short *pbuf, *temp;
1729+ int offset, n, i;
1730+ int value = 0;
1731+ int result = 0;
1732+ printf("\n");
1733+ pbuf = (unsigned short *)VERIFY_ADDR;
1734+ temp = pbuf;
1735+ for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
1736+ offset = (n - 7) * BLOCK_SIZE;
1737+ printf("--------Erase block:%2d..", n);
1738+ erase_block_flash(n);
1739+ printf("OK\r");
1740+ printf("--------Program block:%2d...", n);
1741+ write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
1742+ printf("OK\r");
1743+ printf("--------Verify block:%2d...", n);
1744+ for (i = 0; i < BLOCK_SIZE; i += 2) {
1745+ if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
1746+ *temp++) {
1747+ value = 1;
1748+ result = 1;
1749+ }
1750+ }
1751+ if (value)
1752+ printf("failed\n");
1753+ else
1754+ printf("OK %3d%%\r",
1755+ (int)(
1756+ (n + 1 -
1757+ FLASH_START_POST_BLOCK) *
1758+ 100 / (FLASH_END_POST_BLOCK -
1759+ FLASH_START_POST_BLOCK)));
1760+
1761+ temp = pbuf;
1762+ value = 0;
1763+ }
1764+ printf("\n");
1765+ if (result)
1766+ return -1;
1767+ else
1768+ return 0;
1769+}
1770+
1771+/****************************************************
1772+ * LED1 ---- PF6 LED2 ---- PF7 *
1773+ * LED3 ---- PF8 LED4 ---- PF9 *
1774+ * LED5 ---- PF10 LED6 ---- PF11 *
1775+ ****************************************************/
1776+int led_post_test(int flags)
1777+{
1778+ *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
1779+ *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
1780+ *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
1781+ *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
1782+ udelay(1000000);
1783+ printf("LED1 on");
1784+ *pPORTFIO |= PF6;
1785+ udelay(1000000);
1786+ printf("\b\b\b\b\b\b\b");
1787+ printf("LED2 on");
1788+ *pPORTFIO |= PF7;
1789+ udelay(1000000);
1790+ printf("\b\b\b\b\b\b\b");
1791+ printf("LED3 on");
1792+ *pPORTFIO |= PF8;
1793+ udelay(1000000);
1794+ printf("\b\b\b\b\b\b\b");
1795+ printf("LED4 on");
1796+ *pPORTFIO |= PF9;
1797+ udelay(1000000);
1798+ printf("\b\b\b\b\b\b\b");
1799+ printf("LED5 on");
1800+ *pPORTFIO |= PF10;
1801+ udelay(1000000);
1802+ printf("\b\b\b\b\b\b\b");
1803+ printf("lED6 on");
1804+ *pPORTFIO |= PF11;
1805+ printf("\b\b\b\b\b\b\b ");
1806+ return 0;
1807+}
1808+
1809+/************************************************
1810+ * SW10 ---- PF5 SW11 ---- PF4 *
1811+ * SW12 ---- PF3 SW13 ---- PF2 *
1812+ ************************************************/
1813+int button_post_test(int flags)
1814+{
1815+ int i, delay = 5;
1816+ unsigned short value = 0;
1817+ int result = 0;
1818+
1819+ *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
1820+ *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
1821+ *pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
1822+
1823+ printf("\n--------Press SW10: %2d ", delay);
1824+ while (delay--) {
1825+ for (i = 0; i < 100; i++) {
1826+ value = *pPORTFIO & PF5;
1827+ if (value != 0) {
1828+ break;
1829+ }
1830+ udelay(10000);
1831+ }
1832+ printf("\b\b\b%2d ", delay);
1833+ }
1834+ if (value != 0)
1835+ printf("\b\bOK");
1836+ else {
1837+ result = -1;
1838+ printf("\b\bfailed");
1839+ }
1840+
1841+ delay = 5;
1842+ printf("\n--------Press SW11: %2d ", delay);
1843+ while (delay--) {
1844+ for (i = 0; i < 100; i++) {
1845+ value = *pPORTFIO & PF4;
1846+ if (value != 0) {
1847+ break;
1848+ }
1849+ udelay(10000);
1850+ }
1851+ printf("\b\b\b%2d ", delay);
1852+ }
1853+ if (value != 0)
1854+ printf("\b\bOK");
1855+ else {
1856+ result = -1;
1857+ printf("\b\bfailed");
1858+ }
1859+
1860+ delay = 5;
1861+ printf("\n--------Press SW12: %2d ", delay);
1862+ while (delay--) {
1863+ for (i = 0; i < 100; i++) {
1864+ value = *pPORTFIO & PF3;
1865+ if (value != 0) {
1866+ break;
1867+ }
1868+ udelay(10000);
1869+ }
1870+ printf("\b\b\b%2d ", delay);
1871+ }
1872+ if (value != 0)
1873+ printf("\b\bOK");
1874+ else {
1875+ result = -1;
1876+ printf("\b\bfailed");
1877+ }
1878+
1879+ delay = 5;
1880+ printf("\n--------Press SW13: %2d ", delay);
1881+ while (delay--) {
1882+ for (i = 0; i < 100; i++) {
1883+ value = *pPORTFIO & PF2;
1884+ if (value != 0) {
1885+ break;
1886+ }
1887+ udelay(10000);
1888+ }
1889+ printf("\b\b\b%2d ", delay);
1890+ }
1891+ if (value != 0)
1892+ printf("\b\bOK");
1893+ else {
1894+ result = -1;
1895+ printf("\b\bfailed");
1896+ }
1897+ printf("\n");
1898+ return result;
1899+}
1900+#endif
1901diff --git a/u-boot-1.1.6/board/VuQuest2D/Makefile b/u-boot-1.1.6/board/VuQuest2D/Makefile
1902new file mode 100644
1903index 0000000..1a924d9
1904--- /dev/null
1905+++ b/u-boot-1.1.6/board/VuQuest2D/Makefile
1906@@ -0,0 +1,59 @@
1907+#
1908+# U-boot - Makefile
1909+#
1910+# Copyright (c) 2005-2008 Analog Device Inc.
1911+#
1912+# (C) Copyright 2000-2006
1913+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1914+#
1915+# See file CREDITS for list of people who contributed to this
1916+# project.
1917+#
1918+# This program is free software; you can redistribute it and/or
1919+# modify it under the terms of the GNU General Public License as
1920+# published by the Free Software Foundation; either version 2 of
1921+# the License, or (at your option) any later version.
1922+#
1923+# This program is distributed in the hope that it will be useful,
1924+# but WITHOUT ANY WARRANTY; without even the implied warranty of
1925+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1926+# GNU General Public License for more details.
1927+#
1928+# You should have received a copy of the GNU General Public License
1929+# along with this program; if not, write to the Free Software
1930+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1931+# MA 02111-1307 USA
1932+#
1933+
1934+include $(TOPDIR)/config.mk
1935+
1936+LIB = $(obj)lib$(BOARD).a
1937+
1938+#COBJS := $(BOARD).o spi_flash.o video.o
1939+COBJS := $(BOARD).o spi.o video.o
1940+
1941+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
1942+OBJS := $(addprefix $(obj),$(COBJS))
1943+SOBJS := $(addprefix $(obj),$(SOBJS))
1944+
1945+$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
1946+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
1947+
1948+u-boot.lds: u-boot.lds.S
1949+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
1950+ mv -f $@.tmp $@
1951+
1952+clean:
1953+ rm -f $(SOBJS) $(OBJS)
1954+
1955+distclean: clean
1956+ rm -f $(LIB) core *.bak .depend
1957+
1958+#########################################################################
1959+
1960+# defines $(obj).depend target
1961+include $(SRCTREE)/rules.mk
1962+
1963+sinclude $(obj).depend
1964+
1965+#########################################################################
1966diff --git a/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.c b/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.c
1967new file mode 100644
1968index 0000000..04647d7
1969--- /dev/null
1970+++ b/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.c
1971@@ -0,0 +1,418 @@
1972+/*
1973+ * U-boot - stamp.c STAMP board specific routines
1974+ *
1975+ * Copyright (c) 2005-2007 Analog Devices Inc.
1976+ *
1977+ * (C) Copyright 2000-2004
1978+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1979+ *
1980+ * See file CREDITS for list of people who contributed to this
1981+ * project.
1982+ *
1983+ * This program is free software; you can redistribute it and/or
1984+ * modify it under the terms of the GNU General Public License as
1985+ * published by the Free Software Foundation; either version 2 of
1986+ * the License, or (at your option) any later version.
1987+ *
1988+ * This program is distributed in the hope that it will be useful,
1989+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1990+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1991+ * GNU General Public License for more details.
1992+ *
1993+ * You should have received a copy of the GNU General Public License
1994+ * along with this program; if not, write to the Free Software
1995+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
1996+ * MA 02110-1301 USA
1997+ */
1998+
1999+#include <common.h>
2000+#include <asm/blackfin.h>
2001+#include <asm/io.h>
2002+#include <asm/mach-common/bits/ebiu.h>
2003+#include "VuQuest2D.h"
2004+#include "Metrologic_Hardware.h"
2005+
2006+#define STATUS_LED_OFF 0
2007+#define STATUS_LED_ON 1
2008+
2009+#ifdef CONFIG_SHOW_BOOT_PROGRESS
2010+# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
2011+#else
2012+# define SHOW_BOOT_PROGRESS(arg)
2013+#endif
2014+
2015+#ifdef CONFIG_METROLOGIC_IO_INIT
2016+void set_VQ_default_io(void);
2017+#endif
2018+
2019+extern void Configure_Interface_IO(void);
2020+extern void Configure_RTS_Pin(void);
2021+extern int get_pfx_level(int pf_num);
2022+
2023+#if (CONFIG_METROLOGIC_VQ2D_REV > 1)
2024+
2025+int
2026+Read_VQ_AtoD(void)
2027+{
2028+#define VQ2D_RTS_PIN 6
2029+ int fio_dir = *pFIO_DIR;
2030+ int fio_ilen = *pFIO_INEN;
2031+ int pf6_level;
2032+
2033+ *pFIO_DIR &= ~(PF6);
2034+ *pFIO_INEN |= PF6;
2035+
2036+ pf6_level = get_pfx_level(VQ2D_RTS_PIN);
2037+
2038+ *pFIO_DIR = fio_dir;
2039+ *pFIO_INEN = fio_ilen;
2040+
2041+ if (pf6_level == 0)
2042+ { /* RS232 */
2043+ return (241 + 255) / 2;
2044+ }
2045+ else
2046+ { /* USB */
2047+ return (113 + 127) / 2;
2048+ }
2049+}
2050+
2051+void
2052+Configure_VQ2D_Interface_IO(int interface_board)
2053+{
2054+ if (interface_board == RS232_BOARD)
2055+ {
2056+#define PWR_DWN_PIN 9
2057+#define PWR_ON_PIN 5
2058+ Configure_RTS_Pin();
2059+
2060+ *pFIO_DIR |= PF9;
2061+ *pFIO_INEN &= ~PF9;
2062+ *pFIO_FLAG_D |= PF5;
2063+ *pFIO_FLAG_D &= ~PF9; /* PWR_DWN will be turned off at img.ko */
2064+ }
2065+ else
2066+ { /* USB board */
2067+#define SLAVE_BUSY_PIN 9
2068+
2069+ *pFIO_DIR &= ~(PF9);
2070+ }
2071+
2072+ /* power down pin handled by silabs */
2073+}
2074+
2075+#endif /* #if (CONFIG_METROLOGIC_VQ2D_REV > 1) */
2076+
2077+int checkboard(void)
2078+{
2079+ printf("CPU: ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28);
2080+ printf("Board: Metrologic VuQuest2D decode board\n");
2081+ printf(" Support: http://www.metrologic.com/\n");
2082+ return 0;
2083+}
2084+
2085+long int initdram(int board_type)
2086+{
2087+ DECLARE_GLOBAL_DATA_PTR;
2088+#ifdef DEBUG
2089+ printf("SDRAM attributes:\n");
2090+ printf
2091+ (" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
2092+ "CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11),
2093+ (SDRAM_tRAS >> 6), (SDRAM_tWR >> 19), (SDRAM_CL >> 2));
2094+ printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
2095+ printf("Bank size = %d MB\n", 128);
2096+#endif
2097+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
2098+ gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
2099+ return (gd->bd->bi_memsize);
2100+}
2101+
2102+void swap_to(int device_id)
2103+{
2104+#ifdef CONFIG_METROLOGIC_IO_INIT
2105+ if (device_id == FLASH)
2106+ {
2107+ bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF2);
2108+ SSYNC();
2109+ bfin_write_FIO_FLAG_S(PF2);
2110+ SSYNC();
2111+ }
2112+#else
2113+ bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0);
2114+ SSYNC();
2115+ bfin_write_FIO_FLAG_C(PF1);
2116+ if (device_id == ETHERNET)
2117+ bfin_write_FIO_FLAG_S(PF0);
2118+ else if (device_id == FLASH)
2119+ bfin_write_FIO_FLAG_C(PF0);
2120+ else
2121+ printf("Unknown device to switch\n");
2122+ SSYNC();
2123+#endif
2124+}
2125+
2126+#if defined(CONFIG_MISC_INIT_R)
2127+/* miscellaneous platform dependent initialisations */
2128+int misc_init_r(void)
2129+{
2130+ int i;
2131+ int cf_stat = 0;
2132+
2133+ /* Check whether CF card is inserted */
2134+ *pFIO_EDGE = FIO_EDGE_CF_BITS;
2135+ *pFIO_POLAR = FIO_POLAR_CF_BITS;
2136+ for (i = 0; i < 0x300; i++)
2137+ asm("nop;");
2138+
2139+ if ((*pFIO_FLAG_S) & CF_STAT_BITS) {
2140+ cf_stat = 0;
2141+ } else {
2142+ cf_stat = 1;
2143+ }
2144+
2145+ *pFIO_EDGE = FIO_EDGE_BITS;
2146+ *pFIO_POLAR = FIO_POLAR_BITS;
2147+
2148+ if (cf_stat) {
2149+ printf("Booting from COMPACT flash\n");
2150+
2151+ for (i = 0; i < 0x1000; i++)
2152+ asm("nop;");
2153+ for (i = 0; i < 0x1000; i++)
2154+ asm("nop;");
2155+ for (i = 0; i < 0x1000; i++)
2156+ asm("nop;");
2157+
2158+ serial_setbrg();
2159+ ide_init();
2160+
2161+ setenv("bootargs", "");
2162+ setenv("bootcmd",
2163+ "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
2164+ } else {
2165+ printf("Booting from FLASH\n");
2166+ }
2167+ return 0;
2168+}
2169+#endif
2170+
2171+#ifdef CONFIG_STAMP_CF
2172+
2173+void cf_outb(unsigned char val, volatile unsigned char *addr)
2174+{
2175+ /*
2176+ * Set PF1 PF0 respectively to 0 1 to divert address
2177+ * to the expansion memory banks
2178+ */
2179+ *pFIO_FLAG_S = CF_PF0;
2180+ *pFIO_FLAG_C = CF_PF1;
2181+ SSYNC();
2182+
2183+ *(addr) = val;
2184+ SSYNC();
2185+
2186+ /* Setback PF1 PF0 to 0 0 to address external
2187+ * memory banks */
2188+ *(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0;
2189+ SSYNC();
2190+}
2191+
2192+unsigned char cf_inb(volatile unsigned char *addr)
2193+{
2194+ volatile unsigned char c;
2195+
2196+ *pFIO_FLAG_S = CF_PF0;
2197+ *pFIO_FLAG_C = CF_PF1;
2198+ SSYNC();
2199+
2200+ c = *(addr);
2201+ SSYNC();
2202+
2203+ *pFIO_FLAG_C = CF_PF1_PF0;
2204+ SSYNC();
2205+
2206+ return c;
2207+}
2208+
2209+void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
2210+{
2211+ int i;
2212+
2213+ *pFIO_FLAG_S = CF_PF0;
2214+ *pFIO_FLAG_C = CF_PF1;
2215+ SSYNC();
2216+
2217+ for (i = 0; i < words; i++) {
2218+ *(sect_buf + i) = *(addr);
2219+ SSYNC();
2220+ }
2221+
2222+ *pFIO_FLAG_C = CF_PF1_PF0;
2223+ SSYNC();
2224+}
2225+
2226+void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
2227+{
2228+ int i;
2229+
2230+ *pFIO_FLAG_S = CF_PF0;
2231+ *pFIO_FLAG_C = CF_PF1;
2232+ SSYNC();
2233+
2234+ for (i = 0; i < words; i++) {
2235+ *(addr) = *(sect_buf + i);
2236+ SSYNC();
2237+ }
2238+
2239+ *pFIO_FLAG_C = CF_PF1_PF0;
2240+ SSYNC();
2241+}
2242+#endif
2243+
2244+#ifdef CONFIG_METROLOGIC_IO_INIT
2245+
2246+void set_VQ_default_io(void)
2247+{
2248+ /* Port F:
2249+ 0 - (Out?) I2C Clock
2250+ 1 - (In?) I2C Data
2251+ 2 - (Out) SPI chip select
2252+ 3 - (In?) nWake / PPI_FS3
2253+ 4 - (Out) Target Pin
2254+ 5 - (Out) nGoodRead
2255+ 6 - (Out) RTS
2256+ 7 - (In) CTS
2257+ 8 - (Out) Minflash / IllumOn
2258+ 9 - (Out?) nPowerDown (RS232) / (In) Slave_Busy (USB)
2259+ 10 - (Out) CamSync
2260+ 11 - (In) nTrigger (Input to decode)
2261+
2262+ 12 - (In) PPI Data
2263+ 13 - (In) PPI Data
2264+ 14 - (In) PPI Data
2265+ 15 - (In) PPI Data
2266+
2267+ */
2268+
2269+
2270+
2271+
2272+
2273+#if (CONFIG_METROLOGIC_VQ2D_REV > 1)
2274+ *pFIO_DIR |= PF0|PF1|PF2|PF4|PF5|PF8|PF10;
2275+ *pFIO_DIR &= ~(PF3 | PF6|PF9 | PF12|PF13|PF14|PF15);
2276+#else
2277+ *pFIO_DIR |= PF0|PF1|PF2|PF4|PF5|PF8|PF9|PF10;
2278+ *pFIO_DIR &= ~(PF3 | PF12|PF13|PF14|PF15);
2279+#endif
2280+
2281+ *pFIO_EDGE = 0;
2282+
2283+
2284+
2285+#if (CONFIG_METROLOGIC_VQ2D_REV > 1)
2286+ *pFIO_INEN &= ~(PF0|PF1|PF2 | PF4|PF5|PF8|PF10 | PF12|PF13|PF14|PF15);
2287+ *pFIO_INEN |= PF3 | PF6 | PF7 | PF9 | PF11;
2288+#else
2289+ *pFIO_INEN &= ~(PF0|PF1|PF2 | PF4|PF5|PF6|PF8|PF9|PF10);
2290+ *pFIO_INEN |= PF3 | PF7 | PF11;
2291+#endif
2292+
2293+
2294+
2295+
2296+
2297+
2298+
2299+
2300+
2301+
2302+ *pFIO_POLAR = 0;
2303+ *pFIO_FLAG_D &= ~(PF0|PF1 | PF4|PF8|PF10);
2304+#if (CONFIG_METROLOGIC_VQ2D_REV > 1)
2305+ *pFIO_FLAG_D |= PF2;
2306+ *pFIO_FLAG_D &= ~PF5;
2307+#else
2308+ *pFIO_FLAG_D |= PF2|PF5|PF9;
2309+#endif
2310+
2311+
2312+ __builtin_bfin_ssync();
2313+}
2314+
2315+int metrologic_io_init(void)
2316+{
2317+ set_VQ_default_io();
2318+
2319+ Configure_Interface_IO();
2320+
2321+
2322+
2323+ return 0;
2324+
2325+
2326+
2327+}
2328+
2329+#endif /* CONFIG_METROLOGIC_IO_INIT */
2330+
2331+void stamp_led_set(int LED1, int LED2, int LED3)
2332+{
2333+#ifndef CONFIG_METROLOGIC_IO_INIT
2334+ *pFIO_INEN &= ~(PF2 | PF3 | PF4);
2335+ *pFIO_DIR |= (PF2 | PF3 | PF4);
2336+
2337+ if (LED1 == STATUS_LED_OFF)
2338+ *pFIO_FLAG_S = PF2;
2339+ else
2340+ *pFIO_FLAG_C = PF2;
2341+ if (LED2 == STATUS_LED_OFF)
2342+ *pFIO_FLAG_S = PF3;
2343+ else
2344+ *pFIO_FLAG_C = PF3;
2345+ if (LED3 == STATUS_LED_OFF)
2346+ *pFIO_FLAG_S = PF4;
2347+ else
2348+ *pFIO_FLAG_C = PF4;
2349+ SSYNC();
2350+#endif
2351+}
2352+
2353+void show_boot_progress(int status)
2354+{
2355+ switch (status) {
2356+ case 1:
2357+ stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
2358+ break;
2359+ case 2:
2360+ stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
2361+ break;
2362+ case 3:
2363+ stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
2364+ break;
2365+ case 4:
2366+ stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
2367+ break;
2368+ case 5:
2369+ case 6:
2370+ stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
2371+ break;
2372+ case 7:
2373+ case 8:
2374+ stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
2375+ break;
2376+ case 9:
2377+ case 10:
2378+ case 11:
2379+ case 12:
2380+ case 13:
2381+ case 14:
2382+ case 15:
2383+ stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_OFF);
2384+ break;
2385+ default:
2386+ stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
2387+ break;
2388+ }
2389+}
2390diff --git a/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.h b/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.h
2391new file mode 100644
2392index 0000000..96f7aa7
2393--- /dev/null
2394+++ b/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.h
2395@@ -0,0 +1,53 @@
2396+/*
2397+ * U-boot - stamp.h
2398+ *
2399+ * Copyright (c) 2005-2007 Analog Devices Inc.
2400+ *
2401+ * (C) Copyright 2000-2004
2402+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
2403+ *
2404+ * See file CREDITS for list of people who contributed to this
2405+ * project.
2406+ *
2407+ * This program is free software; you can redistribute it and/or
2408+ * modify it under the terms of the GNU General Public License as
2409+ * published by the Free Software Foundation; either version 2 of
2410+ * the License, or (at your option) any later version.
2411+ *
2412+ * This program is distributed in the hope that it will be useful,
2413+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2414+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2415+ * GNU General Public License for more details.
2416+ *
2417+ * You should have received a copy of the GNU General Public License
2418+ * along with this program; if not, write to the Free Software
2419+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
2420+ * MA 02110-1301 USA
2421+ */
2422+
2423+#ifndef __VUQUEST2D_H__
2424+#define __VUQUEST2D_H__
2425+
2426+extern void init_Flags(void);
2427+
2428+extern volatile unsigned long *ambctl0;
2429+extern volatile unsigned long *ambctl1;
2430+extern volatile unsigned long *amgctl;
2431+
2432+/* Definitions used in Compact Flash Boot support */
2433+#define FIO_EDGE_CF_BITS 0x0000
2434+#define FIO_POLAR_CF_BITS 0x0000
2435+#define FIO_EDGE_BITS 0x1E0
2436+#define FIO_POLAR_BITS 0x160
2437+
2438+/* Compact flash status bits in status register */
2439+#define CF_STAT_BITS 0x00000060
2440+
2441+/* CF Flags used to switch between expansion and external
2442+ * memory banks
2443+ */
2444+#define CF_PF0 0x0001
2445+#define CF_PF1 0x0002
2446+#define CF_PF1_PF0 0x0003
2447+
2448+#endif
2449diff --git a/u-boot-1.1.6/board/VuQuest2D/config.mk b/u-boot-1.1.6/board/VuQuest2D/config.mk
2450new file mode 100644
2451index 0000000..2afee57
2452--- /dev/null
2453+++ b/u-boot-1.1.6/board/VuQuest2D/config.mk
2454@@ -0,0 +1,15 @@
2455+#
2456+# Copyright (c) 2005-2008 Analog Device Inc.
2457+#
2458+# (C) Copyright 2001
2459+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
2460+#
2461+# Licensed under the GPL-2 or later.
2462+#
2463+
2464+# This is not actually used for Blackfin boards so do not change it
2465+#TEXT_BASE = do-not-use-me
2466+
2467+# Set some default LDR flags based on boot mode.
2468+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
2469+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
2470diff --git a/u-boot-1.1.6/board/VuQuest2D/spi.c b/u-boot-1.1.6/board/VuQuest2D/spi.c
2471new file mode 100644
2472index 0000000..908d4e1
2473--- /dev/null
2474+++ b/u-boot-1.1.6/board/VuQuest2D/spi.c
2475@@ -0,0 +1,533 @@
2476+/****************************************************************************
2477+ * SPI flash driver for M25P64
2478+ ****************************************************************************/
2479+#include <common.h>
2480+#include <linux/ctype.h>
2481+#include <asm/mach-common/bits/spi.h>
2482+
2483+#if defined(CONFIG_SPI)
2484+
2485+//Application definitions
2486+
2487+#define NUM_SECTORS 128 /* number of sectors */
2488+#define SECTOR_SIZE 0x10000
2489+#define NOP_NUM 1000
2490+
2491+#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL) //Settings to the SPI_CTL
2492+#define TIMOD01 (0x01) //stes the SPI to work with core instructions
2493+
2494+//Flash commands
2495+#define SPI_WREN (0x06) //Set Write Enable Latch
2496+#define SPI_WRDI (0x04) //Reset Write Enable Latch
2497+#define SPI_RDSR (0x05) //Read Status Register
2498+#define SPI_WRSR (0x01) //Write Status Register
2499+#define SPI_READ (0x03) //Read data from memory
2500+#define SPI_FAST_READ (0x0B) //Read data from memory
2501+#define SPI_PP (0x02) //Program Data into memory
2502+#define SPI_SE (0xD8) //Erase one sector in memory
2503+#define SPI_BE (0xC7) //Erase all memory
2504+#define WIP (0x1) //Check the write in progress bit of the SPI status register
2505+#define WEL (0x2) //Check the write enable bit of the SPI status register
2506+
2507+#define TIMEOUT 350000000
2508+
2509+typedef enum
2510+{
2511+ NO_ERR,
2512+ POLL_TIMEOUT,
2513+ INVALID_SECTOR,
2514+ INVALID_BLOCK,
2515+}ERROR_CODE;
2516+
2517+
2518+void spi_init_f (void);
2519+void spi_init_r (void);
2520+ssize_t spi_read (uchar *, int, uchar *, int);
2521+ssize_t spi_write (uchar *, int, uchar *, int);
2522+
2523+char ReadStatusRegister(void);
2524+void Wait_For_SPIF(void);
2525+void SetupSPI( const int spi_setting );
2526+void SPI_OFF(void);
2527+void SendSingleCommand( const int iCommand );
2528+
2529+ERROR_CODE GetSectorNumber( unsigned long ulOffset, int *pnSector );
2530+ERROR_CODE EraseBlock( int nBlock );
2531+ERROR_CODE ReadData( unsigned long ulStart, long lCount,int *pnData );
2532+ERROR_CODE WriteData( unsigned long ulStart, long lCount, int *pnData );
2533+ERROR_CODE Wait_For_Status( char Statusbit );
2534+ERROR_CODE Wait_For_WEL(void);
2535+
2536+/* -------------------
2537+ * Variables
2538+ * ------------------- */
2539+
2540+/* **************************************************************************
2541+ *
2542+ * Function: spi_init_f
2543+ *
2544+ * Description: Init SPI-Controller (ROM part)
2545+ *
2546+ * return: ---
2547+ *
2548+ * *********************************************************************** */
2549+void spi_init_f (void)
2550+{
2551+}
2552+
2553+/* **************************************************************************
2554+ *
2555+ * Function: spi_init_r
2556+ *
2557+ * Description: Init SPI-Controller (RAM part) -
2558+ * The malloc engine is ready and we can move our buffers to
2559+ * normal RAM
2560+ *
2561+ * return: ---
2562+ *
2563+ * *********************************************************************** */
2564+void spi_init_r (void)
2565+{
2566+ return;
2567+}
2568+
2569+/****************************************************************************
2570+ * Function: spi_write
2571+ **************************************************************************** */
2572+ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
2573+{
2574+ unsigned long offset;
2575+ int start_block,end_block;
2576+ int start_byte,end_byte;
2577+ ERROR_CODE result = NO_ERR;
2578+ uchar temp[SECTOR_SIZE];
2579+ int i,num;
2580+
2581+ offset = addr[0]<<16 | addr[1] <<8 | addr[2];
2582+ /* Get the start block number */
2583+ GetSectorNumber(offset, &start_block);
2584+ /* Get the end block number */
2585+ GetSectorNumber(offset + len, &end_block);
2586+
2587+ for(num = start_block;num <= end_block;num ++){
2588+ ReadData(num*SECTOR_SIZE,SECTOR_SIZE,(int *)temp);
2589+ start_byte = num*SECTOR_SIZE;
2590+ end_byte = (num+1) * SECTOR_SIZE -1;
2591+ if(start_byte < offset) start_byte = offset;
2592+ if( end_byte > (offset+len)) end_byte = (offset+len-1);
2593+ for(i=start_byte;i<=end_byte;i++)
2594+ temp[i-num*SECTOR_SIZE] = buffer[i - offset];
2595+ EraseBlock(num);
2596+ result = WriteData(num*SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
2597+ if(result != NO_ERR)
2598+ return 0;
2599+ printf(".");
2600+ }
2601+ return len;
2602+}
2603+
2604+/****************************************************************************
2605+ * Function: spi_read
2606+ **************************************************************************** */
2607+ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
2608+{
2609+ unsigned long offset;
2610+ offset = addr[0]<<16 | addr[1] <<8 | addr[2];
2611+ ReadData ( offset, len, (int *)buffer );
2612+ return len;
2613+}
2614+
2615+void SendSingleCommand( const int iCommand )
2616+{
2617+ unsigned short dummy;
2618+
2619+ /*turns on the SPI in single write mode*/
2620+ SetupSPI( (COMMON_SPI_SETTINGS|TIMOD01) );
2621+
2622+ /*sends the actual command to the SPI TX register*/
2623+ *pSPI_TDBR = iCommand;
2624+ __builtin_bfin_ssync();
2625+
2626+ /*The SPI status register will be polled to check the SPIF bit*/
2627+ Wait_For_SPIF();
2628+
2629+ dummy = *pSPI_RDBR;
2630+
2631+ /*The SPI will be turned off*/
2632+ SPI_OFF();
2633+
2634+}
2635+
2636+void SetupSPI( const int spi_setting )
2637+{
2638+
2639+ if(icache_status()||dcache_status())
2640+ udelay(CONFIG_CCLK_HZ/50000000);
2641+ /*sets up the PF2 to be the slave select of the SPI */
2642+ *pSPI_FLG = 0xFB04;
2643+ *pSPI_BAUD = CONFIG_SPI_BAUD;
2644+ *pSPI_CTL = spi_setting;
2645+ __builtin_bfin_ssync();
2646+}
2647+
2648+void SPI_OFF(void)
2649+{
2650+
2651+ *pSPI_CTL = 0x0400; /* disable SPI*/
2652+ *pSPI_FLG = 0;
2653+ *pSPI_BAUD = 0;
2654+ __builtin_bfin_ssync();
2655+ udelay(CONFIG_CCLK_HZ/50000000);
2656+
2657+}
2658+
2659+void Wait_For_SPIF(void)
2660+{
2661+ unsigned short dummyread;
2662+ while( (*pSPI_STAT&TXS));
2663+ while(!(*pSPI_STAT&SPIF));
2664+ while(!(*pSPI_STAT&RXS));
2665+ dummyread = *pSPI_RDBR; // Read dummy to empty the receive register
2666+
2667+}
2668+
2669+ERROR_CODE Wait_For_WEL(void)
2670+{
2671+ int i;
2672+ char status_register = 0;
2673+ ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash*/
2674+
2675+ for(i = 0; i < TIMEOUT; i++)
2676+ {
2677+ status_register = ReadStatusRegister();
2678+ if( (status_register & WEL) )
2679+ {
2680+ ErrorCode = NO_ERR; /* tells us if there was an error erasing flash*/
2681+ break;
2682+ }
2683+ ErrorCode = POLL_TIMEOUT; /* Time out error*/
2684+ };
2685+
2686+ return ErrorCode;
2687+}
2688+
2689+ERROR_CODE Wait_For_Status( char Statusbit )
2690+{
2691+ int i;
2692+ char status_register = 0xFF;
2693+ ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
2694+
2695+ for(i = 0; i < TIMEOUT; i++)
2696+ {
2697+ status_register = ReadStatusRegister();
2698+ if( !(status_register & Statusbit) )
2699+ {
2700+ ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
2701+ break;
2702+ }
2703+ ErrorCode = POLL_TIMEOUT; /* Time out error */
2704+ };
2705+
2706+
2707+ return ErrorCode;
2708+}
2709+
2710+
2711+char ReadStatusRegister(void)
2712+{
2713+ char status_register = 0;
2714+
2715+ SetupSPI( (COMMON_SPI_SETTINGS|TIMOD01) ); /* Turn on the SPI */
2716+
2717+ *pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */
2718+ __builtin_bfin_ssync();
2719+ Wait_For_SPIF(); /*wait until the instruction has been sent*/
2720+ *pSPI_TDBR = 0; /*send dummy to receive the status register*/
2721+ __builtin_bfin_ssync();
2722+ Wait_For_SPIF(); /*wait until the data has been sent*/
2723+ status_register = *pSPI_RDBR; /*read the status register*/
2724+
2725+ SPI_OFF(); /* Turn off the SPI */
2726+
2727+ return status_register;
2728+}
2729+
2730+ERROR_CODE GetSectorNumber( unsigned long ulOffset, int *pnSector )
2731+{
2732+ int nSector = 0;
2733+ ERROR_CODE ErrorCode = NO_ERR;
2734+
2735+ if(ulOffset > (NUM_SECTORS*0x10000 -1)){
2736+ ErrorCode = INVALID_SECTOR;
2737+ return ErrorCode;
2738+ }
2739+
2740+ nSector = (int)ulOffset/0x10000;
2741+ *pnSector = nSector;
2742+
2743+ // ok
2744+ return ErrorCode;
2745+}
2746+
2747+ERROR_CODE EraseBlock( int nBlock )
2748+{
2749+ unsigned long ulSectorOff = 0x0, ShiftValue;
2750+ ERROR_CODE ErrorCode = NO_ERR;
2751+
2752+
2753+ // if the block is invalid just return
2754+ if ( (nBlock < 0) || (nBlock > NUM_SECTORS) )
2755+ {
2756+ ErrorCode = INVALID_BLOCK; // tells us if there was an error erasing flash
2757+ return ErrorCode;
2758+ }
2759+
2760+ // figure out the offset of the block in flash
2761+ if ( (nBlock >= 0) && (nBlock < NUM_SECTORS) )
2762+ {
2763+ ulSectorOff = (nBlock * SECTOR_SIZE);
2764+
2765+ }
2766+ else
2767+ {
2768+ ErrorCode = INVALID_BLOCK; // tells us if there was an error erasing flash
2769+ return ErrorCode;
2770+ }
2771+
2772+ // A write enable instruction must previously have been executed
2773+ SendSingleCommand(SPI_WREN);
2774+
2775+ //The status register will be polled to check the write enable latch "WREN"
2776+ ErrorCode = Wait_For_WEL();
2777+
2778+ if( POLL_TIMEOUT == ErrorCode )
2779+ {
2780+ printf("SPI Erase block error\n");
2781+ return ErrorCode;
2782+ }
2783+ else
2784+
2785+
2786+ //Turn on the SPI to send single commands
2787+ SetupSPI( (COMMON_SPI_SETTINGS|TIMOD01) );
2788+
2789+ // Send the erase block command to the flash followed by the 24 address
2790+ // to point to the start of a sector.
2791+ *pSPI_TDBR = SPI_SE;
2792+ __builtin_bfin_ssync();
2793+ Wait_For_SPIF();
2794+ ShiftValue = (ulSectorOff >> 16); // Send the highest byte of the 24 bit address at first
2795+ *pSPI_TDBR = ShiftValue;
2796+ __builtin_bfin_ssync();
2797+ Wait_For_SPIF(); // Wait until the instruction has been sent
2798+ ShiftValue = (ulSectorOff >> 8); // Send the middle byte of the 24 bit address at second
2799+ *pSPI_TDBR = ShiftValue;
2800+ __builtin_bfin_ssync();
2801+ Wait_For_SPIF(); // Wait until the instruction has been sent
2802+ *pSPI_TDBR = ulSectorOff; // Send the lowest byte of the 24 bit address finally
2803+ __builtin_bfin_ssync();
2804+ Wait_For_SPIF(); // Wait until the instruction has been sent
2805+
2806+ //Turns off the SPI
2807+ SPI_OFF();
2808+
2809+ // Poll the status register to check the Write in Progress bit
2810+ // Sector erase takes time
2811+ ErrorCode = Wait_For_Status(WIP);
2812+
2813+ // block erase should be complete
2814+ return ErrorCode;
2815+}
2816+
2817+/*****************************************************************************
2818+* ERROR_CODE ReadData()
2819+*
2820+* Read a value from flash for verify purpose
2821+*
2822+* Inputs: unsigned long ulStart - holds the SPI start address
2823+* int pnData - pointer to store value read from flash
2824+* long lCount - number of elements to read
2825+***************************************************************************** */
2826+ERROR_CODE ReadData( unsigned long ulStart, long lCount,int *pnData )
2827+{
2828+ unsigned long ShiftValue;
2829+ char *cnData,ReadValue;
2830+ int i;
2831+
2832+ cnData = (char *)pnData; /* Pointer cast to be able to increment byte wise */
2833+
2834+ // Start SPI interface
2835+ SetupSPI( (COMMON_SPI_SETTINGS|TIMOD01) );
2836+
2837+#ifdef CONFIG_SERIAL_BF537_USE_FAST_READ
2838+ *pSPI_TDBR = SPI_FAST_READ; // Send the read command to SPI device
2839+#else
2840+ *pSPI_TDBR = SPI_READ; // Send the read command to SPI device
2841+#endif
2842+ __builtin_bfin_ssync();
2843+ Wait_For_SPIF(); // Wait until the instruction has been sent
2844+ ShiftValue = (ulStart >> 16); // Send the highest byte of the 24 bit address at first
2845+ *pSPI_TDBR = ShiftValue; // Send the byte to the SPI device
2846+ __builtin_bfin_ssync();
2847+ Wait_For_SPIF(); // Wait until the instruction has been sent
2848+ ShiftValue = (ulStart >> 8); // Send the middle byte of the 24 bit address at second
2849+ *pSPI_TDBR = ShiftValue; // Send the byte to the SPI device
2850+ __builtin_bfin_ssync();
2851+ Wait_For_SPIF(); // Wait until the instruction has been sent
2852+ *pSPI_TDBR = ulStart; // Send the lowest byte of the 24 bit address finally
2853+ __builtin_bfin_ssync();
2854+ Wait_For_SPIF(); // Wait until the instruction has been sent
2855+
2856+#ifdef CONFIG_SERIAL_BF537_USE_FAST_READ
2857+ *pSPI_TDBR = 0; // Send dummy for FAST_READ
2858+ __builtin_bfin_ssync();
2859+ Wait_For_SPIF(); // Wait until the instruction has been sent
2860+#endif
2861+
2862+ // After the SPI device address has been placed on the MOSI pin the data can be
2863+ // received on the MISO pin.
2864+ for (i=0; i<lCount; i++)
2865+ {
2866+ *pSPI_TDBR = 0; //send dummy
2867+ __builtin_bfin_ssync();
2868+ while(!(*pSPI_STAT&RXS));
2869+ *cnData++ = *pSPI_RDBR; //read
2870+
2871+ if((i>=SECTOR_SIZE)&&(i%SECTOR_SIZE == 0))
2872+ printf(".");
2873+ }
2874+
2875+ SPI_OFF(); // Turn off the SPI
2876+
2877+ return NO_ERR;
2878+}
2879+
2880+ERROR_CODE WriteFlash ( unsigned long ulStartAddr, long lTransferCount, int *iDataSource, long *lWriteCount )
2881+{
2882+
2883+ unsigned long ulWAddr;
2884+ long lWTransferCount = 0;
2885+ int i;
2886+ char iData;
2887+ char *temp = (char *)iDataSource;
2888+ ERROR_CODE ErrorCode = NO_ERR; // tells us if there was an error erasing flash
2889+
2890+ // First, a Write Enable Command must be sent to the SPI.
2891+ SendSingleCommand(SPI_WREN);
2892+
2893+ // Second, the SPI Status Register will be tested whether the
2894+ // Write Enable Bit has been set.
2895+ ErrorCode = Wait_For_WEL();
2896+ if( POLL_TIMEOUT == ErrorCode )
2897+ {
2898+ printf("SPI Write Time Out\n");
2899+ return ErrorCode;
2900+ }
2901+ else
2902+ // Third, the 24 bit address will be shifted out the SPI MOSI bytewise.
2903+ SetupSPI( (COMMON_SPI_SETTINGS|TIMOD01) ); // Turns the SPI on
2904+ *pSPI_TDBR = SPI_PP;
2905+ __builtin_bfin_ssync();
2906+ Wait_For_SPIF(); //wait until the instruction has been sent
2907+ ulWAddr = (ulStartAddr >> 16);
2908+ *pSPI_TDBR = ulWAddr;
2909+ __builtin_bfin_ssync();
2910+ Wait_For_SPIF(); //wait until the instruction has been sent
2911+ ulWAddr = (ulStartAddr >> 8);
2912+ *pSPI_TDBR = ulWAddr;
2913+ __builtin_bfin_ssync();
2914+ Wait_For_SPIF(); //wait until the instruction has been sent
2915+ ulWAddr = ulStartAddr;
2916+ *pSPI_TDBR = ulWAddr;
2917+ __builtin_bfin_ssync();
2918+ Wait_For_SPIF(); //wait until the instruction has been sent
2919+ // Fourth, maximum number of 256 bytes will be taken from the Buffer
2920+ // and sent to the SPI device.
2921+ for (i=0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++)
2922+ {
2923+ iData = *temp;
2924+ *pSPI_TDBR = iData;
2925+ __builtin_bfin_ssync();
2926+ Wait_For_SPIF(); //wait until the instruction has been sent
2927+ temp++;
2928+ }
2929+
2930+ SPI_OFF(); // Turns the SPI off
2931+
2932+ // Sixth, the SPI Write in Progress Bit must be toggled to ensure the
2933+ // programming is done before start of next transfer.
2934+ ErrorCode = Wait_For_Status(WIP);
2935+
2936+ if( POLL_TIMEOUT == ErrorCode )
2937+ {
2938+ printf("SPI Program Time out!\n");
2939+ return ErrorCode;
2940+ }
2941+ else
2942+
2943+ *lWriteCount = lWTransferCount;
2944+
2945+ return ErrorCode;
2946+}
2947+
2948+
2949+ERROR_CODE WriteData( unsigned long ulStart, long lCount, int *pnData )
2950+{
2951+
2952+ unsigned long ulWStart = ulStart;
2953+ long lWCount = lCount, lWriteCount;
2954+ long *pnWriteCount = &lWriteCount;
2955+
2956+ ERROR_CODE ErrorCode = NO_ERR;
2957+
2958+ while (lWCount != 0)
2959+ {
2960+ ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
2961+
2962+ // After each function call of WriteFlash the counter must be adjusted
2963+ lWCount -= *pnWriteCount;
2964+
2965+ // Also, both address pointers must be recalculated.
2966+ ulWStart += *pnWriteCount;
2967+ pnData += *pnWriteCount/4;
2968+ }
2969+
2970+ // return the appropriate error code
2971+ return ErrorCode;
2972+}
2973+
2974+/*
2975+ * Spit out some useful information about the SPI eeprom
2976+ */
2977+int eeprom_info(void)
2978+{
2979+#if (1)
2980+ return 1;
2981+#else
2982+
2983+ int ret = 0;
2984+
2985+ SPI_INIT();
2986+
2987+ if (spi_detect_part())
2988+ ret = 1;
2989+ else
2990+ printf("SPI Device: %s 0x%02X (%s) 0x%02X 0x%02X\n"
2991+ "Parameters: num sectors = %i, sector size = %i, write size = %i\n"
2992+ "Flash Size: %i mbit (%i mbyte)\n"
2993+ "Status: 0x%02X\n",
2994+ flash.flash->name, flash.manufacturer_id, flash.manufacturer->name,
2995+ flash.device_id1, flash.device_id2, flash.num_sectors,
2996+ flash.sector_size, flash.write_length,
2997+ (flash.num_sectors * flash.sector_size) >> 17,
2998+ (flash.num_sectors * flash.sector_size) >> 20,
2999+ read_status_register());
3000+
3001+ SPI_DEINIT();
3002+
3003+ return ret;
3004+#endif
3005+}
3006+
3007+
3008+#endif /* CONFIG_SPI */
3009diff --git a/u-boot-1.1.6/board/VuQuest2D/spi_flash.c b/u-boot-1.1.6/board/VuQuest2D/spi_flash.c
3010new file mode 100644
3011index 0000000..8784741
3012--- /dev/null
3013+++ b/u-boot-1.1.6/board/VuQuest2D/spi_flash.c
3014@@ -0,0 +1,2 @@
3015+/* Share the spi flash code */
3016+#include "../bf537-stamp/spi_flash.c"
3017diff --git a/u-boot-1.1.6/board/VuQuest2D/u-boot.lds.S b/u-boot-1.1.6/board/VuQuest2D/u-boot.lds.S
3018new file mode 100644
3019index 0000000..01780c5
3020--- /dev/null
3021+++ b/u-boot-1.1.6/board/VuQuest2D/u-boot.lds.S
3022@@ -0,0 +1,136 @@
3023+/*
3024+ * U-boot - u-boot.lds.S
3025+ *
3026+ * Copyright (c) 2005-2008 Analog Device Inc.
3027+ *
3028+ * (C) Copyright 2000-2004
3029+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
3030+ *
3031+ * See file CREDITS for list of people who contributed to this
3032+ * project.
3033+ *
3034+ * This program is free software; you can redistribute it and/or
3035+ * modify it under the terms of the GNU General Public License as
3036+ * published by the Free Software Foundation; either version 2 of
3037+ * the License, or (at your option) any later version.
3038+ *
3039+ * This program is distributed in the hope that it will be useful,
3040+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3041+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3042+ * GNU General Public License for more details.
3043+ *
3044+ * You should have received a copy of the GNU General Public License
3045+ * along with this program; if not, write to the Free Software
3046+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3047+ * MA 02111-1307 USA
3048+ */
3049+
3050+#include <config.h>
3051+#include <asm/blackfin.h>
3052+#undef ALIGN
3053+
3054+/* If we don't actually load anything into L1 data, this will avoid
3055+ * a syntax error. If we do actually load something into L1 data,
3056+ * we'll get a linker memory load error (which is what we'd want).
3057+ * This is here in the first place so we can quickly test building
3058+ * for different CPU's which may lack non-cache L1 data.
3059+ */
3060+#ifndef L1_DATA_B_SRAM
3061+# define L1_DATA_B_SRAM CFG_MONITOR_BASE
3062+# define L1_DATA_B_SRAM_SIZE 0
3063+#endif
3064+
3065+OUTPUT_ARCH(bfin)
3066+
3067+/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
3068+MEMORY
3069+{
3070+ ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
3071+ l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
3072+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
3073+}
3074+
3075+SECTIONS
3076+{
3077+ .text :
3078+ {
3079+#ifdef ENV_IS_EMBEDDED
3080+ /* WARNING - the following is hand-optimized to fit within
3081+ * the sector before the environment sector. If it throws
3082+ * an error during compilation remove an object here to get
3083+ * it linked after the configuration sector.
3084+ */
3085+
3086+ cpu/blackfin/start.o (.text)
3087+ cpu/blackfin/traps.o (.text)
3088+ cpu/blackfin/interrupt.o (.text)
3089+ cpu/blackfin/serial.o (.text)
3090+ common/dlmalloc.o (.text)
3091+ lib_generic/crc32.o (.text)
3092+
3093+ . = DEFINED(env_offset) ? env_offset : .;
3094+ common/environment.o (.text)
3095+#endif
3096+
3097+ *(.text .text.*)
3098+ } >ram
3099+
3100+ .rodata :
3101+ {
3102+ . = ALIGN(4);
3103+ *(.rodata .rodata.*)
3104+ *(.rodata1)
3105+ *(.eh_frame)
3106+ . = ALIGN(4);
3107+ } >ram
3108+
3109+ .data :
3110+ {
3111+ . = ALIGN(256);
3112+ *(.data .data.*)
3113+ *(.data1)
3114+ *(.sdata)
3115+ *(.sdata2)
3116+ *(.dynamic)
3117+ CONSTRUCTORS
3118+ } >ram
3119+
3120+ .u_boot_cmd :
3121+ {
3122+ ___u_boot_cmd_start = .;
3123+ *(.u_boot_cmd)
3124+ ___u_boot_cmd_end = .;
3125+ } >ram
3126+
3127+ .text_l1 :
3128+ {
3129+ . = ALIGN(4);
3130+ __stext_l1 = .;
3131+ *(.l1.text)
3132+ . = ALIGN(4);
3133+ __etext_l1 = .;
3134+ } >l1_code AT>ram
3135+ __stext_l1_lma = LOADADDR(.text_l1);
3136+
3137+ .data_l1 :
3138+ {
3139+ . = ALIGN(4);
3140+ __sdata_l1 = .;
3141+ *(.l1.data)
3142+ *(.l1.bss)
3143+ . = ALIGN(4);
3144+ __edata_l1 = .;
3145+ } >l1_data AT>ram
3146+ __sdata_l1_lma = LOADADDR(.data_l1);
3147+
3148+ .bss :
3149+ {
3150+ . = ALIGN(4);
3151+ __bss_start = .;
3152+ *(.sbss) *(.scommon)
3153+ *(.dynbss)
3154+ *(.bss .bss.*)
3155+ *(COMMON)
3156+ __bss_end = .;
3157+ } >ram
3158+}
3159diff --git a/u-boot-1.1.6/board/VuQuest2D/video.c b/u-boot-1.1.6/board/VuQuest2D/video.c
3160new file mode 100644
3161index 0000000..2d6f7a4
3162--- /dev/null
3163+++ b/u-boot-1.1.6/board/VuQuest2D/video.c
3164@@ -0,0 +1,187 @@
3165+/*
3166+ * (C) Copyright 2000
3167+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
3168+ * (C) Copyright 2002
3169+ * Wolfgang Denk, wd@denx.de
3170+ * (C) Copyright 2006
3171+ * Aubrey Li, aubrey.li@analog.com
3172+ *
3173+ * See file CREDITS for list of people who contributed to this
3174+ * project.
3175+ *
3176+ * This program is free software; you can redistribute it and/or
3177+ * modify it under the terms of the GNU General Public License as
3178+ * published by the Free Software Foundation; either version 2 of
3179+ * the License, or (at your option) any later version.
3180+ *
3181+ * This program is distributed in the hope that it will be useful,
3182+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3183+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3184+ * GNU General Public License for more details.
3185+ *
3186+ * You should have received a copy of the GNU General Public License
3187+ * along with this program; if not, write to the Free Software
3188+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3189+ * MA 02111-1307 USA
3190+ */
3191+
3192+#include <stdarg.h>
3193+#include <common.h>
3194+#include <config.h>
3195+#include <malloc.h>
3196+#include <asm/blackfin.h>
3197+#include <asm/mach-common/bits/dma.h>
3198+#include <i2c.h>
3199+#include <linux/types.h>
3200+#include <devices.h>
3201+
3202+int gunzip(void *, int, unsigned char *, unsigned long *);
3203+
3204+#ifdef CONFIG_VIDEO
3205+
3206+#define DMA_SIZE16 2
3207+
3208+#include <asm/mach-common/bits/ppi.h>
3209+
3210+#define NTSC_FRAME_ADDR 0x06000000
3211+#include "video.h"
3212+
3213+/* NTSC OUTPUT SIZE 720 * 240 */
3214+#define VERTICAL 2
3215+#define HORIZONTAL 4
3216+
3217+int is_vblank_line(const int line)
3218+{
3219+ /*
3220+ * This array contains a single bit for each line in
3221+ * an NTSC frame.
3222+ */
3223+ if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
3224+ return true;
3225+
3226+ return false;
3227+}
3228+
3229+int NTSC_framebuffer_init(char *base_address)
3230+{
3231+ const int NTSC_frames = 1;
3232+ const int NTSC_lines = 525;
3233+ char *dest = base_address;
3234+ int frame_num, line_num;
3235+
3236+ for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
3237+ for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
3238+ unsigned int code;
3239+ int offset = 0;
3240+ int i;
3241+
3242+ if (is_vblank_line(line_num))
3243+ offset++;
3244+
3245+ if (line_num > 266 || line_num < 3)
3246+ offset += 2;
3247+
3248+ /* Output EAV code */
3249+ code = SystemCodeMap[offset].EAV;
3250+ write_dest_byte((char)(code >> 24) & 0xff);
3251+ write_dest_byte((char)(code >> 16) & 0xff);
3252+ write_dest_byte((char)(code >> 8) & 0xff);
3253+ write_dest_byte((char)(code) & 0xff);
3254+
3255+ /* Output horizontal blanking */
3256+ for (i = 0; i < 67 * 2; ++i) {
3257+ write_dest_byte(0x80);
3258+ write_dest_byte(0x10);
3259+ }
3260+
3261+ /* Output SAV */
3262+ code = SystemCodeMap[offset].SAV;
3263+ write_dest_byte((char)(code >> 24) & 0xff);
3264+ write_dest_byte((char)(code >> 16) & 0xff);
3265+ write_dest_byte((char)(code >> 8) & 0xff);
3266+ write_dest_byte((char)(code) & 0xff);
3267+
3268+ /* Output empty horizontal data */
3269+ for (i = 0; i < 360 * 2; ++i) {
3270+ write_dest_byte(0x80);
3271+ write_dest_byte(0x10);
3272+ }
3273+ }
3274+ }
3275+
3276+ return dest - base_address;
3277+}
3278+
3279+void fill_frame(char *Frame, int Value)
3280+{
3281+ int *OddPtr32;
3282+ int OddLine;
3283+ int *EvenPtr32;
3284+ int EvenLine;
3285+ int i;
3286+ int *data;
3287+ int m, n;
3288+
3289+ /* fill odd and even frames */
3290+ for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
3291+ OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
3292+ EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
3293+ for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
3294+ *OddPtr32 = Value;
3295+ *EvenPtr32 = Value;
3296+ }
3297+ }
3298+
3299+ for (m = 0; m < VERTICAL; m++) {
3300+ data = (int *)u_boot_logo.data;
3301+ for (OddLine = (22 + m), EvenLine = (285 + m);
3302+ OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
3303+ OddLine += VERTICAL, EvenLine += VERTICAL) {
3304+ OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
3305+ EvenPtr32 =
3306+ (int *)((Frame + ((EvenLine) * 1716)) + 276);
3307+ for (i = 0; i < u_boot_logo.width / 2; i++) {
3308+ /* enlarge one pixel to m x n */
3309+ for (n = 0; n < HORIZONTAL; n++) {
3310+ *OddPtr32++ = *data;
3311+ *EvenPtr32++ = *data;
3312+ }
3313+ data++;
3314+ }
3315+ }
3316+ }
3317+}
3318+
3319+static void video_init(char *NTSCFrame)
3320+{
3321+ NTSCFrame = (char *)NTSC_FRAME_ADDR;
3322+ NTSC_framebuffer_init(NTSCFrame);
3323+ fill_frame(NTSCFrame, BLUE);
3324+
3325+ bfin_write_PPI_CONTROL(0x0082);
3326+ bfin_write_PPI_FRAME(0x020D);
3327+
3328+ bfin_write_DMA0_START_ADDR(NTSCFrame);
3329+ bfin_write_DMA0_X_COUNT(0x035A);
3330+ bfin_write_DMA0_X_MODIFY(0x0002);
3331+ bfin_write_DMA0_Y_COUNT(0x020D);
3332+ bfin_write_DMA0_Y_MODIFY(0x0002);
3333+ bfin_write_DMA0_CONFIG(0x1015);
3334+ bfin_write_PPI_CONTROL(0x0083);
3335+}
3336+
3337+int drv_video_init(void)
3338+{
3339+ device_t videodev;
3340+
3341+ video_init((void *)NTSC_FRAME_ADDR);
3342+
3343+ memset(&videodev, 0, sizeof(videodev));
3344+ strcpy(videodev.name, "video");
3345+ videodev.ext = DEV_EXT_VIDEO;
3346+ videodev.flags = DEV_FLAGS_SYSTEM;
3347+
3348+ return device_register(&videodev);
3349+}
3350+
3351+#endif
3352diff --git a/u-boot-1.1.6/board/VuQuest2D/video.h b/u-boot-1.1.6/board/VuQuest2D/video.h
3353new file mode 100644
3354index 0000000..d5a8bc8
3355--- /dev/null
3356+++ b/u-boot-1.1.6/board/VuQuest2D/video.h
3357@@ -0,0 +1,25 @@
3358+#include <video_logo.h>
3359+#define write_dest_byte(val) {*dest++=val;}
3360+#define BLACK (0x01800180) /* black pixel pattern */
3361+#define BLUE (0x296E29F0) /* blue pixel pattern */
3362+#define RED (0x51F0515A) /* red pixel pattern */
3363+#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */
3364+#define GREEN (0x91229136) /* green pixel pattern */
3365+#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
3366+#define YELLOW (0xD292D210) /* yellow pixel pattern */
3367+#define WHITE (0xFE80FE80) /* white pixel pattern */
3368+
3369+#define true 1
3370+#define false 0
3371+
3372+typedef struct {
3373+ unsigned int SAV;
3374+ unsigned int EAV;
3375+} SystemCodeType;
3376+
3377+const SystemCodeType SystemCodeMap[4] = {
3378+ {0xFF000080, 0xFF00009D},
3379+ {0xFF0000AB, 0xFF0000B6},
3380+ {0xFF0000C7, 0xFF0000DA},
3381+ {0xFF0000EC, 0xFF0000F1}
3382+};
3383diff --git a/u-boot-1.1.6/common/Makefile b/u-boot-1.1.6/common/Makefile
3384index f848123..c9cdabd 100644
3385--- a/u-boot-1.1.6/common/Makefile
3386+++ b/u-boot-1.1.6/common/Makefile
3387@@ -51,7 +51,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \
3388 memsize.o miiphybb.o miiphyutil.o \
3389 s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
3390 usb.o usb_kbd.o usb_storage.o \
3391- virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o
3392+ virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o interface_select.o metro_pf.o
3393
3394 SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
3395 OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
3396diff --git a/u-boot-1.1.6/common/cmd_bdinfo.c b/u-boot-1.1.6/common/cmd_bdinfo.c
3397index bba7b75..3b1fcfc 100644
3398--- a/u-boot-1.1.6/common/cmd_bdinfo.c
3399+++ b/u-boot-1.1.6/common/cmd_bdinfo.c
3400@@ -91,36 +91,38 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3401 print_str ("pevfreq", strmhz(buf, bd->bi_pevfreq));
3402 #endif
3403
3404+#if (CONFIG_COMMANDS & CFG_CMD_NET)
3405 puts ("ethaddr =");
3406 for (i=0; i<6; ++i) {
3407 printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
3408 }
3409
3410-#if defined(CONFIG_HAS_ETH1)
3411+ #if defined(CONFIG_HAS_ETH1)
3412 puts ("\neth1addr =");
3413 for (i=0; i<6; ++i) {
3414 printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
3415 }
3416-#endif
3417+ #endif
3418
3419-#if defined(CONFIG_HAS_ETH2)
3420+ #if defined(CONFIG_HAS_ETH2)
3421 puts ("\neth2addr =");
3422 for (i=0; i<6; ++i) {
3423 printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
3424 }
3425-#endif
3426+ #endif
3427
3428-#if defined(CONFIG_HAS_ETH3)
3429+ #if defined(CONFIG_HAS_ETH3)
3430 puts ("\neth3addr =");
3431 for (i=0; i<6; ++i) {
3432 printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]);
3433 }
3434-#endif
3435+ #endif
3436
3437-#ifdef CONFIG_HERMES
3438+ #ifdef CONFIG_HERMES
3439 print_str ("ethspeed", strmhz(buf, bd->bi_ethspeed));
3440-#endif
3441+ #endif
3442 puts ("\nIP addr = "); print_IPaddr (bd->bi_ip_addr);
3443+#endif /* (CONFIG_COMMANDS & CFG_CMD_NET) */
3444 printf ("\nbaudrate = %6ld bps\n", bd->bi_baudrate );
3445 return 0;
3446 }
3447@@ -138,12 +140,13 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3448 print_num ("flashsize", (ulong)bd->bi_flashsize);
3449 print_num ("flashoffset", (ulong)bd->bi_flashoffset);
3450
3451+#if (CONFIG_COMMANDS & CFG_CMD_NET)
3452 puts ("ethaddr =");
3453 for (i=0; i<6; ++i) {
3454 printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
3455 }
3456- puts ("\nip_addr = ");
3457- print_IPaddr (bd->bi_ip_addr);
3458+ puts ("\nip_addr = "); print_IPaddr (bd->bi_ip_addr);
3459+#endif
3460 printf ("\nbaudrate = %ld bps\n", bd->bi_baudrate);
3461
3462 return 0;
3463@@ -167,13 +170,12 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3464 print_num ("sram size", (ulong)bd->bi_sramsize);
3465 #endif
3466
3467-#if defined(CFG_CMD_NET)
3468+#if (CONFIG_COMMANDS & CFG_CMD_NET)
3469 puts ("ethaddr =");
3470 for (i=0; i<6; ++i) {
3471 printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
3472 }
3473- puts ("\nip_addr = ");
3474- print_IPaddr (bd->bi_ip_addr);
3475+ puts ("\nip_addr = "); print_IPaddr (bd->bi_ip_addr);
3476 #endif
3477
3478 printf ("\nbaudrate = %ld bps\n", bd->bi_baudrate);
3479@@ -202,11 +204,12 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3480 print_num("flashsize", (ulong)bd->bi_flashsize);
3481 print_num("flashoffset", (ulong)bd->bi_flashoffset);
3482
3483+#if (CONFIG_COMMANDS & CFG_CMD_NET)
3484 puts("ethaddr =");
3485 for (i = 0; i < 6; ++i)
3486 printf("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
3487- puts("\nip_addr = ");
3488- print_IPaddr(bd->bi_ip_addr);
3489+ puts("\nip_addr = "); print_IPaddr(bd->bi_ip_addr);
3490+#endif
3491 printf("\nbaudrate = %d bps\n", bd->bi_baudrate);
3492
3493 return 0;
3494@@ -226,12 +229,13 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3495 print_num ("flashsize", (ulong)bd->bi_flashsize);
3496 print_num ("flashoffset", (ulong)bd->bi_flashoffset);
3497
3498+#if (CONFIG_COMMANDS & CFG_CMD_NET)
3499 puts ("ethaddr =");
3500 for (i=0; i<6; ++i) {
3501 printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
3502 }
3503- puts ("\nip_addr = ");
3504- print_IPaddr (bd->bi_ip_addr);
3505+ puts ("\nip_addr = "); print_IPaddr (bd->bi_ip_addr);
3506+#endif
3507 printf ("\nbaudrate = %d bps\n", bd->bi_baudrate);
3508
3509 return 0;
3510@@ -255,6 +259,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3511 print_num("-> size", bd->bi_dram[i].size);
3512 }
3513
3514+#if (CONFIG_COMMANDS & CFG_CMD_NET)
3515 puts ("ethaddr =");
3516 for (i=0; i<6; ++i) {
3517 printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
3518@@ -262,6 +267,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3519 puts ( "\n"
3520 "ip_addr = ");
3521 print_IPaddr (bd->bi_ip_addr);
3522+#endif
3523 printf ("\n"
3524 "baudrate = %d bps\n", bd->bi_baudrate);
3525
3526diff --git a/u-boot-1.1.6/common/cmd_bootm.c b/u-boot-1.1.6/common/cmd_bootm.c
3527index e6fe472..8711ff4 100644
3528--- a/u-boot-1.1.6/common/cmd_bootm.c
3529+++ b/u-boot-1.1.6/common/cmd_bootm.c
3530@@ -150,6 +150,13 @@ image_header_t header;
3531
3532 ulong load_addr = CFG_LOAD_ADDR; /* Default Load Address */
3533
3534+#if defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
3535+
3536+extern int Get_Interface_AtoD_Value(void);
3537+extern void Send_Interface_AtoD_to_kernel(void);
3538+
3539+#endif
3540+
3541 int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3542 {
3543 ulong iflag;
3544@@ -415,6 +422,12 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3545 #ifdef CONFIG_SILENT_CONSOLE
3546 fixup_silent_linux();
3547 #endif
3548+#if defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
3549+ if (Get_Interface_AtoD_Value() >= 0)
3550+ {
3551+ Send_Interface_AtoD_to_kernel();
3552+ }
3553+#endif
3554 do_bootm_linux (cmdtp, flag, argc, argv,
3555 addr, len_ptr, verify);
3556 break;
3557diff --git a/u-boot-1.1.6/common/cmd_eeprom.c b/u-boot-1.1.6/common/cmd_eeprom.c
3558index cb7963f..84d65aa 100644
3559--- a/u-boot-1.1.6/common/cmd_eeprom.c
3560+++ b/u-boot-1.1.6/common/cmd_eeprom.c
3561@@ -42,6 +42,14 @@
3562 #include <command.h>
3563 #include <i2c.h>
3564
3565+#define DEBUG_BOOT_PERFORMANCE 1
3566+
3567+#if (DEBUG_BOOT_PERFORMANCE)
3568+#include <Metrologic_Hardware.h>
3569+#include <metro_pf.h>
3570+#endif
3571+
3572+
3573 #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) || defined(CFG_ENV_IS_IN_EEPROM)
3574
3575 extern void eeprom_init (void);
3576@@ -139,6 +147,10 @@ int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt
3577 unsigned blk_off;
3578 int rcode = 0;
3579
3580+
3581+#if (DEBUG_BOOT_PERFORMANCE) && defined(__ADSPBF531__)
3582+ *pFIO_FLAG_D |= (PF4); /* Assert Aiming_On */
3583+#endif
3584 /* Read data until done or would cross a page boundary.
3585 * We must write the address again when changing pages
3586 * because the next page may be in a different device.
3587diff --git a/u-boot-1.1.6/common/cmd_load.c b/u-boot-1.1.6/common/cmd_load.c
3588index f63b8e8..0c64bc9 100644
3589--- a/u-boot-1.1.6/common/cmd_load.c
3590+++ b/u-boot-1.1.6/common/cmd_load.c
3591@@ -25,11 +25,14 @@
3592 * Serial up- and download support
3593 */
3594 #include <common.h>
3595+#include <watchdog.h>
3596 #include <command.h>
3597 #include <s_record.h>
3598 #include <net.h>
3599 #include <exports.h>
3600 #include <xyzModem.h>
3601+#include <asm/mach-common/bits/bootrom.h>
3602+#include <Metrologic_Hardware.h>
3603
3604 DECLARE_GLOBAL_DATA_PTR;
3605
3606@@ -84,9 +87,11 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3607 if (load_baudrate != current_baudrate) {
3608 printf ("## Switch baudrate to %d bps and press ENTER ...\n",
3609 load_baudrate);
3610+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3611 udelay(50000);
3612 gd->baudrate = load_baudrate;
3613 serial_setbrg ();
3614+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3615 udelay(50000);
3616 for (;;) {
3617 if (getc() == '\r')
3618@@ -127,9 +132,11 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3619 if (load_baudrate != current_baudrate) {
3620 printf ("## Switch baudrate to %d bps and press ESC ...\n",
3621 current_baudrate);
3622+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3623 udelay (50000);
3624 gd->baudrate = current_baudrate;
3625 serial_setbrg ();
3626+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3627 udelay (50000);
3628 for (;;) {
3629 if (getc() == 0x1B) /* ESC */
3630@@ -282,9 +289,11 @@ int do_save_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3631 if (save_baudrate != current_baudrate) {
3632 printf ("## Switch baudrate to %d bps and press ENTER ...\n",
3633 save_baudrate);
3634+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3635 udelay(50000);
3636 gd->baudrate = save_baudrate;
3637 serial_setbrg ();
3638+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3639 udelay(50000);
3640 for (;;) {
3641 if (getc() == '\r')
3642@@ -311,9 +320,11 @@ int do_save_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3643 if (save_baudrate != current_baudrate) {
3644 printf ("## Switch baudrate to %d bps and press ESC ...\n",
3645 (int)current_baudrate);
3646+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3647 udelay (50000);
3648 gd->baudrate = current_baudrate;
3649 serial_setbrg ();
3650+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3651 udelay (50000);
3652 for (;;) {
3653 if (getc() == 0x1B) /* ESC */
3654@@ -466,9 +477,11 @@ int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3655 if (load_baudrate != current_baudrate) {
3656 printf ("## Switch baudrate to %d bps and press ENTER ...\n",
3657 load_baudrate);
3658+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3659 udelay(50000);
3660 gd->baudrate = load_baudrate;
3661 serial_setbrg ();
3662+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3663 udelay(50000);
3664 for (;;) {
3665 if (getc() == '\r')
3666@@ -504,9 +517,11 @@ int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3667 if (load_baudrate != current_baudrate) {
3668 printf ("## Switch baudrate to %d bps and press ESC ...\n",
3669 current_baudrate);
3670+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3671 udelay (50000);
3672 gd->baudrate = current_baudrate;
3673 serial_setbrg ();
3674+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3675 udelay (50000);
3676 for (;;) {
3677 if (getc() == 0x1B) /* ESC */
3678@@ -1036,6 +1051,406 @@ static ulong load_serial_ymodem (ulong offset)
3679 return offset;
3680 }
3681
3682+/**********************************************************************
3683+ *************** Added by Metrologic *********************************
3684+ **********************************************************************/
3685+
3686+extern flash_info_t flash_info[]; /* info for FLASH chips */
3687+
3688+int do_flash (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3689+{
3690+#ifdef CFG_NO_FLASH
3691+ return 0;
3692+#else
3693+ ulong addr_first;
3694+ ulong addr_last;
3695+ ulong addr = load_addr;
3696+ ulong dest;
3697+ ulong count;
3698+ int rc = 0;
3699+ char *s;
3700+
3701+ if (argc != 2)
3702+ {
3703+ goto __DO_FLASH_ERROR;
3704+ }
3705+
3706+ if ((s = getenv("filesize")) != NULL)
3707+ {
3708+ count = simple_strtoul(s, NULL, 16);
3709+ }
3710+ else
3711+ {
3712+ puts ("Unknown filesize! Download file first!\n");
3713+ return 1;;
3714+ }
3715+
3716+ if (strcmp(argv[1] ,"u-boot") == 0)
3717+ {
3718+ int i;
3719+ flash_info_t *info;
3720+ int protect_on = 0;
3721+ int bank;
3722+ int p = 0;
3723+
3724+ puts ("Unprotecting flash sectors... ");
3725+
3726+ for (bank=1; bank<=CFG_MAX_FLASH_BANKS; ++bank) {
3727+ info = &flash_info[bank-1];
3728+ if (info->flash_id == FLASH_UNKNOWN) {
3729+ continue;
3730+ }
3731+ printf ("%sProtect Flash Bank # %ld\n",
3732+ p ? "" : "Un-", bank);
3733+
3734+ for (i=0; i<info->sector_count; ++i) {
3735+#if defined(CFG_FLASH_PROTECTION)
3736+ if (flash_real_protect(info, i, p))
3737+ rcode = 1;
3738+ putc ('.');
3739+#else
3740+ info->protect[i] = p;
3741+#endif /* CFG_FLASH_PROTECTION */
3742+ }
3743+ }
3744+
3745+ puts ("Done\n");
3746+
3747+ addr_first = (ulong)U_BOOT_START_ADDR;
3748+ addr_last = (ulong)CONFIG_START_ADDR - 1;
3749+
3750+ dest = U_BOOT_START_ADDR;
3751+ rc = 1;
3752+ }
3753+ else if (strcmp(argv[1] ,"kernel") == 0)
3754+ {
3755+ addr_first = (ulong)KERNEL_START_ADDR;
3756+ addr_last = (ulong)FILSYS_START_ADDR - 1;
3757+
3758+ dest = KERNEL_START_ADDR;
3759+ rc = 2;
3760+ }
3761+ else if (strcmp(argv[1] ,"filesystem") == 0)
3762+ {
3763+#ifndef CFG_FLASH_SIZE
3764+ puts ("CFG_FLASH_SIZE must be defined to use this feature!\n");
3765+ return 1;
3766+#endif
3767+
3768+ addr_first = (ulong)FILSYS_START_ADDR;
3769+ addr_last = (ulong)FLASH_PARTITION_START + (ulong)CFG_FLASH_SIZE - 1;
3770+
3771+ dest = FILSYS_START_ADDR;
3772+ rc = 3;
3773+ }
3774+
3775+ if (rc >= 1)
3776+ {
3777+ if (addr_last <= addr_first)
3778+ {
3779+ puts("Invalid CFG_FLASH_SIZE\n");
3780+ return 1;
3781+ }
3782+
3783+ printf ("Erasing %s\n", argv[1]);
3784+
3785+ if (flash_sect_erase(addr_first, addr_last))
3786+ {
3787+ printf ("Error erasing region %d - %d\n", addr_first, addr_last);
3788+ return 1;
3789+ }
3790+ puts ("Done\n");
3791+
3792+ printf ("Copy %s to Flash... ", argv[1]);
3793+
3794+ rc = flash_write ((uchar *)addr, dest, count);
3795+ if (rc != 0) {
3796+ flash_perror (rc);
3797+ return (1);
3798+ }
3799+ puts ("done\n");
3800+ return 0;
3801+ }
3802+
3803+__DO_FLASH_ERROR:
3804+
3805+ printf ("Usage:\n%s\n", cmdtp->usage);
3806+ return 1;
3807+#endif
3808+}
3809+
3810+int do_eflash ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
3811+{
3812+ const char *const fmt =
3813+ "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
3814+
3815+ ulong dev_addr = CFG_DEF_EEPROM_ADDR;
3816+ ulong addr = load_addr;
3817+ ulong off;
3818+ ulong cnt;
3819+ char *s;
3820+ int rcode = 0;
3821+
3822+ if (argc != 2)
3823+ {
3824+ goto __DO_EFLASH_ERROR;
3825+ }
3826+
3827+ if ((s = getenv("filesize")) != NULL)
3828+ {
3829+ cnt = simple_strtoul(s, NULL, 16);
3830+ }
3831+ else
3832+ {
3833+ puts ("Unknown filesize! Download file first!\n");
3834+ return 1;
3835+ }
3836+
3837+ if (strcmp(argv[1] ,"u-boot") == 0)
3838+ {
3839+ off = U_BOOT_START_OFFS;
3840+ rcode = 1;
3841+ }
3842+ else if (strcmp(argv[1] ,"kernel") == 0)
3843+ {
3844+ off = KERNEL_START_OFFS;
3845+ rcode = 2;
3846+ }
3847+ else if (strcmp(argv[1] ,"filesystem") == 0)
3848+ {
3849+ ulong addr_pad = load_addr - PADDING_BUFF_SIZE;
3850+ ulong bytes_to_erase = (ulong)CFG_FLASH_SIZE - 1 - FILSYS_START_OFFS;
3851+ ulong start_offset = FILSYS_START_OFFS;
3852+ int i;
3853+
3854+ if (load_addr < PADDING_BUFF_SIZE)
3855+ {
3856+ printf ("load_addr too small, need %d bytes room to erase filesystem\n", PADDING_BUFF_SIZE);
3857+ return 1;
3858+ }
3859+
3860+ for (i = 0; i < PADDING_BUFF_SIZE; i++)
3861+ {
3862+ *((u_char *)addr_pad) = (u_char)PADDING_CHAR;
3863+ addr_pad += 1;
3864+ }
3865+
3866+ addr_pad = load_addr - PADDING_BUFF_SIZE;
3867+
3868+ if (cnt >= 12)
3869+ {
3870+ for (i = 0; i < 12; i++)
3871+ {
3872+ *((u_char *)addr_pad) = *((u_char*)addr);
3873+ addr_pad += 1;
3874+ addr += 1;
3875+ }
3876+ }
3877+
3878+ addr = load_addr;
3879+ addr_pad = load_addr - PADDING_BUFF_SIZE;
3880+
3881+ puts ("Formatting file system partition... ");
3882+
3883+ while (bytes_to_erase > 0)
3884+ {
3885+ ulong count;
3886+
3887+ if ( bytes_to_erase > PADDING_BUFF_SIZE )
3888+ {
3889+ count = PADDING_BUFF_SIZE;
3890+ }
3891+ else
3892+ {
3893+ for (i = 0; i < 12; i++)
3894+ {
3895+ *((u_char *)addr_pad) = (u_char)PADDING_CHAR;
3896+ addr_pad += 1;
3897+ }
3898+ addr_pad = load_addr - PADDING_BUFF_SIZE;
3899+ count = bytes_to_erase;
3900+ }
3901+
3902+ if (eeprom_write (dev_addr, start_offset, (uchar *) addr_pad, count))
3903+ {
3904+ printf("Error erasing %d to %d\n", start_offset, start_offset + count);
3905+ return 1;
3906+ }
3907+ else
3908+ {
3909+ puts (".");
3910+ }
3911+ start_offset += count;
3912+ bytes_to_erase -= count;
3913+ }
3914+
3915+ puts ("done\n");
3916+ off = FILSYS_START_OFFS;
3917+ rcode = 3;
3918+ }
3919+
3920+ if (rcode >= 1)
3921+ {
3922+ printf (fmt, dev_addr, "write", addr, off, cnt);
3923+ rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);
3924+ puts ("done\n");
3925+ return rcode;
3926+ }
3927+
3928+__DO_EFLASH_ERROR:
3929+
3930+ printf ("Usage:\n%s\n", cmdtp->usage);
3931+ return 1;
3932+
3933+}
3934+
3935+
3936+int print_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3937+{
3938+ uint regval1, regval2, regval3, regval4;
3939+
3940+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534) || \
3941+ defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) )
3942+
3943+ regval1 = *pPORTF_FER;
3944+ regval2 = *pPORTFIO_DIR;
3945+ regval3 = *pPORTFIO_INEN;
3946+ regval4 = *pPORTFIO;
3947+
3948+ printf ("PortF, FER 0x%04x, DIR 0x%04x, INEN 0x%04x, DATA 0x%04x\r\n",
3949+ regval1, regval2, regval3, regval4);
3950+
3951+ regval1 = *pPORTG_FER;
3952+ regval2 = *pPORTGIO_DIR;
3953+ regval3 = *pPORTGIO_INEN;
3954+ regval4 = *pPORTGIO;
3955+
3956+ printf ("PortG, FER 0x%04x, DIR 0x%04x, INEN 0x%04x, DATA 0x%04x\r\n",
3957+ regval1, regval2, regval3, regval4);
3958+
3959+ regval1 = *pPORTH_FER;
3960+ regval2 = *pPORTHIO_DIR;
3961+ regval3 = *pPORTHIO_INEN;
3962+ regval4 = *pPORTHIO;
3963+
3964+ printf ("PortH, FER 0x%04x, DIR 0x%04x, INEN 0x%04x, DATA 0x%04x\r\n",
3965+ regval1, regval2, regval3, regval4);
3966+
3967+#elif (defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
3968+ defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) )
3969+
3970+ regval1 = *pFIO_DIR;
3971+ regval2 = *pFIO_EDGE;
3972+ regval3 = *pFIO_INEN;
3973+ regval4 = *pFIO_FLAG_D;
3974+
3975+ {
3976+ uint regval5 = *pFIO_POLAR;
3977+
3978+ printf ("PortF, DIR 0x%04x, EDGE 0x%04x, INEN 0x%04x, DATA 0x%04x, POLAR 0x%04x\r\n",
3979+ regval1, regval2, regval3, regval4, regval5);
3980+ }
3981+#else
3982+#error "Unknown Blackfin platform..."
3983+#endif
3984+
3985+ regval1 = *pVR_CTL;
3986+ printf("VR_CTL = 0x%04x\r\n", regval1);
3987+
3988+ return 0;
3989+}
3990+
3991+extern void Configure_Interface_IO(void);
3992+extern void DisplayInterfaceBoard(void);
3993+
3994+#if defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
3995+
3996+extern int Get_Interface_AtoD_Value(void);
3997+extern void Send_Interface_AtoD_to_kernel(void);
3998+int program_vrctl(int millivolt);
3999+
4000+#endif
4001+
4002+int interfaceboard_init (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
4003+{
4004+ Configure_Interface_IO();
4005+ DisplayInterfaceBoard();
4006+#if defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
4007+ if (Get_Interface_AtoD_Value() >= 0)
4008+ {
4009+ Send_Interface_AtoD_to_kernel();
4010+ }
4011+#endif
4012+ return 0;
4013+}
4014+
4015+int prog_vrctl (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
4016+{
4017+ unsigned long voltage;
4018+
4019+ if (argc != 2)
4020+ {
4021+ goto __PROG_VRCTL_ERROR;
4022+ }
4023+
4024+ voltage = simple_strtoul(argv[1], NULL, 10);
4025+
4026+ if (voltage < 850 || voltage > 1300)
4027+ {
4028+ goto __PROG_VRCTL_ERROR;
4029+ }
4030+
4031+ if (voltage % 50)
4032+ {
4033+ goto __PROG_VRCTL_ERROR;
4034+ }
4035+
4036+ program_vrctl(voltage);
4037+
4038+ return 0;
4039+
4040+__PROG_VRCTL_ERROR:
4041+ printf ("Usage:\n%s\n", cmdtp->usage);
4042+ return 1;
4043+}
4044+
4045+int program_vrctl(int millivolt)
4046+{
4047+ int vlev = 6;
4048+ uint mask = 0xFF0F;
4049+
4050+#if defined(CONFIG_DISABLE_CLKIN_OUTPUT)
4051+#if (CONFIG_DISABLE_CLKIN_OUTPUT)
4052+
4053+ mask = 0xBF0F;
4054+
4055+#endif
4056+#endif
4057+
4058+ vlev = 6 + (millivolt - 850) / 50;
4059+
4060+ disable_interrupts();
4061+
4062+ if (millivolt < 850 || millivolt > 1300)
4063+ { /* Preserve the voltage setting but update the clkin-output */
4064+ *pVR_CTL = *pVR_CTL & (mask | 0x00f0);
4065+ }
4066+ else
4067+ {
4068+ *pVR_CTL = (*pVR_CTL & mask) | (vlev << 4);
4069+ }
4070+
4071+ asm("idle;");
4072+
4073+ enable_interrupts();
4074+
4075+ return 0;
4076+}
4077+
4078+/**********************************************************************
4079+ *************** Metrologic *********************************
4080+ **********************************************************************/
4081+
4082 #endif /* CFG_CMD_LOADB */
4083
4084 /* -------------------------------------------------------------------- */
4085@@ -1103,6 +1518,47 @@ U_BOOT_CMD(
4086 " with offset 'off' and baudrate 'baud'\n"
4087 );
4088
4089+
4090+/**********************************************************************
4091+ *************** Added by Metrologic *********************************
4092+ **********************************************************************/
4093+
4094+U_BOOT_CMD(
4095+ flash, 2, 0, do_flash,
4096+ "flash - save binary file to parallel flash\n",
4097+ "[ u-boot | kernel | filesystem ]\n"
4098+ " - save binary file to parallel flash\n"
4099+);
4100+
4101+U_BOOT_CMD(
4102+ eflash, 2, 0, do_eflash,
4103+ "eflash - save binary file to EEPROM\n",
4104+ "[ u-boot | kernel | filesystem ]\n"
4105+ " - save binary file to EEPROM\n"
4106+);
4107+
4108+U_BOOT_CMD(
4109+ status, 2, 0, print_status,
4110+ "status - Prints the status of different registers\n",
4111+ "\n"
4112+);
4113+
4114+U_BOOT_CMD(
4115+ ibinit, 2, 0, interfaceboard_init,
4116+ "ibinit - Detect Interface Board and initialize IO \n",
4117+ "\n"
4118+);
4119+
4120+U_BOOT_CMD(
4121+ vrctl, 2, 0, prog_vrctl,
4122+ "vrctl - Programs new voltage (mV) to Bfin Core [850 .. 1300]\n",
4123+ "\n"
4124+);
4125+
4126+/**********************************************************************
4127+ *************** Metrologic *********************************
4128+ **********************************************************************/
4129+
4130 #endif /* CFG_CMD_LOADB */
4131
4132 /* -------------------------------------------------------------------- */
4133diff --git a/u-boot-1.1.6/common/cmd_mem.c b/u-boot-1.1.6/common/cmd_mem.c
4134index 3f1023c..154035e 100644
4135--- a/u-boot-1.1.6/common/cmd_mem.c
4136+++ b/u-boot-1.1.6/common/cmd_mem.c
4137@@ -1028,6 +1028,95 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
4138 }
4139
4140
4141+/*
4142+ * Runs memory test from CFG_MEMTEST_END to CFG_MEMTEST_END.
4143+ */
4144+
4145+int FullRamTest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
4146+{
4147+ int testcnt = 0;
4148+ int test_passed = 1;
4149+
4150+ vu_long *addr_to_fail;
4151+ vu_long *current_addr;
4152+
4153+ vu_long *start = (ulong *)CFG_MEMTEST_START;
4154+ vu_long *end = (ulong *)CFG_MEMTEST_END;
4155+
4156+ ulong pattern1 = 0x5a5a5a5a;
4157+ ulong pattern2 = 0xa5a5a5a5;
4158+
4159+ ulong val1, val2;
4160+
4161+ if (argc > 2)
4162+ {
4163+ printf("Performing Full Ram Test from 0x%08x to 0x%08x:\n", CFG_MEMTEST_START, CFG_MEMTEST_END - 1);
4164+ }
4165+
4166+ if ( argc < 2 )
4167+ {
4168+ addr_to_fail = (ulong *)CFG_MEMTEST_END + 0x1000;
4169+ }
4170+ else if (argc > 1)
4171+ {
4172+ addr_to_fail = (ulong *)simple_strtoul(argv[1], NULL, 16);
4173+ }
4174+
4175+ for(current_addr = CFG_MEMTEST_START; current_addr < CFG_MEMTEST_END; current_addr+=2)
4176+ {
4177+ if ( (((long)current_addr & 0x3ffff) == 0) && (argc > 2) )
4178+ { /* print progress */
4179+ printf("0x%08x\r", current_addr);
4180+ }
4181+
4182+ test_passed = 0;
4183+
4184+ if (current_addr != addr_to_fail)
4185+ { /* Run memory test here */
4186+ *current_addr = pattern1;
4187+ *(current_addr + 1) = pattern2;
4188+
4189+ val1 = *current_addr;
4190+ val2 = *(current_addr + 1);
4191+
4192+ if ((val1 == pattern1) && (val2 == pattern2))
4193+ {
4194+ test_passed = 1;
4195+ }
4196+
4197+ testcnt += 2;
4198+ }
4199+
4200+ if (test_passed < 1 && argc > 2)
4201+ {
4202+ if (val1 != pattern1)
4203+ {
4204+ printf("Ram test failed at 0x%08x\n", current_addr);
4205+ printf("\rExpected 0x%08x but read 0x%08x \r\n", val1, pattern1);
4206+ }
4207+ if (val2 != pattern2)
4208+ {
4209+ printf("Ram test failed at 0x%08x\n", current_addr + 1);
4210+ printf("\rExpected 0x%08x but read 0x%08x \r\n", val2, pattern2);
4211+ }
4212+ }
4213+ }
4214+
4215+ if (argc > 2)
4216+ {
4217+ printf("\nDone testing 0x%08x addresses!\n", testcnt);
4218+ }
4219+
4220+ if (argc == 1)
4221+ {
4222+ printf("%d\r\n", test_passed);
4223+ }
4224+
4225+ return test_passed ;
4226+}
4227+
4228+
4229+
4230 /* Modify memory.
4231 *
4232 * Syntax:
4233@@ -1314,6 +1403,13 @@ U_BOOT_CMD(
4234 " - simple RAM read/write test\n"
4235 );
4236
4237+U_BOOT_CMD(
4238+ ramtest, 3, 1, FullRamTest,
4239+ "ramtest - RAM test covering all but the last MB of Memory\n",
4240+ "[loop]\n"
4241+ " - RAM read/write test\n"
4242+);
4243+
4244 #ifdef CONFIG_MX_CYCLIC
4245 U_BOOT_CMD(
4246 mdc, 4, 1, do_mem_mdc,
4247diff --git a/u-boot-1.1.6/common/interface_select.c b/u-boot-1.1.6/common/interface_select.c
4248new file mode 100644
4249index 0000000..d571105
4250--- /dev/null
4251+++ b/u-boot-1.1.6/common/interface_select.c
4252@@ -0,0 +1,526 @@
4253+#include <common.h>
4254+#include <watchdog.h>
4255+#include <config.h>
4256+#include <asm/blackfin.h>
4257+#include <i2c.h>
4258+#include <Metrologic_Hardware.h>
4259+#include <metro_pf.h>
4260+
4261+/* All transfers are described by this data structure */
4262+struct i2c_msg {
4263+ u16 addr; /* slave address */
4264+ u16 flags;
4265+#define I2C_M_STOP 0x2
4266+#define I2C_M_RD 0x1
4267+ u16 len; /* msg length */
4268+ u8 *buf; /* pointer to msg data */
4269+};
4270+
4271+#define CLR_PIN(x) set_pfx_level(x, 0)
4272+#define SET_PIN(x) set_pfx_level(x, 1)
4273+#define GPDRX_OUT(x) set_pfx_dir(x, 1)
4274+#define GPDRX_IN(x) set_pfx_dir(x, 0)
4275+
4276+
4277+//extern int i2c_transfer(struct i2c_msg *msg);
4278+extern int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
4279+extern int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
4280+
4281+BOARD_FEATURE board_desc[] = {
4282+ { KBW_BOARD, 17 , 31 },
4283+ { LASER_EMULATION_BOARD, 33 , 47 },
4284+ { IBM_BOARD, 49 , 63 },
4285+ { OCIA_BOARD, 65 , 79 },
4286+ { LS_USB_HID_BOARD, 81 , 95 },
4287+ { LS_USB_POS_BOARD, 97 , 111 },
4288+ { FS_USB_BOARD, 113, 127 },
4289+ { BLUETOOTH_BOARD, 129, 143 },
4290+ { MULTIFUN_IBM_USB_BOARD, 145, 159 },
4291+ { RS232_BOARD, 241, 255 },
4292+ { 0, 0 , 0 }
4293+};
4294+
4295+static unsigned char NOVRAM_Array[NOVRAM_SIGNATURE_LEN + NOVRAMSIZE];
4296+static int Detected_Interface_Board;
4297+static int AtoD_Value;
4298+
4299+/*
4300+ * Function will return rd_len if successful
4301+ */
4302+
4303+#if defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
4304+
4305+int
4306+Psoc_I2C_Xfer(unsigned char *wr_msg, int wr_len,
4307+ unsigned char *rd_msg, int rd_len,
4308+ int wait_uSec,
4309+ int timeout_uSec)
4310+{
4311+ int i2c_clk;
4312+ int num_polls;
4313+ int i, j;
4314+ struct i2c_msg msg;
4315+
4316+#if defined(CONFIG_HARD_I2C)
4317+ i2c_clk = CFG_I2C_SPEED;
4318+#elif defined(CONFIG_SOFT_I2C)
4319+ i2c_clk = CFG_I2C_SPEED;
4320+#else
4321+ i2c_clk = 50000;
4322+#endif
4323+
4324+ num_polls = timeout_uSec * i2c_clk / (1000000 * rd_len * 10);
4325+
4326+ if (num_polls < 1)
4327+ {
4328+ num_polls = 1;
4329+ }
4330+
4331+ i2c_init(i2c_clk, PSOC_CHIP_ADDR);
4332+
4333+// PRINTD("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x, buf0=0x%x\n", chip, addr, alen, len, buffer[0]);
4334+
4335+ /* write out command */
4336+
4337+ for (i = 0; i < NUM_RETRIES_ON_XFER; i++)
4338+ {
4339+ msg.addr = PSOC_CHIP_ADDR;
4340+ msg.flags = 0;
4341+ msg.len = wr_len;
4342+ msg.buf = wr_msg;
4343+
4344+// if (i2c_transfer(&msg)) return -1;
4345+ if (i2c_write(PSOC_CHIP_ADDR, 0, 0, wr_msg, wr_len))
4346+ {
4347+ return -1;
4348+ }
4349+
4350+ /* Wait */
4351+
4352+ if (wait_uSec)
4353+ {
4354+ udelay(wait_uSec);
4355+ }
4356+
4357+ /* poll */
4358+ for (j = 0; j < num_polls; j++)
4359+ {
4360+ msg.addr = PSOC_CHIP_ADDR;
4361+ msg.flags = I2C_M_RD;
4362+ msg.len = rd_len;
4363+ msg.buf = rd_msg;
4364+
4365+// if (i2c_transfer(&msg)) return -1;
4366+ if (i2c_read(PSOC_CHIP_ADDR, 0, 0, rd_msg, rd_len))
4367+ {
4368+ return -1;
4369+ }
4370+
4371+ /* Check for valid data here */
4372+
4373+ if (rd_msg[0] == 0x06)
4374+ { /* Data is valid */
4375+ return rd_len;
4376+ }
4377+
4378+ udelay(10);
4379+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
4380+ }
4381+
4382+ udelay(10 * 1000);
4383+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
4384+ }
4385+
4386+ /* Timeout */
4387+
4388+ return -2;
4389+}
4390+
4391+static int
4392+ReadAtoD(void)
4393+{
4394+ unsigned char wr_msg[1], rd_msg[2];
4395+
4396+ wr_msg[0] = 'a';
4397+
4398+ if (Psoc_I2C_Xfer(wr_msg, 1, rd_msg, 2, PSOC_COMMAND_DELAY_USEC, PSOC_COMMAND_TIMEOUT_USEC) < 0)
4399+ {
4400+#if defined(DEBUG_METRO_IO)
4401+ printf("Error reading I2C()\r\n");
4402+#endif
4403+ return -1;
4404+ }
4405+ else
4406+ {
4407+#if defined(DEBUG_METRO_IO)
4408+ printf("I2C read completed()\r\n");
4409+#endif
4410+ return (int)rd_msg[1];
4411+ }
4412+}
4413+
4414+
4415+static int
4416+ReadInterfaceType(void)
4417+{
4418+ int i;
4419+
4420+#if defined(DEBUG_METRO_IO)
4421+ printf("start ReadAtoD()\r\n");
4422+#endif
4423+#if (CONFIG_METROLOGIC_VQ2D_REV)
4424+ AtoD_Value = Read_VQ_AtoD();
4425+#else
4426+ AtoD_Value = ReadAtoD();
4427+#endif
4428+#if defined(DEBUG_METRO_IO)
4429+ printf("returned from ReadAtoD()\r\n");
4430+#endif
4431+
4432+ if (AtoD_Value < 0 || AtoD_Value > 255)
4433+ {
4434+ return UNKNOWN_INTERFACE_BOARD;
4435+ }
4436+
4437+ for (i = 0; i < NUM_SUPPORTED_INTERFACE_BOARD; i++)
4438+ {
4439+ if ((AtoD_Value <= board_desc[i].AtoD_high) && (AtoD_Value >= board_desc[i].AtoD_low))
4440+ {
4441+ return board_desc[i].board_type;
4442+ }
4443+ }
4444+
4445+ return UNKNOWN_INTERFACE_BOARD;
4446+
4447+}
4448+
4449+
4450+//extern int Get_Interface_AtoD_Value(void);
4451+
4452+void
4453+Send_Interface_AtoD_to_kernel(void)
4454+{
4455+ DECLARE_GLOBAL_DATA_PTR;
4456+ char buf[256], buf2[32], *start, *end;
4457+ char *cmdline = getenv ("bootargs");
4458+
4459+ if (cmdline)
4460+ {
4461+ if ((start = strstr (cmdline, "intsel=")) == NULL)
4462+ {
4463+ strcpy (buf, cmdline);
4464+ sprintf(buf2, " intsel=%d", Get_Interface_AtoD_Value());
4465+ strcat (buf, buf2);
4466+ }
4467+ }
4468+
4469+ setenv ("bootargs", buf);
4470+}
4471+
4472+#endif /* CONFIG_METROLOGIC_INTERFACE_DETECTION */
4473+
4474+static int
4475+GetNovram(void)
4476+{
4477+ ulong dev_addr = CFG_DEF_EEPROM_ADDR;
4478+ ulong addr = (ulong)NOVRAM_Array;
4479+ ulong off = CONFIG_START_OFFS;
4480+ ulong cnt = NOVRAM_SIGNATURE_LEN + NOVRAMSIZE;
4481+ int i;
4482+
4483+ if (eeprom_read (dev_addr, off, (uchar *) addr, cnt))
4484+ {
4485+ return -1;
4486+ }
4487+
4488+ for (i = 0; i < NOVRAM_SIGNATURE_LEN; i++)
4489+ {
4490+ if (NOVRAM_Array[i] != NOVRAM_SIGNATURE[i])
4491+ {
4492+ return -1;
4493+ }
4494+ }
4495+
4496+ return 1;
4497+}
4498+
4499+static uchar
4500+get_NOVRAM_Data(int addr)
4501+{
4502+ if (addr < 0 || addr > NOVRAMSIZE)
4503+ {
4504+ return 0;
4505+ }
4506+ return NOVRAM_Array[addr + NOVRAM_SIGNATURE_LEN];
4507+}
4508+
4509+void
4510+Configure_RTS_Pin(void)
4511+{
4512+#if defined(RTS_PIN)
4513+#if defined(CONFIG_RTS_DEFAULT_ASSERTED)
4514+ if ( !(get_NOVRAM_Data(158) & (1 << 6)) )
4515+ { /* Not support for Metrologic RTS / CTS */
4516+ CLR_PIN(RTS_PIN);
4517+ }
4518+ else
4519+ {
4520+ if (get_NOVRAM_Data(245) & 1)
4521+ { /* RTS level inverted, asserts high */
4522+ SET_PIN(RTS_PIN);
4523+ }
4524+ else
4525+ { /* RTS level normal, asserts low */
4526+ CLR_PIN(RTS_PIN);
4527+ }
4528+ }
4529+#else
4530+ if (get_NOVRAM_Data(245) & 1)
4531+ { /* RTS level inverted, idles low */
4532+ CLR_PIN(RTS_PIN);
4533+ }
4534+ else
4535+ { /* RTS level normal, idles high */
4536+ SET_PIN(RTS_PIN);
4537+ }
4538+#endif
4539+ GPDRX_OUT(RTS_PIN);
4540+#endif
4541+}
4542+
4543+void
4544+Configure_Interface_IO(void)
4545+{
4546+ if (GetNovram() < 0)
4547+ { /* Error reading NOVRAM */
4548+ int i;
4549+
4550+ for (i = 0; i < NOVRAM_SIGNATURE_LEN + NOVRAMSIZE; i++)
4551+ {
4552+ NOVRAM_Array[i] = 0;
4553+ }
4554+ }
4555+
4556+#if (CONFIG_METROLOGIC_VQ2D_REV)
4557+ int interface_board;
4558+
4559+ interface_board = Detected_Interface_Board = ReadInterfaceType();
4560+
4561+ Configure_VQ2D_Interface_IO(interface_board);
4562+
4563+ if (interface_board == RS232_BOARD)
4564+ {
4565+ Configure_RTS_Pin();
4566+ }
4567+
4568+#elif defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
4569+ int interface_board;
4570+
4571+ interface_board = Detected_Interface_Board = ReadInterfaceType();
4572+
4573+#if defined(DEBUG_METRO_IO)
4574+ printf("returned from ReadInterfaceType()\r\n");
4575+#endif
4576+
4577+ if (interface_board == KBW_BOARD)
4578+ {
4579+#ifdef CONFIG_SUPPORT_KBW
4580+ /* configure RTS as KBClock (output low, but inverted to high
4581+ * at the interface board) for the KBW. If in stand-alone mode, kb
4582+ * would still be funcitonal and responsible for handshaking until
4583+ * kbw driver is loaded */
4584+ CLR_PIN(KBCLOCK_PIN);
4585+ GPDRX_OUT(KBCLOCK_PIN);
4586+
4587+ CLR_PIN(KBW_GATE_PIN); /* enable feed thru */
4588+#endif
4589+#if defined(DEBUG_METRO_IO)
4590+ printf("configured KBW\r\n");
4591+#endif
4592+ }
4593+ else if (interface_board == RS232_BOARD || interface_board == LS_USB_HID_BOARD ||
4594+ interface_board == LS_USB_POS_BOARD || interface_board == FS_USB_BOARD ||
4595+ interface_board == IBM_BOARD )
4596+ { /* read the novram and set up the RTS level */
4597+#if defined(RTS_PIN)
4598+#if defined(CONFIG_RTS_DEFAULT_ASSERTED)
4599+ if ( !(get_NOVRAM_Data(158) & (1 << 6)) )
4600+ { /* Not support for Metrologic RTS / CTS */
4601+ CLR_PIN(RTS_PIN);
4602+ }
4603+ else
4604+ {
4605+ if (get_NOVRAM_Data(245) & 1)
4606+ { /* RTS level inverted, asserts high */
4607+ SET_PIN(RTS_PIN);
4608+ }
4609+ else
4610+ { /* RTS level normal, asserts low */
4611+ CLR_PIN(RTS_PIN);
4612+ }
4613+ }
4614+#else
4615+ if (get_NOVRAM_Data(245) & 1)
4616+ { /* RTS level inverted, idles low */
4617+ CLR_PIN(RTS_PIN);
4618+ }
4619+ else
4620+ { /* RTS level normal, idles high */
4621+ SET_PIN(RTS_PIN);
4622+ }
4623+#endif
4624+
4625+ GPDRX_OUT(RTS_PIN);
4626+#endif /* RTS_PIN */
4627+
4628+#ifdef CONFIG_SUPPORT_IBM
4629+ if (interface_board == IBM_BOARD)
4630+ {
4631+ CLR_PIN(IBM_RS4680_RESET_PIN);
4632+#if defined(DEBUG_METRO_IO)
4633+ printf("configured IBM\r\n");
4634+#endif
4635+ }
4636+#endif
4637+ }
4638+ else if (interface_board == MULTIFUN_IBM_USB_BOARD)
4639+ {
4640+#ifdef CONFIG_SUPPORT_MULTIFUNC
4641+ /* set up the I/O for MULTIFUN_IBM_USB_BOARD */
4642+ CLR_PIN(IBM_RS4680_RESET_PIN);
4643+ /* RTS line is used as CTS to Interface signal, for now, signal that Focus is
4644+ * ready to receive data so that nothing is lock up.
4645+ * CAUTION!!! Must confirm this is the right handshaking protocol */
4646+ CLR_PIN(RTS_PIN);
4647+ GPDRX_OUT(RTS_PIN);
4648+#endif
4649+ }
4650+ else if (interface_board == BLUETOOTH_BOARD)
4651+ {
4652+#ifdef CONFIG_SUPPORT_BLUETOOTH
4653+ // configure IO pins
4654+ GPDRX_OUT(BT_LDO_PIN);
4655+ GPDRX_OUT(BT_RESET_PIN);
4656+ GPDRX_OUT(BT_SWITCH_PIN);
4657+ GPDRX_OUT(BLUE_LED_PIN);
4658+ GPDRX_OUT(WHITE_LED_PIN);
4659+ GPDRX_OUT(YELLOW_LED_PIN);
4660+
4661+ GPDRX_IN(BT_CONN_PIN);
4662+ GPDRX_IN(BT_RDY_PIN);
4663+ GPDRX_IN(BT_DSR_PIN);
4664+ GPDRX_IN(TRIG_PIN);
4665+
4666+ SET_PIN(BT_LDO_PIN);
4667+ SET_PIN(BT_RESET_PIN);
4668+ SET_PIN(BT_SWITCH_PIN);
4669+
4670+ CLR_PIN(FOCUS_KBWEN_PIN);
4671+ GPDRX_OUT(FOCUS_KBWEN_PIN);
4672+#endif
4673+ }
4674+
4675+ /* Now enable the KB_GATE, BTRTS, PC_CLK, PC_DATA signals */
4676+#ifdef FOCUS_KBWEN_PIN
4677+ if (FOCUS_KBWEN_PIN >= 0 && FOCUS_KBWEN_PIN < 48)
4678+ {
4679+ CLR_PIN(FOCUS_KBWEN_PIN); /* Active low signal */
4680+ GPDRX_OUT(FOCUS_KBWEN_PIN);
4681+ }
4682+#endif
4683+
4684+#else /* CONFIG_METROLOGIC_INTERFACE_DETECTION */
4685+
4686+#if defined(RTS_PIN)
4687+ if (get_NOVRAM_Data(245) & 1)
4688+ { /* RTS level inverted, idles low */
4689+ CLR_PIN(RTS_PIN);
4690+ }
4691+ else
4692+ { /* RTS level normal, idles high */
4693+ SET_PIN(RTS_PIN);
4694+ }
4695+
4696+ GPDRX_OUT(RTS_PIN);
4697+
4698+#endif /* RTS_PIN */
4699+
4700+#endif /* CONFIG_METROLOGIC_INTERFACE_DETECTION */
4701+
4702+ __builtin_bfin_ssync();
4703+
4704+}
4705+
4706+void
4707+DisplayInterfaceBoard(void)
4708+{
4709+ printf(INTERFACE_TYPE_TITLE);
4710+ printf(" ");
4711+
4712+ switch(Detected_Interface_Board)
4713+ {
4714+ case RS232_BOARD:
4715+ printf(INTERFACE_RS232_TEXT);
4716+ break;
4717+
4718+ case KBW_BOARD:
4719+ printf(INTERFACE_KBW_TEXT);
4720+ break;
4721+
4722+ case LASER_EMULATION_BOARD:
4723+ printf(INTERFACE_UNKNOWN_TEXT);
4724+ break;
4725+
4726+ case IBM_BOARD:
4727+ printf(INTERFACE_IBM_TEXT);
4728+ break;
4729+
4730+ case OCIA_BOARD:
4731+ printf(INTERFACE_OCIA_TEXT);
4732+ break;
4733+
4734+ case LS_USB_HID_BOARD:
4735+ printf(INTERFACE_LSUSBHID_TEXT);
4736+ break;
4737+
4738+ case LS_USB_POS_BOARD:
4739+ printf(INTERFACE_LSUSBPOS_TEXT);
4740+ break;
4741+
4742+ case FS_USB_BOARD:
4743+ printf(INTERFACE_FSUSB_TEXT);
4744+ break;
4745+
4746+ case BLUETOOTH_BOARD:
4747+ printf(INTERFACE_BLUETOOTH_TEXT);
4748+ break;
4749+
4750+ case MULTIFUN_IBM_USB_BOARD:
4751+ printf(INTERFACE_MULTIFUN_USB_IBM_TEXT);
4752+ break;
4753+
4754+ default:
4755+ printf(INTERFACE_UNKNOWN_TEXT);
4756+ break;
4757+
4758+ }
4759+
4760+ printf("\n");
4761+
4762+ printf("IntSel A/D = %d\r\n", AtoD_Value);
4763+
4764+ printf("Novram[155] = 0x%02x\r\n", get_NOVRAM_Data(155));
4765+}
4766+
4767+
4768+int Get_Interface_Board_Type(void)
4769+{
4770+ return Detected_Interface_Board;
4771+}
4772+
4773+
4774+int Get_Interface_AtoD_Value(void)
4775+{
4776+ return AtoD_Value;
4777+}
4778+
4779diff --git a/u-boot-1.1.6/common/main.c b/u-boot-1.1.6/common/main.c
4780index 0659c5b..6acc222 100644
4781--- a/u-boot-1.1.6/common/main.c
4782+++ b/u-boot-1.1.6/common/main.c
4783@@ -28,11 +28,14 @@
4784 /* #define DEBUG */
4785
4786 #include <common.h>
4787+#include <config.h>
4788 #include <watchdog.h>
4789 #include <command.h>
4790 #ifdef CONFIG_MODEM_SUPPORT
4791 #include <malloc.h> /* for free() prototype */
4792 #endif
4793+#include <Metrologic_Hardware.h>
4794+#include <metro_pf.h>
4795
4796 #ifdef CFG_HUSH_PARSER
4797 #include <hush.h>
4798@@ -49,6 +52,14 @@ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* fo
4799 #endif
4800
4801 extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
4802+extern int Get_Interface_Board_Type(void);
4803+extern int get_pfx_level(int pf_num);
4804+extern int set_pfx_level(int pf_num, int level);
4805+extern void set_cmdline_active(int active);
4806+
4807+#define SET_PIN(gpio_pin) { set_pfx_level(gpio_pin, 1); }
4808+#define CLR_PIN(gpio_pin) { set_pfx_level(gpio_pin, 0); }
4809+#define GET_PIN_LEVEL(gpio_pin) ( get_pfx_level(gpio_pin) )
4810
4811
4812 #define MAX_DELAY_STOP_STR 32
4813@@ -84,16 +95,66 @@ int do_mdm_init = 0;
4814 extern void mdm_init(void); /* defined in board.c */
4815 #endif
4816
4817+#ifdef CONFIG_SUPPORT_BLUETOOTH
4818+static __inline__ int bluetooth_abortboot(void)
4819+{
4820+ int abort = 0;
4821+
4822+ if(Get_Interface_Board_Type() == BLUETOOTH_BOARD)
4823+ {
4824+ int ct, prev_state, curr_state;
4825+ int lh_trans = 0; // number of low-to-high transitions on trigger pin
4826+ int hl_trans = 0; // number of high-to-low transitions on trigger pin
4827+
4828+ prev_state = GET_PIN_LEVEL(TRIG_PIN);
4829+
4830+ if (prev_state == 0) // enter this loop only if trigger is initially activated
4831+ // (trigger is active-low)
4832+ {
4833+ SET_PIN(YELLOW_LED_PIN);
4834+ CLR_PIN(WHITE_LED_PIN);
4835+ CLR_PIN(BLUE_LED_PIN);
4836+
4837+ // Sit in a loop for 2 seconds and check trigger pin every 5 ms
4838+ for(ct=0; ct<400; ct++)
4839+ {
4840+ udelay(5000);
4841+ curr_state = GET_PIN_LEVEL(TRIG_PIN);
4842+ if (curr_state == 1 && prev_state == 0)
4843+ {
4844+ lh_trans++;
4845+ }
4846+ else if (curr_state == 0 && prev_state == 1)
4847+ {
4848+ hl_trans++;
4849+ }
4850+ prev_state = curr_state;
4851+
4852+ if(lh_trans > 1 && hl_trans > 1) // double-click detected
4853+ {
4854+ abort = 1;
4855+ break;
4856+ }
4857+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
4858+ }
4859+ }
4860+ }
4861+ return abort;
4862+}
4863+#endif
4864+
4865 /***************************************************************************
4866 * Watch for 'delay' seconds for autoboot stop or autoboot delay string.
4867 * returns: 0 - no key string, allow autoboot
4868 * 1 - got key string, abort
4869 */
4870+
4871 #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
4872 # if defined(CONFIG_AUTOBOOT_KEYED)
4873 static __inline__ int abortboot(int bootdelay)
4874 {
4875 int abort = 0;
4876+ int try_once = 0;
4877 uint64_t etime = endtick(bootdelay);
4878 struct {
4879 char* str;
4880@@ -150,6 +211,13 @@ static __inline__ int abortboot(int bootdelay)
4881 presskey_max = presskey_max > delaykey[i].len ?
4882 presskey_max : delaykey[i].len;
4883
4884+#if defined CONFIG_ZERO_BOOTDELAY_CHECK
4885+ if (bootdelay == 0 && delaykey[i].len == 1)
4886+ {
4887+ try_once = 1;
4888+ }
4889+#endif
4890+
4891 # if DEBUG_BOOTKEYS
4892 printf("%s key:<%s>\n",
4893 delaykey[i].retry ? "delay" : "stop",
4894@@ -157,10 +225,23 @@ static __inline__ int abortboot(int bootdelay)
4895 # endif
4896 }
4897
4898+#if defined CONFIG_ZERO_BOOTDELAY_CHECK
4899+ if (try_once)
4900+ {
4901+ udelay(10000);
4902+
4903+ if (tstc())
4904+ {
4905+ presskey [presskey_len ++] = getc();
4906+ }
4907+ }
4908+#endif
4909+
4910 /* In order to keep up with incoming data, check timeout only
4911 * when catch up.
4912 */
4913- while (!abort && get_ticks() <= etime) {
4914+ while (try_once > 0 || (!abort && get_ticks() <= etime)) {
4915+ try_once = 0;
4916 for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) {
4917 if (delaykey[i].len > 0 &&
4918 presskey_len >= delaykey[i].len &&
4919@@ -198,6 +279,13 @@ static __inline__ int abortboot(int bootdelay)
4920 puts ("key timeout\n");
4921 # endif
4922
4923+#ifdef CONFIG_SUPPORT_BLUETOOTH
4924+ if (!abort)
4925+ {
4926+ abort = bluetooth_abortboot();
4927+ }
4928+#endif
4929+
4930 #ifdef CONFIG_SILENT_CONSOLE
4931 if (abort) {
4932 /* permanently enable normal console output */
4933@@ -274,6 +362,13 @@ static __inline__ int abortboot(int bootdelay)
4934
4935 putc ('\n');
4936
4937+#ifdef CONFIG_SUPPORT_BLUETOOTH
4938+ if (!abort)
4939+ {
4940+ abort = bluetooth_abortboot();
4941+ }
4942+#endif
4943+
4944 #ifdef CONFIG_SILENT_CONSOLE
4945 if (abort) {
4946 /* permanently enable normal console output */
4947@@ -443,7 +538,31 @@ void main_loop (void)
4948 }
4949 #endif
4950
4951- /*
4952+#ifdef CONFIG_SUPPORT_BLUETOOTH
4953+ if(Get_Interface_Board_Type() == BLUETOOTH_BOARD)
4954+ {
4955+ CLR_PIN(YELLOW_LED_PIN);
4956+ SET_PIN(WHITE_LED_PIN); // indicates to user that we have entered the bootloader
4957+
4958+ CLR_PIN(BT_RESET_PIN); // reset Bluetooth chip
4959+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
4960+ udelay(5000);
4961+ SET_PIN(BT_RESET_PIN);
4962+
4963+ if (gd->baudrate != 115200)
4964+ {
4965+ // Reinitialize serial to 115200 bps
4966+ gd->baudrate = 115200;
4967+ serial_setbrg();
4968+
4969+ udelay(50000);
4970+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
4971+ }
4972+ set_cmdline_active(1);
4973+ }
4974+#endif
4975+
4976+ /*
4977 * Main Loop for Monitor Command Processing
4978 */
4979 #ifdef CFG_HUSH_PARSER
4980diff --git a/u-boot-1.1.6/common/metro_pf.c b/u-boot-1.1.6/common/metro_pf.c
4981new file mode 100644
4982index 0000000..de6421b
4983--- /dev/null
4984+++ b/u-boot-1.1.6/common/metro_pf.c
4985@@ -0,0 +1,318 @@
4986+#include <common.h>
4987+#include <config.h>
4988+#include <asm/blackfin.h>
4989+#include <metro_pf.h>
4990+
4991+#ifndef PF_bit
4992+#define PF_bit(pfx) ( 1 << (pfx & 0x0f) )
4993+#endif
4994+
4995+//#ifndef CSYNC
4996+//#define CSYNC asm("csync;")
4997+//#endif
4998+
4999+//#ifndef SSYNC
5000+//#define SSYNC asm("ssync;")
5001+//#endif
5002+
5003+int Metro_set_pfx_dir(int pf_num, int dir, int initial_val);
5004+int Metro_get_pfx_dir(int pf_num);
5005+
5006+#if (defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) || \
5007+ defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) )
5008+
5009+
5010+static void
5011+Metro_set_portF_pfx_dir(int pf_num, int dir, int initial_val)
5012+{
5013+ unsigned short mask = PF_bit(pf_num);
5014+
5015+ *pPORTFIO_MASKA_CLEAR = mask;
5016+ *pPORTFIO_MASKB_CLEAR = mask;
5017+ *pPORTF_FER &= ~mask;
5018+ SSYNC();
5019+ if (dir)
5020+ {
5021+ *pPORTFIO_INEN &= ~mask;
5022+ if (initial_val > 0)
5023+ *pPORTFIO_SET = mask;
5024+ else if (initial_val == 0)
5025+ *pPORTFIO_CLEAR = mask;
5026+ *pPORTFIO_DIR |= mask;
5027+ *pPORTFIO_POLAR &= ~mask;
5028+ *pPORTFIO_EDGE &= ~mask;
5029+ *pPORTFIO_BOTH &= ~mask;
5030+ }
5031+ else
5032+ {
5033+ *pPORTFIO_DIR &= ~mask;
5034+ *pPORTFIO_POLAR &= ~mask;
5035+ *pPORTFIO_EDGE &= ~mask;
5036+ *pPORTFIO_BOTH &= ~mask;
5037+ *pPORTFIO_INEN |= mask;
5038+ }
5039+ SSYNC();
5040+}
5041+
5042+static void
5043+Metro_set_portG_pfx_dir(int pf_num, int dir, int initial_val)
5044+{
5045+ unsigned short mask = PF_bit(pf_num);
5046+
5047+ *pPORTGIO_MASKA_CLEAR = mask;
5048+ *pPORTGIO_MASKB_CLEAR = mask;
5049+ *pPORTG_FER &= ~mask;
5050+ SSYNC();
5051+ if (dir)
5052+ {
5053+ *pPORTGIO_INEN &= ~mask;
5054+ if (initial_val > 0)
5055+ *pPORTGIO_SET = mask;
5056+ else if (initial_val == 0)
5057+ *pPORTGIO_CLEAR = mask;
5058+ *pPORTGIO_DIR |= mask;
5059+ *pPORTGIO_POLAR &= ~mask;
5060+ *pPORTGIO_EDGE &= ~mask;
5061+ *pPORTGIO_BOTH &= ~mask;
5062+ }
5063+ else
5064+ {
5065+ *pPORTGIO_DIR &= ~mask;
5066+ *pPORTGIO_POLAR &= ~mask;
5067+ *pPORTGIO_EDGE &= ~mask;
5068+ *pPORTGIO_BOTH &= ~mask;
5069+ *pPORTGIO_INEN |= mask;
5070+ }
5071+ SSYNC();
5072+}
5073+
5074+static void
5075+Metro_set_portH_pfx_dir(int pf_num, int dir, int initial_val)
5076+{
5077+ unsigned short mask = PF_bit(pf_num);
5078+
5079+ *pPORTHIO_MASKA_CLEAR = mask;
5080+ *pPORTHIO_MASKB_CLEAR = mask;
5081+ *pPORTH_FER &= ~mask;
5082+ SSYNC();
5083+ if (dir)
5084+ {
5085+ *pPORTHIO_INEN &= ~mask;
5086+ if (initial_val > 0)
5087+ *pPORTHIO_SET = mask;
5088+ else if (initial_val == 0)
5089+ *pPORTHIO_CLEAR = mask;
5090+ *pPORTHIO_DIR |= mask;
5091+ *pPORTHIO_POLAR &= ~mask;
5092+ *pPORTHIO_EDGE &= ~mask;
5093+ *pPORTHIO_BOTH &= ~mask;
5094+ }
5095+ else
5096+ {
5097+ *pPORTHIO_DIR &= ~mask;
5098+ *pPORTHIO_POLAR &= ~mask;
5099+ *pPORTHIO_EDGE &= ~mask;
5100+ *pPORTHIO_BOTH &= ~mask;
5101+ *pPORTHIO_INEN |= mask;
5102+ }
5103+ SSYNC();
5104+}
5105+
5106+int
5107+Metro_set_pfx_dir(int pf_num, int dir, int initial_val)
5108+{
5109+ unsigned long flags;
5110+
5111+ if (pf_num < 0 || pf_num >= 48 || dir < 0 || dir > 1)
5112+ {
5113+ return -1;
5114+ }
5115+
5116+ local_irq_save(flags);
5117+ if (pf_num < 16)
5118+ {
5119+ Metro_set_portF_pfx_dir(pf_num, dir, initial_val);
5120+ }
5121+ else if (pf_num < 32)
5122+ {
5123+ Metro_set_portG_pfx_dir(pf_num, dir, initial_val);
5124+ }
5125+ else
5126+ {
5127+ Metro_set_portH_pfx_dir(pf_num, dir, initial_val);
5128+ }
5129+ local_irq_restore(flags);
5130+
5131+ return 0;
5132+}
5133+
5134+#elif (defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) || \
5135+ defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) )
5136+
5137+int
5138+Metro_set_pfx_dir(int pf_num, int dir, int initial_val)
5139+{
5140+ unsigned long flags;
5141+ unsigned short mask;
5142+
5143+ if (pf_num < 0 || pf_num >= 16 || dir < 0 || dir > 1)
5144+ {
5145+ return -1;
5146+ }
5147+
5148+ mask = PF_bit(pf_num);
5149+ local_irq_save(flags);
5150+
5151+ *pFIO_MASKA_C = mask;
5152+ *pFIO_MASKB_C = mask;
5153+
5154+ if (dir)
5155+ { /* Output */
5156+ *pFIO_INEN &= ~mask;
5157+ if (initial_val > 0)
5158+ *pFIO_FLAG_S = mask;
5159+ else if (initial_val == 0)
5160+ *pFIO_FLAG_C = mask;
5161+ *pFIO_DIR |= mask;
5162+ *pFIO_POLAR &= ~mask;
5163+ *pFIO_EDGE &= ~mask;
5164+ *pFIO_BOTH &= ~mask;
5165+ }
5166+ else
5167+ { /* Input */
5168+ *pFIO_DIR &= ~mask;
5169+ *pFIO_POLAR &= ~mask;
5170+ *pFIO_EDGE &= ~mask;
5171+ *pFIO_BOTH &= ~mask;
5172+ *pFIO_INEN |= mask;
5173+ }
5174+
5175+ SSYNC();
5176+ local_irq_restore(flags);
5177+ return 0;
5178+}
5179+
5180+#else
5181+#error "undefined platform!!!"
5182+#endif
5183+
5184+
5185+#if (defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) || \
5186+ defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) )
5187+
5188+/*
5189+ * Return value:
5190+ * <0: error
5191+ * 0: input
5192+ * 1: output
5193+ */
5194+int
5195+Metro_get_pfx_dir(int pf_num)
5196+{
5197+ unsigned short mask = PF_bit(pf_num);
5198+
5199+ if (pf_num < 0 || pf_num >= 48)
5200+ {
5201+ return -1;
5202+ }
5203+
5204+ if (pf_num < 16)
5205+ {
5206+ if (*pPORTF_FER & mask)
5207+ return -1;
5208+
5209+ return (*pPORTFIO_DIR & mask ? 1 : 0);
5210+ }
5211+ else if (pf_num < 32)
5212+ {
5213+ if (*pPORTG_FER & mask)
5214+ return -1;
5215+
5216+ return (*pPORTGIO_DIR & mask ? 1 : 0);
5217+ }
5218+ else
5219+ {
5220+ if (*pPORTH_FER & mask)
5221+ return -1;
5222+
5223+ return (*pPORTHIO_DIR & mask ? 1 : 0);
5224+ }
5225+}
5226+
5227+#elif (defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) || \
5228+ defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) )
5229+
5230+
5231+/*
5232+ * Return value:
5233+ * <0: error
5234+ * 0: input
5235+ * 1: output
5236+ */
5237+int
5238+Metro_get_pfx_dir(int pf_num)
5239+{
5240+ if (pf_num < 0 || pf_num >= 16)
5241+ {
5242+ return -1;
5243+ }
5244+ return (*pFIO_DIR & PF_bit(pf_num) ? 1 : 0);
5245+}
5246+
5247+#endif
5248+
5249+int
5250+set_pfx_dir(int pf_num, int dir)
5251+{
5252+ return Metro_set_pfx_dir(pf_num, dir, -1);
5253+}
5254+
5255+int
5256+get_pfx_dir(int pf_num)
5257+{
5258+ return Metro_get_pfx_dir(pf_num);
5259+}
5260+
5261+int
5262+get_pfx_level(int pf_num)
5263+{
5264+#if (defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) || \
5265+ defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) )
5266+ if (pf_num < 0 || pf_num >= 48)
5267+ {
5268+ return -1;
5269+ }
5270+#elif (defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) || \
5271+ defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) )
5272+
5273+ if (pf_num < 0 || pf_num >= 16)
5274+ {
5275+ return -1;
5276+ }
5277+#endif
5278+
5279+ return Metro_get_pfx_level(pf_num);
5280+}
5281+
5282+int
5283+set_pfx_level(int pf_num, int level)
5284+{
5285+#if (defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) || \
5286+ defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) )
5287+
5288+ if (pf_num < 0 || pf_num >= 48 || level < 0 || level > 1)
5289+ {
5290+ return -1;
5291+ }
5292+#elif (defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) || \
5293+ defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) )
5294+
5295+ if (pf_num < 0 || pf_num >= 16 || level < 0 || level > 1)
5296+ {
5297+ return -1;
5298+ }
5299+#endif
5300+
5301+ Metro_set_pfx_level(pf_num, level);
5302+ return 0;
5303+}
5304diff --git a/u-boot-1.1.6/cpu/blackfin/i2c.c b/u-boot-1.1.6/cpu/blackfin/i2c.c
5305index 0524680..8eaf509 100644
5306--- a/u-boot-1.1.6/cpu/blackfin/i2c.c
5307+++ b/u-boot-1.1.6/cpu/blackfin/i2c.c
5308@@ -14,6 +14,7 @@
5309
5310 #include <asm/blackfin.h>
5311 #include <asm/mach-common/bits/twi.h>
5312+#if defined DEBUG_I2C
5313
5314 #define debugi(fmt, args...) \
5315 debug( \
5316@@ -22,6 +23,10 @@
5317 bfin_read_TWI_MASTER_STAT(), bfin_read_TWI_FIFO_STAT(), bfin_read_TWI_INT_STAT(), \
5318 __func__, __LINE__, ## args)
5319
5320+#else
5321+#define debugi(fmt, args...)
5322+#endif
5323+
5324 #ifdef TWI0_CLKDIV
5325 #define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val)
5326 #define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val)
5327@@ -126,14 +131,18 @@ static int wait_for_completion(struct i2c_msg *msg)
5328 *
5329 * @return: 0 if things worked, non-0 if things failed
5330 */
5331-static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags)
5332+int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags)
5333 {
5334+#if (0)
5335 uchar addr_buffer[] = {
5336 (addr >> 0),
5337 (addr >> 8),
5338 (addr >> 16),
5339 };
5340- struct i2c_msg msg = {
5341+#else
5342+ uchar addr_buffer[3 + 256];
5343+#endif
5344+ struct i2c_msg msg = {
5345 .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
5346 .buf = buffer,
5347 .len = len,
5348@@ -141,8 +150,29 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len,
5349 .alen = alen,
5350 };
5351 int ret;
5352-
5353- memset(buffer, 0xff, len);
5354+ int i;
5355+
5356+ addr_buffer[0] = (addr >> 0);
5357+ addr_buffer[0] = (addr >> 8);
5358+ addr_buffer[0] = (addr >> 16);
5359+
5360+ if (flags == 0) /* write operation */
5361+ {
5362+ if (len > 255)
5363+ {
5364+ len = 255;
5365+ }
5366+
5367+ msg.alen = alen + len;
5368+ msg.len = 0;
5369+
5370+ for (i = 0; i < len; i++)
5371+ {
5372+ addr_buffer[alen + i] = buffer[i];
5373+ }
5374+ }
5375+
5376+//??? memset(buffer, 0xff, len);
5377 debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ",
5378 chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr"));
5379
5380diff --git a/u-boot-1.1.6/cpu/blackfin/serial.c b/u-boot-1.1.6/cpu/blackfin/serial.c
5381index f7b935d..1e5ebda 100644
5382--- a/u-boot-1.1.6/cpu/blackfin/serial.c
5383+++ b/u-boot-1.1.6/cpu/blackfin/serial.c
5384@@ -41,6 +41,7 @@
5385 */
5386
5387 #include <common.h>
5388+#include <config.h>
5389 #include <watchdog.h>
5390 #include <asm/blackfin.h>
5391 #include <asm/mach-common/bits/uart.h>
5392@@ -51,6 +52,28 @@
5393
5394 #include "serial.h"
5395
5396+
5397+#include <Metrologic_Hardware.h>
5398+#include <metro_pf.h>
5399+
5400+extern int Get_Interface_Board_Type(void);
5401+extern int get_pfx_level(int pf_num);
5402+extern int set_pfx_level(int pf_num, int level);
5403+
5404+#define SET_PIN(gpio_pin) { set_pfx_level(gpio_pin, 1); }
5405+#define CLR_PIN(gpio_pin) { set_pfx_level(gpio_pin, 0); }
5406+#define GET_PIN_LEVEL(gpio_pin) ( get_pfx_level(gpio_pin) )
5407+
5408+#ifdef CONFIG_SUPPORT_BLUETOOTH
5409+static int bt_state = 0;
5410+#endif
5411+static int cmdline_active = 0;
5412+
5413+void set_cmdline_active(int active)
5414+{
5415+ cmdline_active = active;
5416+}
5417+
5418 #ifdef CONFIG_DEBUG_SERIAL
5419 uint16_t cached_lsr[256];
5420 uint16_t cached_rbr[256];
5421@@ -114,6 +137,14 @@ int serial_init(void)
5422
5423 void serial_putc(const char c)
5424 {
5425+#ifdef CONFIG_SUPPORT_BLUETOOTH
5426+ if (Get_Interface_Board_Type() == BLUETOOTH_BOARD && bt_state == 0)
5427+ {
5428+ WATCHDOG_RESET();
5429+ return;
5430+ }
5431+#endif
5432+
5433 /* send a \r for compatibility */
5434 if (c == '\n')
5435 serial_putc('\r');
5436@@ -138,16 +169,67 @@ void serial_putc(const char c)
5437 int serial_tstc(void)
5438 {
5439 WATCHDOG_RESET();
5440+#ifdef CONFIG_SUPPORT_BLUETOOTH
5441+ {
5442+ int bt_pin_level;
5443+ int board_type = Get_Interface_Board_Type();
5444+
5445+ if(board_type == BLUETOOTH_BOARD && cmdline_active == 1)
5446+ {
5447+ bt_pin_level = GET_PIN_LEVEL(BT_CONN_PIN);
5448+ if (bt_state == 0 && bt_pin_level == 1)
5449+ {
5450+ bt_state = 1;
5451+ SET_PIN(BLUE_LED_PIN);
5452+ udelay(500000);
5453+ WATCHDOG_RESET();
5454+ }
5455+ if (bt_state == 1 && bt_pin_level == 0)
5456+ {
5457+ bt_state = 0;
5458+ CLR_PIN(BLUE_LED_PIN);
5459+ udelay(500000);
5460+ WATCHDOG_RESET();
5461+ }
5462+ }
5463+ }
5464+#endif
5465+
5466 return (uart_lsr_read() & DR) ? 1 : 0;
5467 }
5468
5469 int serial_getc(void)
5470 {
5471 uint16_t uart_rbr_val;
5472+#ifdef CONFIG_SUPPORT_BLUETOOTH
5473+ int board_type = Get_Interface_Board_Type();
5474+ int bt_pin_level;
5475+#endif
5476+
5477
5478 /* wait for data ! */
5479 while (!serial_tstc())
5480+ {
5481+#ifdef CONFIG_SUPPORT_BLUETOOTH
5482+ if(board_type == BLUETOOTH_BOARD && cmdline_active == 1)
5483+ {
5484+ bt_pin_level = GET_PIN_LEVEL(BT_CONN_PIN);
5485+ if (bt_state == 0 && bt_pin_level == 1)
5486+ {
5487+ bt_state = 1;
5488+ SET_PIN(BLUE_LED_PIN);
5489+ udelay(500000);
5490+ }
5491+ if (bt_state == 1 && bt_pin_level == 0)
5492+ {
5493+ bt_state = 0;
5494+ CLR_PIN(BLUE_LED_PIN);
5495+ udelay(500000);
5496+ }
5497+ }
5498+#endif
5499 continue;
5500+ }
5501
5502 /* grab the new byte */
5503 uart_rbr_val = *pUART_RBR;
5504diff --git a/u-boot-1.1.6/examples/Makefile b/u-boot-1.1.6/examples/Makefile
5505index 75753a2..85df974 100644
5506--- a/u-boot-1.1.6/examples/Makefile
5507+++ b/u-boot-1.1.6/examples/Makefile
5508@@ -89,9 +89,23 @@ BIN += sched.bin
5509 endif
5510
5511 ifeq ($(ARCH),blackfin)
5512+
5513+ifneq ($(BOARD),bf537-stamp)
5514+ifneq ($(BOARD),bf533-stamp)
5515+ifneq ($(BOARD),Focus)
5516+ifneq ($(BOARD),Orbit3)
5517+ifneq ($(BOARD),VuQuest2D)
5518+
5519 ELF += smc91111_eeprom smsc9118_eeprom
5520 SREC += smc91111_eeprom.srec smsc9118_eeprom.srec
5521 BIN += smc91111_eeprom.bin smsc9118_eeprom.bin
5522+
5523+endif # VuQuest2D
5524+endif # Orbit3
5525+endif # Focus
5526+endif # bf533-stamp
5527+endif # bf537-stamp
5528+
5529 endif
5530
5531 # The following example is pretty 8xx specific...
5532diff --git a/u-boot-1.1.6/include/Metrologic_Hardware.h b/u-boot-1.1.6/include/Metrologic_Hardware.h
5533new file mode 100644
5534index 0000000..19506af
5535--- /dev/null
5536+++ b/u-boot-1.1.6/include/Metrologic_Hardware.h
5537@@ -0,0 +1,69 @@
5538+#ifndef METROLOGIC_HARDWARE_H
5539+#define METROLOGIC_HARDWARE_H
5540+
5541+#define PADDING_CHAR 0xff
5542+#define SPI_SECTOR_SIZE 0x10000
5543+#define PADDING_BUFF_SIZE SPI_SECTOR_SIZE
5544+
5545+#define U_BOOT_START_OFFS 0x000000
5546+#define CONFIG_START_OFFS 0x040000
5547+#define KERNEL_START_OFFS 0x060000
5548+#define FILSYS_START_OFFS 0x100000
5549+
5550+#define FLASH_PARTITION_START 0x20000000
5551+
5552+#define U_BOOT_START_ADDR ( U_BOOT_START_OFFS + FLASH_PARTITION_START)
5553+#define CONFIG_START_ADDR ( CONFIG_START_OFFS + FLASH_PARTITION_START)
5554+#define KERNEL_START_ADDR ( KERNEL_START_OFFS + FLASH_PARTITION_START)
5555+#define FILSYS_START_ADDR ( FILSYS_START_OFFS + FLASH_PARTITION_START)
5556+
5557+#define NOVRAM_SIGNATURE "MTLG FOCUS TK 04"
5558+#define NOVRAM_SIGNATURE_LEN 16
5559+#define NOVRAMSIZE 512
5560+
5561+
5562+#define NUM_RETRIES_ON_XFER 3
5563+#define PSOC_COMMAND_DELAY_USEC 100
5564+#define PSOC_COMMAND_TIMEOUT_USEC 1000
5565+
5566+#define PSOC_CHIP_ADDR 0x71
5567+
5568+
5569+#define INTERFACE_TYPE_TITLE "Interface Board:"
5570+#define INTERFACE_RS232_TEXT "RS232"
5571+#define INTERFACE_KBW_TEXT "Keyboard Wedge"
5572+#define INTERFACE_IBM_TEXT "IBM"
5573+#define INTERFACE_OCIA_TEXT "OCIA"
5574+#define INTERFACE_LSUSBHID_TEXT "USB-HID"
5575+#define INTERFACE_LSUSBPOS_TEXT "USB-POS"
5576+#define INTERFACE_FSUSB_TEXT "FS-USB"
5577+#define INTERFACE_BLUETOOTH_TEXT "BlueTooth"
5578+#define INTERFACE_MULTIFUN_USB_IBM_TEXT "MultiFunction"
5579+#define INTERFACE_UNKNOWN_TEXT "Unknown"
5580+
5581+#define UNKNOWN_INTERFACE_BOARD 999
5582+
5583+enum {
5584+ RS232_BOARD = 0,
5585+ KBW_BOARD,
5586+ LASER_EMULATION_BOARD,
5587+ IBM_BOARD,
5588+ OCIA_BOARD,
5589+ LS_USB_HID_BOARD,
5590+ LS_USB_POS_BOARD,
5591+ FS_USB_BOARD,
5592+ BLUETOOTH_BOARD,
5593+ MULTIFUN_IBM_USB_BOARD,
5594+ NUM_SUPPORTED_INTERFACE_BOARD
5595+};
5596+
5597+typedef struct {
5598+ int board_type;
5599+ int AtoD_low;
5600+ int AtoD_high;
5601+} BOARD_FEATURE;
5602+
5603+extern BOARD_FEATURE board_desc[];
5604+
5605+
5606+#endif /* METROLOGIC_HARDWARE_H */
5607diff --git a/u-boot-1.1.6/include/asm-blackfin/blackfin-config-post.h b/u-boot-1.1.6/include/asm-blackfin/blackfin-config-post.h
5608index 0ad4715..ec5bc5d 100644
5609--- a/u-boot-1.1.6/include/asm-blackfin/blackfin-config-post.h
5610+++ b/u-boot-1.1.6/include/asm-blackfin/blackfin-config-post.h
5611@@ -9,55 +9,7 @@
5612 #ifndef __ASM_BLACKFIN_CONFIG_POST_H__
5613 #define __ASM_BLACKFIN_CONFIG_POST_H__
5614
5615-/* Sanity check CONFIG_BFIN_CPU */
5616-#ifndef CONFIG_BFIN_CPU
5617-# error CONFIG_BFIN_CPU: your board config needs to define this
5618-#endif
5619-
5620-/* Make sure the structure is properly aligned */
5621-#if ((CFG_GBL_DATA_ADDR & -4) != CFG_GBL_DATA_ADDR)
5622-# error CFG_GBL_DATA_ADDR: must be 4 byte aligned
5623-#endif
5624-
5625-/* Set default CONFIG_VCO_HZ if need be */
5626-#if !defined(CONFIG_VCO_HZ)
5627-# if (CONFIG_CLKIN_HALF == 0)
5628-# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
5629-# else
5630-# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2)
5631-# endif
5632-#endif
5633-
5634-/* Set default CONFIG_CCLK_HZ if need be */
5635-#if !defined(CONFIG_CCLK_HZ)
5636-# if (CONFIG_PLL_BYPASS == 0)
5637-# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV)
5638-# else
5639-# define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
5640-# endif
5641-#endif
5642-
5643-/* Set default CONFIG_SCLK_HZ if need be */
5644-#if !defined(CONFIG_SCLK_HZ)
5645-# if (CONFIG_PLL_BYPASS == 0)
5646-# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV)
5647-# else
5648-# define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
5649-# endif
5650-#endif
5651-
5652-/* Since we use these to program PLL registers directly,
5653- * make sure the values are sane and won't screw us up.
5654- */
5655-#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT
5656-# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63)
5657-#endif
5658-#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF
5659-# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1
5660-#endif
5661-#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS
5662-# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1
5663-#endif
5664+#include <asm/blackfin_clocks.h>
5665
5666 /* Using L1 scratch pad makes sense for everyone by default. */
5667 #ifndef CMD_LINE_ADDR
5668diff --git a/u-boot-1.1.6/include/asm-blackfin/blackfin_clocks.h b/u-boot-1.1.6/include/asm-blackfin/blackfin_clocks.h
5669new file mode 100644
5670index 0000000..67c7709
5671--- /dev/null
5672+++ b/u-boot-1.1.6/include/asm-blackfin/blackfin_clocks.h
5673@@ -0,0 +1,56 @@
5674+#ifndef __ASM_BLACKFIN_CLOCKS_H__
5675+#define __ASM_BLACKFIN_CLOCKS_H__
5676+
5677+/* Sanity check CONFIG_BFIN_CPU */
5678+#ifndef CONFIG_BFIN_CPU
5679+# error CONFIG_BFIN_CPU: your board config needs to define this
5680+#endif
5681+
5682+/* Set default CONFIG_CCLK_HZ if need be */
5683+#if !defined(CONFIG_CCLK_HZ)
5684+# if (CONFIG_PLL_BYPASS == 0)
5685+# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV)
5686+# else
5687+# define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
5688+# endif
5689+#endif
5690+
5691+/* Set default CONFIG_SCLK_HZ if need be */
5692+#if !defined(CONFIG_SCLK_HZ)
5693+# if (CONFIG_PLL_BYPASS == 0)
5694+# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV)
5695+# else
5696+# define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
5697+# endif
5698+#endif
5699+
5700+/* Since we use these to program PLL registers directly,
5701+ * make sure the values are sane and won't screw us up.
5702+ */
5703+#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT
5704+# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63)
5705+#endif
5706+#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF
5707+# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1
5708+#endif
5709+#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS
5710+# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1
5711+#endif
5712+
5713+/* Make sure the structure is properly aligned */
5714+#if ((CFG_GBL_DATA_ADDR & -4) != CFG_GBL_DATA_ADDR)
5715+# error CFG_GBL_DATA_ADDR: must be 4 byte aligned
5716+#endif
5717+
5718+/* Set default CONFIG_VCO_HZ if need be */
5719+#if !defined(CONFIG_VCO_HZ)
5720+# if (CONFIG_CLKIN_HALF == 0)
5721+# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
5722+# else
5723+# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2)
5724+# endif
5725+#endif
5726+
5727+#endif /* __ASM_BLACKFIN_CLOCKS_H__ */
5728+
5729+
5730diff --git a/u-boot-1.1.6/include/asm-blackfin/mem_init.h b/u-boot-1.1.6/include/asm-blackfin/mem_init.h
5731new file mode 100644
5732index 0000000..e413aae
5733--- /dev/null
5734+++ b/u-boot-1.1.6/include/asm-blackfin/mem_init.h
5735@@ -0,0 +1,338 @@
5736+#ifndef __ASM_MEM_INIT_H__
5737+#define __ASM_MEM_INIT_H__
5738+/*
5739+ * U-boot - mem_init.h Header file for memory initialization
5740+ *
5741+ * Copyright (c) 2005 blackfin.uclinux.org
5742+ *
5743+ * See file CREDITS for list of people who contributed to this
5744+ * project.
5745+ *
5746+ * This program is free software; you can redistribute it and/or
5747+ * modify it under the terms of the GNU General Public License as
5748+ * published by the Free Software Foundation; either version 2 of
5749+ * the License, or (at your option) any later version.
5750+ *
5751+ * This program is distributed in the hope that it will be useful,
5752+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
5753+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5754+ * GNU General Public License for more details.
5755+ *
5756+ * You should have received a copy of the GNU General Public License
5757+ * along with this program; if not, write to the Free Software
5758+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
5759+ * MA 02111-1307 USA
5760+ */
5761+#include <asm/blackfin_clocks.h>
5762+
5763+#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \
5764+ CONFIG_MEM_MT48LC64M4A2FB_7E || \
5765+ CONFIG_MEM_MT48LC16M8A2TG_75 || \
5766+ CONFIG_MEM_MT48LC8M16A2TG_7E || \
5767+ CONFIG_MEM_MT48LC8M32B2B5_7 || \
5768+ CONFIG_MEM_MT48LC32M8A2_75 || \
5769+ CONFIG_MEM_IS42S16160B_7 \
5770+ )
5771+
5772+ #if ( CONFIG_SCLK_HZ > 119402985 )
5773+ #define SDRAM_tRP TRP_2
5774+ #define SDRAM_tRP_num 2
5775+ #define SDRAM_tRAS TRAS_7
5776+ #define SDRAM_tRAS_num 7
5777+ #define SDRAM_tRCD TRCD_2
5778+ #define SDRAM_tWR TWR_2
5779+ #endif
5780+ #if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 )
5781+ #define SDRAM_tRP TRP_2
5782+ #define SDRAM_tRP_num 2
5783+ #define SDRAM_tRAS TRAS_6
5784+ #define SDRAM_tRAS_num 6
5785+ #define SDRAM_tRCD TRCD_2
5786+ #define SDRAM_tWR TWR_2
5787+ #endif
5788+ #if ( CONFIG_SCLK_HZ > 89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 )
5789+ #define SDRAM_tRP TRP_2
5790+ #define SDRAM_tRP_num 2
5791+ #define SDRAM_tRAS TRAS_5
5792+ #define SDRAM_tRAS_num 5
5793+ #define SDRAM_tRCD TRCD_2
5794+ #define SDRAM_tWR TWR_2
5795+ #endif
5796+ #if ( CONFIG_SCLK_HZ > 74626866 ) && ( CONFIG_SCLK_HZ <= 89552239 )
5797+ #define SDRAM_tRP TRP_2
5798+ #define SDRAM_tRP_num 2
5799+ #define SDRAM_tRAS TRAS_4
5800+ #define SDRAM_tRAS_num 4
5801+ #define SDRAM_tRCD TRCD_2
5802+ #define SDRAM_tWR TWR_2
5803+ #endif
5804+ #if ( CONFIG_SCLK_HZ > 66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 )
5805+ #define SDRAM_tRP TRP_2
5806+ #define SDRAM_tRP_num 2
5807+ #define SDRAM_tRAS TRAS_3
5808+ #define SDRAM_tRAS_num 3
5809+ #define SDRAM_tRCD TRCD_2
5810+ #define SDRAM_tWR TWR_2
5811+ #endif
5812+ #if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
5813+ #define SDRAM_tRP TRP_1
5814+ #define SDRAM_tRP_num 1
5815+ #define SDRAM_tRAS TRAS_3
5816+ #define SDRAM_tRAS_num 3
5817+ #define SDRAM_tRCD TRCD_1
5818+ #define SDRAM_tWR TWR_2
5819+ #endif
5820+ #if ( CONFIG_SCLK_HZ > 44776119 ) && ( CONFIG_SCLK_HZ <= 59701493 )
5821+ #define SDRAM_tRP TRP_1
5822+ #define SDRAM_tRP_num 1
5823+ #define SDRAM_tRAS TRAS_3
5824+ #define SDRAM_tRAS_num 3
5825+ #define SDRAM_tRCD TRCD_1
5826+ #define SDRAM_tWR TWR_2
5827+ #endif
5828+ #if ( CONFIG_SCLK_HZ > 29850746 ) && ( CONFIG_SCLK_HZ <= 44776119 )
5829+ #define SDRAM_tRP TRP_1
5830+ #define SDRAM_tRP_num 1
5831+ #define SDRAM_tRAS TRAS_2
5832+ #define SDRAM_tRAS_num 2
5833+ #define SDRAM_tRCD TRCD_1
5834+ #define SDRAM_tWR TWR_2
5835+ #endif
5836+ #if ( CONFIG_SCLK_HZ <= 29850746 )
5837+ #define SDRAM_tRP TRP_1
5838+ #define SDRAM_tRP_num 1
5839+ #define SDRAM_tRAS TRAS_1
5840+ #define SDRAM_tRAS_num 1
5841+ #define SDRAM_tRCD TRCD_1
5842+ #define SDRAM_tWR TWR_2
5843+ #endif
5844+#endif
5845+
5846+#if (CONFIG_MEM_IS42S16160B_7)
5847+ /*SDRAM INFORMATION: */
5848+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
5849+ #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
5850+ #define SDRAM_CL CL_2
5851+#endif
5852+
5853+#if (CONFIG_MEM_MT48LC16M16A2TG_75)
5854+ /*SDRAM INFORMATION: */
5855+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
5856+ #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
5857+ #define SDRAM_CL CL_3
5858+#endif
5859+
5860+#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
5861+ /*SDRAM INFORMATION: */
5862+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
5863+ #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
5864+ #define SDRAM_CL CL_2
5865+#endif
5866+
5867+#if (CONFIG_MEM_MT48LC16M8A2TG_75)
5868+ /*SDRAM INFORMATION: */
5869+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
5870+ #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
5871+ #define SDRAM_CL CL_3
5872+#endif
5873+
5874+#if (CONFIG_MEM_MT48LC32M8A2_75)
5875+ /*SDRAM INFORMATION: */
5876+#define SDRAM_Tref 64 /* Refresh period in milliseconds */
5877+#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
5878+#define SDRAM_CL CL_3
5879+#endif
5880+
5881+#if (CONFIG_MEM_MT48LC8M16A2TG_7E)
5882+ /*SDRAM INFORMATION: */
5883+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
5884+ #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
5885+ #define SDRAM_CL CL_2
5886+#endif
5887+
5888+#if (CONFIG_MEM_MT48LC8M32B2B5_7)
5889+ /*SDRAM INFORMATION: */
5890+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
5891+ #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
5892+ #define SDRAM_CL CL_3
5893+#endif
5894+
5895+#if ( CONFIG_MEM_SIZE == 128 )
5896+ #define SDRAM_SIZE EBSZ_128
5897+#endif
5898+#if ( CONFIG_MEM_SIZE == 64 )
5899+ #define SDRAM_SIZE EBSZ_64
5900+#endif
5901+#if ( CONFIG_MEM_SIZE == 32 )
5902+ #define SDRAM_SIZE EBSZ_32
5903+#endif
5904+#if ( CONFIG_MEM_SIZE == 16 )
5905+ #define SDRAM_SIZE EBSZ_16
5906+#endif
5907+#if ( CONFIG_MEM_ADD_WDTH == 11 )
5908+ #define SDRAM_WIDTH EBCAW_11
5909+#endif
5910+#if ( CONFIG_MEM_ADD_WDTH == 10 )
5911+ #define SDRAM_WIDTH EBCAW_10
5912+#endif
5913+#if ( CONFIG_MEM_ADD_WDTH == 9 )
5914+ #define SDRAM_WIDTH EBCAW_9
5915+#endif
5916+#if ( CONFIG_MEM_ADD_WDTH == 8 )
5917+ #define SDRAM_WIDTH EBCAW_8
5918+#endif
5919+
5920+#define mem_SDBCTL SDRAM_WIDTH | SDRAM_SIZE | EBE
5921+
5922+/* Equation from section 17 (p17-46) of BF533 HRM */
5923+#define mem_SDRRC ((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
5924+
5925+/* Enable SCLK Out */
5926+#define mem_SDGCTL ( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS )
5927+
5928+#define flash_EBIU_AMBCTL_WAT ( ( CONFIG_FLASH_SPEED_BWAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
5929+#define flash_EBIU_AMBCTL_RAT ( ( CONFIG_FLASH_SPEED_BRAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
5930+#define flash_EBIU_AMBCTL_HT ( ( CONFIG_FLASH_SPEED_BHT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) )
5931+#define flash_EBIU_AMBCTL_ST ( ( CONFIG_FLASH_SPEED_BST * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
5932+#define flash_EBIU_AMBCTL_TT ( ( CONFIG_FLASH_SPEED_BTT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
5933+
5934+#if (flash_EBIU_AMBCTL_TT > 3 )
5935+ #define flash_EBIU_AMBCTL0_TT B0TT_4
5936+#endif
5937+#if (flash_EBIU_AMBCTL_TT == 3 )
5938+ #define flash_EBIU_AMBCTL0_TT B0TT_3
5939+#endif
5940+#if (flash_EBIU_AMBCTL_TT == 2 )
5941+ #define flash_EBIU_AMBCTL0_TT B0TT_2
5942+#endif
5943+#if (flash_EBIU_AMBCTL_TT < 2 )
5944+ #define flash_EBIU_AMBCTL0_TT B0TT_1
5945+#endif
5946+
5947+#if (flash_EBIU_AMBCTL_ST > 3 )
5948+ #define flash_EBIU_AMBCTL0_ST B0ST_4
5949+#endif
5950+#if (flash_EBIU_AMBCTL_ST == 3 )
5951+ #define flash_EBIU_AMBCTL0_ST B0ST_3
5952+#endif
5953+#if (flash_EBIU_AMBCTL_ST == 2 )
5954+ #define flash_EBIU_AMBCTL0_ST B0ST_2
5955+#endif
5956+#if (flash_EBIU_AMBCTL_ST < 2 )
5957+ #define flash_EBIU_AMBCTL0_ST B0ST_1
5958+#endif
5959+
5960+#if (flash_EBIU_AMBCTL_HT > 2 )
5961+ #define flash_EBIU_AMBCTL0_HT B0HT_3
5962+#endif
5963+#if (flash_EBIU_AMBCTL_HT == 2 )
5964+ #define flash_EBIU_AMBCTL0_HT B0HT_2
5965+#endif
5966+#if (flash_EBIU_AMBCTL_HT == 1 )
5967+ #define flash_EBIU_AMBCTL0_HT B0HT_1
5968+#endif
5969+#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
5970+ #define flash_EBIU_AMBCTL0_HT B0HT_0
5971+#endif
5972+#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
5973+ #define flash_EBIU_AMBCTL0_HT B0HT_1
5974+#endif
5975+
5976+#if (flash_EBIU_AMBCTL_WAT > 14)
5977+ #define flash_EBIU_AMBCTL0_WAT B0WAT_15
5978+#endif
5979+#if (flash_EBIU_AMBCTL_WAT == 14)
5980+ #define flash_EBIU_AMBCTL0_WAT B0WAT_14
5981+#endif
5982+#if (flash_EBIU_AMBCTL_WAT == 13)
5983+ #define flash_EBIU_AMBCTL0_WAT B0WAT_13
5984+#endif
5985+#if (flash_EBIU_AMBCTL_WAT == 12)
5986+ #define flash_EBIU_AMBCTL0_WAT B0WAT_12
5987+#endif
5988+#if (flash_EBIU_AMBCTL_WAT == 11)
5989+ #define flash_EBIU_AMBCTL0_WAT B0WAT_11
5990+#endif
5991+#if (flash_EBIU_AMBCTL_WAT == 10)
5992+ #define flash_EBIU_AMBCTL0_WAT B0WAT_10
5993+#endif
5994+#if (flash_EBIU_AMBCTL_WAT == 9)
5995+ #define flash_EBIU_AMBCTL0_WAT B0WAT_9
5996+#endif
5997+#if (flash_EBIU_AMBCTL_WAT == 8)
5998+ #define flash_EBIU_AMBCTL0_WAT B0WAT_8
5999+#endif
6000+#if (flash_EBIU_AMBCTL_WAT == 7)
6001+ #define flash_EBIU_AMBCTL0_WAT B0WAT_7
6002+#endif
6003+#if (flash_EBIU_AMBCTL_WAT == 6)
6004+ #define flash_EBIU_AMBCTL0_WAT B0WAT_6
6005+#endif
6006+#if (flash_EBIU_AMBCTL_WAT == 5)
6007+ #define flash_EBIU_AMBCTL0_WAT B0WAT_5
6008+#endif
6009+#if (flash_EBIU_AMBCTL_WAT == 4)
6010+ #define flash_EBIU_AMBCTL0_WAT B0WAT_4
6011+#endif
6012+#if (flash_EBIU_AMBCTL_WAT == 3)
6013+ #define flash_EBIU_AMBCTL0_WAT B0WAT_3
6014+#endif
6015+#if (flash_EBIU_AMBCTL_WAT == 2)
6016+ #define flash_EBIU_AMBCTL0_WAT B0WAT_2
6017+#endif
6018+#if (flash_EBIU_AMBCTL_WAT == 1)
6019+ #define flash_EBIU_AMBCTL0_WAT B0WAT_1
6020+#endif
6021+
6022+#if (flash_EBIU_AMBCTL_RAT > 14)
6023+ #define flash_EBIU_AMBCTL0_RAT B0RAT_15
6024+#endif
6025+#if (flash_EBIU_AMBCTL_RAT == 14)
6026+ #define flash_EBIU_AMBCTL0_RAT B0RAT_14
6027+#endif
6028+#if (flash_EBIU_AMBCTL_RAT == 13)
6029+ #define flash_EBIU_AMBCTL0_RAT B0RAT_13
6030+#endif
6031+#if (flash_EBIU_AMBCTL_RAT == 12)
6032+ #define flash_EBIU_AMBCTL0_RAT B0RAT_12
6033+#endif
6034+#if (flash_EBIU_AMBCTL_RAT == 11)
6035+ #define flash_EBIU_AMBCTL0_RAT B0RAT_11
6036+#endif
6037+#if (flash_EBIU_AMBCTL_RAT == 10)
6038+ #define flash_EBIU_AMBCTL0_RAT B0RAT_10
6039+#endif
6040+#if (flash_EBIU_AMBCTL_RAT == 9)
6041+ #define flash_EBIU_AMBCTL0_RAT B0RAT_9
6042+#endif
6043+#if (flash_EBIU_AMBCTL_RAT == 8)
6044+ #define flash_EBIU_AMBCTL0_RAT B0RAT_8
6045+#endif
6046+#if (flash_EBIU_AMBCTL_RAT == 7)
6047+ #define flash_EBIU_AMBCTL0_RAT B0RAT_7
6048+#endif
6049+#if (flash_EBIU_AMBCTL_RAT == 6)
6050+ #define flash_EBIU_AMBCTL0_RAT B0RAT_6
6051+#endif
6052+#if (flash_EBIU_AMBCTL_RAT == 5)
6053+ #define flash_EBIU_AMBCTL0_RAT B0RAT_5
6054+#endif
6055+#if (flash_EBIU_AMBCTL_RAT == 4)
6056+ #define flash_EBIU_AMBCTL0_RAT B0RAT_4
6057+#endif
6058+#if (flash_EBIU_AMBCTL_RAT == 3)
6059+ #define flash_EBIU_AMBCTL0_RAT B0RAT_3
6060+#endif
6061+#if (flash_EBIU_AMBCTL_RAT == 2)
6062+ #define flash_EBIU_AMBCTL0_RAT B0RAT_2
6063+#endif
6064+#if (flash_EBIU_AMBCTL_RAT == 1)
6065+ #define flash_EBIU_AMBCTL0_RAT B0RAT_1
6066+#endif
6067+
6068+
6069+//#define flash_EBIU_AMBCTL0 flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN
6070+#define CONFIG_FLASH_SPEED_RDYEN 0
6071+#define flash_EBIU_AMBCTL0 flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN
6072+
6073+#endif
6074diff --git a/u-boot-1.1.6/include/configs/Focus.h b/u-boot-1.1.6/include/configs/Focus.h
6075new file mode 100644
6076index 0000000..e56c362
6077--- /dev/null
6078+++ b/u-boot-1.1.6/include/configs/Focus.h
6079@@ -0,0 +1,381 @@
6080+/*
6081+ * U-boot - Configuration file for BF537 STAMP board
6082+ */
6083+
6084+#ifndef __CONFIG_FOCUS_H__
6085+#define __CONFIG_FOCUS_H__
6086+
6087+#include <asm/blackfin-config-pre.h>
6088+
6089+
6090+#ifndef __ADSPBF534__
6091+#define __ADSPBF534__
6092+#endif
6093+#define METROLOGIC_PLATFORM "Focus"
6094+#define SUPPORT_NETWORKING 0
6095+#define CONFIG_SILENT_CONSOLE 1
6096+#define CONFIG_BAUDRATE 115200
6097+#define CONFIG_LOADADDR 0x800000
6098+
6099+//#define METROLOGIC_FLASH_BOOT_ENV_PARAM "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
6100+
6101+#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
6102+ "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
6103+
6104+#define CFG_PROMPT "bootldr> "
6105+#define CONFIG_ZERO_BOOTDELAY_CHECK
6106+#define CONFIG_AUTOBOOT_KEYED 1
6107+#define CONFIG_AUTOBOOT_STOP_STR "\033"
6108+#define CONFIG_MEM_MT48LC16M16A2TG_75 1
6109+//#define CONFIG_MEM_IS42S16160B_7 1
6110+
6111+//#define CONFIG_DEBUG_EARLY_SERIAL 1
6112+//#define DEBUG_BOOTKEYS 1
6113+//#define DEBUG 1
6114+//#define DEBUG_METRO_IO 1
6115+//#define DEBUG_I2C 1
6116+
6117+// We don't have a parallel flash chip there
6118+#define CFG_NO_FLASH
6119+
6120+
6121+ /*
6122+ * Processor Settings
6123+ */
6124+#define CONFIG_BFIN_CPU bf534-0.2
6125+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
6126+
6127+
6128+/*
6129+ * Clock Settings
6130+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
6131+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
6132+ */
6133+/* CONFIG_CLKIN_HZ is any value in Hz */
6134+#define CONFIG_CLKIN_HZ 25000000
6135+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
6136+/* 1 = CLKIN / 2 */
6137+#define CONFIG_CLKIN_HALF 0
6138+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
6139+/* 1 = bypass PLL */
6140+#define CONFIG_PLL_BYPASS 0
6141+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
6142+/* Values can range from 0-63 (where 0 means 64) */
6143+#define CONFIG_VCO_MULT 20
6144+/* CCLK_DIV controls the core clock divider */
6145+/* Values can be 1, 2, 4, or 8 ONLY */
6146+#define CONFIG_CCLK_DIV 1
6147+/* SCLK_DIV controls the system clock divider */
6148+/* Values can range from 1-15 */
6149+#define CONFIG_SCLK_DIV 4
6150+
6151+
6152+/*
6153+ * Memory Settings
6154+ */
6155+#define CONFIG_MEM_ADD_WDTH 9
6156+#define CONFIG_MEM_SIZE 32
6157+
6158+//#define CONFIG_EBIU_SDRRC_VAL 0x306
6159+//#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
6160+//#define CONFIG_EBIU_SDBCTL_VAL (EBSZ_64 | EBCAW_10 | EBE)
6161+
6162+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
6163+//#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
6164+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
6165+
6166+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for monitor */
6167+#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 384 kB for malloc() (video/spi are big) */
6168+#define CFG_GBL_DATA_SIZE 0x4000
6169+
6170+
6171+/*
6172+ * Network Settings
6173+ */
6174+#if SUPPORT_NETWORKING
6175+#ifndef __ADSPBF534__
6176+#define ADI_CMDS_NETWORK 1
6177+#define CONFIG_BFIN_MAC
6178+#define CONFIG_NETCONSOLE 1
6179+#define CONFIG_NET_MULTI 1
6180+#else
6181+#define ADI_CMDS_NETWORK 0
6182+#endif
6183+#endif
6184+#define CONFIG_HOSTNAME bf537-stamp
6185+/* Uncomment next line to use fixed MAC address */
6186+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
6187+
6188+
6189+/*
6190+ * Flash Settings
6191+ */
6192+#define CFG_FLASH_BASE 0x20000000
6193+#define CFG_FLASH_CFI /* The flash is CFI compatible */
6194+//#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
6195+//#define CFG_FLASH_PROTECTION
6196+#define CFG_MAX_FLASH_BANKS 1
6197+#define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
6198+#define FLASH_SIZE 0x800000
6199+#define CFG_FLASH_SIZE 0x800000
6200+
6201+
6202+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
6203+#define CFG_ENV_IS_IN_EEPROM 1
6204+#define CFG_ENV_OFFSET 0x4000
6205+#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
6206+#else
6207+#define CFG_ENV_IS_IN_FLASH 1
6208+#define CFG_ENV_ADDR 0x20004000
6209+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
6210+#endif
6211+#define CFG_ENV_SIZE 0x2000
6212+#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
6213+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
6214+#define ENV_IS_EMBEDDED
6215+#else
6216+#define ENV_IS_EMBEDDED_CUSTOM
6217+#endif
6218+
6219+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
6220+/* Values can range from 2-65535 */
6221+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
6222+#define CONFIG_SPI
6223+#define CONFIG_SPI_BAUD 2
6224+#define CONFIG_SPI_BAUD_INITBLOCK 3
6225+
6226+
6227+/*
6228+ * I2C Settings
6229+ */
6230+#define CONFIG_HARD_I2C 1 /* I2C TWI */
6231+#define CFG_I2C_SPEED 50000
6232+#define CFG_I2C_SLAVE 0
6233+
6234+
6235+/*
6236+ * NAND Settings
6237+ */
6238+/* #define CONFIG_BF537_NAND */
6239+#ifdef CONFIG_BF537_NAND
6240+# define ADD_NAND_CMD CFG_CMD_NAND
6241+#else
6242+# define ADD_NAND_CMD 0
6243+#endif
6244+
6245+#define CFG_NAND_ADDR 0x20212000
6246+#define CFG_NAND_BASE CFG_NAND_ADDR
6247+#define CFG_MAX_NAND_DEVICE 1
6248+#define SECTORSIZE 512
6249+#define ADDR_COLUMN 1
6250+#define ADDR_PAGE 2
6251+#define ADDR_COLUMN_PAGE 3
6252+#define NAND_ChipID_UNKNOWN 0x00
6253+#define NAND_MAX_FLOORS 1
6254+#define NAND_MAX_CHIPS 1
6255+#define BFIN_NAND_READY PF3
6256+
6257+#define NAND_WAIT_READY(nand) \
6258+ do { \
6259+ int timeout = 0; \
6260+ while(!(*pPORTFIO & PF3)) \
6261+ if (timeout++ > 100000) \
6262+ break; \
6263+ } while (0)
6264+
6265+#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
6266+#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
6267+
6268+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
6269+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
6270+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
6271+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
6272+
6273+
6274+/*
6275+ * CF-CARD IDE-HDD Support
6276+ */
6277+/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
6278+/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
6279+/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
6280+
6281+#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
6282+# define CONFIG_BFIN_IDE 1
6283+# define ADD_IDE_CMD CFG_CMD_IDE
6284+#else
6285+# define ADD_IDE_CMD 0
6286+#endif
6287+
6288+#if defined(CONFIG_BFIN_IDE)
6289+
6290+#define CONFIG_DOS_PARTITION 1
6291+/*
6292+ * IDE/ATA stuff
6293+ */
6294+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
6295+#undef CONFIG_IDE_LED /* no led for ide supported */
6296+#undef CONFIG_IDE_RESET /* no reset for ide supported */
6297+
6298+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
6299+#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
6300+
6301+#undef CONFIG_EBIU_AMBCTL1_VAL
6302+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
6303+
6304+#define CONFIG_CF_ATASEL_DIS 0x20311800
6305+#define CONFIG_CF_ATASEL_ENA 0x20311802
6306+
6307+#if defined(CONFIG_BFIN_TRUE_IDE)
6308+/*
6309+ * Note that these settings aren't for the most part used in include/ata.h
6310+ * when all of the ATA registers are setup
6311+ */
6312+#define CFG_ATA_BASE_ADDR 0x2031C000
6313+#define CFG_ATA_IDE0_OFFSET 0x0000
6314+#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
6315+#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
6316+#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
6317+#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
6318+#endif /* CONFIG_BFIN_TRUE_IDE */
6319+
6320+#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
6321+#define CFG_ATA_BASE_ADDR 0x20211800
6322+#define CFG_ATA_IDE0_OFFSET 0x0000
6323+#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
6324+#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
6325+#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
6326+#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
6327+#endif /* CONFIG_BFIN_CF_IDE */
6328+
6329+#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
6330+#define CFG_ATA_BASE_ADDR 0x20314000
6331+#define CFG_ATA_IDE0_OFFSET 0x0000
6332+#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
6333+#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
6334+#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
6335+#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
6336+
6337+#undef CONFIG_SCLK_DIV
6338+#define CONFIG_SCLK_DIV 8
6339+#endif /* CONFIG_BFIN_HDD_IDE */
6340+
6341+#endif /*CONFIG_BFIN_IDE */
6342+
6343+
6344+/*
6345+ * Misc Settings
6346+ */
6347+#define CONFIG_MISC_INIT_R
6348+//#define CONFIG_RTC_BFIN
6349+
6350+/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
6351+
6352+//#define ADI_CMDS_EXTRA (ADD_IDE_CMD | ADD_NAND_CMD)
6353+
6354+#define CONFIG_BFIN_COMMANDS \
6355+ ( CFG_BFIN_CMD_BOOTLDR | \
6356+ CFG_BFIN_CMD_CPLBINFO )
6357+
6358+/* Define if want to do post memory test */
6359+#undef CONFIG_POST
6360+#ifdef CONFIG_POST
6361+#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
6362+#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
6363+#endif
6364+
6365+/*
6366+ * Pull in common ADI header for remaining command/environment setup
6367+ */
6368+#include <configs/bfin_adi_common.h>
6369+
6370+#include <asm/blackfin-config-post.h>
6371+
6372+#include <asm/mem_init.h>
6373+
6374+
6375+/* Overrides common ADI header's command/environment setup */
6376+
6377+#ifdef CONFIG_BOOTDELAY
6378+#undef CONFIG_BOOTDELAY
6379+#endif
6380+#define CONFIG_BOOTDELAY 10
6381+
6382+#ifdef CONFIG_BOOTCOMMAND
6383+#undef CONFIG_BOOTCOMMAND
6384+#endif
6385+#define CONFIG_BOOTCOMMAND "run flashboot"
6386+
6387+#ifdef CONFIG_BOOTARGS
6388+#undef CONFIG_BOOTARGS
6389+#endif
6390+#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m lpj=496640"
6391+
6392+#ifdef CONFIG_EBIU_SDRRC_VAL
6393+#undef CONFIG_EBIU_SDRRC_VAL
6394+#endif
6395+#define CONFIG_EBIU_SDRRC_VAL mem_SDRRC
6396+
6397+#ifdef CONFIG_EBIU_SDGCTL_VAL
6398+#undef CONFIG_EBIU_SDGCTL_VAL
6399+#endif
6400+#define CONFIG_EBIU_SDGCTL_VAL mem_SDGCTL
6401+
6402+#ifdef CONFIG_EBIU_SDBCTL_VAL
6403+#undef CONFIG_EBIU_SDBCTL_VAL
6404+#endif
6405+#define CONFIG_EBIU_SDBCTL_VAL mem_SDBCTL
6406+
6407+#ifdef CONFIG_EBIU_AMBCTL0_VAL
6408+#undef CONFIG_EBIU_AMBCTL0_VAL
6409+#endif
6410+#define CONFIG_EBIU_AMBCTL0_VAL flash_EBIU_AMBCTL0
6411+
6412+#ifdef CFG_AUTOLOAD
6413+#undef CFG_AUTOLOAD
6414+#endif
6415+#define CFG_AUTOLOAD ""
6416+
6417+ /* CONFIG_SERIAL_BF537 no longer used*/
6418+//#define CONFIG_SERIAL_BF537 1
6419+
6420+#ifdef CONFIG_POST_TEST
6421+#undef CONFIG_POST_TEST
6422+#endif
6423+
6424+#define CONFIG_METROLOGIC_IO_INIT 1
6425+
6426+#define CONFIG_CORE_VOLTAGE_MILLIVOLT 1250
6427+#define CONFIG_DISABLE_CLKIN_OUTPUT 1
6428+
6429+#define CONFIG_METROLOGIC_INTERFACE_DETECTION 1
6430+#define CONFIG_SUPPORT_KBW 1
6431+#define CONFIG_SUPPORT_IBM 1
6432+#define CONFIG_SUPPORT_MULTIFUNC 1
6433+#define CONFIG_SUPPORT_BLUETOOTH 1
6434+//#define CONFIG_RTS_DEFAULT_ASSERTED 1
6435+
6436+#define KBCLOCK_PIN 25
6437+#define RTS_PIN 25
6438+#define KBW_GATE_PIN 27
6439+#define IBM_RS4680_RESET_PIN 27
6440+#define FOCUS_KBWEN_PIN 24
6441+
6442+#define BT_LDO_PIN 27
6443+#define BT_RESET_PIN 26
6444+#define BT_RDY_PIN 37
6445+#define BT_CONN_PIN 35
6446+#define BT_DSR_PIN 34
6447+#define BT_SWITCH_PIN 2
6448+#define TRIG_PIN 41
6449+#define BLUE_LED_PIN 31
6450+#define WHITE_LED_PIN 30
6451+#define YELLOW_LED_PIN 29
6452+
6453+
6454+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
6455+//#define CFG_AUTOLOAD "no"
6456+
6457+
6458+/****************************************************************/
6459+
6460+#endif
6461diff --git a/u-boot-1.1.6/include/configs/IS4980.h b/u-boot-1.1.6/include/configs/IS4980.h
6462new file mode 100644
6463index 0000000..3861d38
6464--- /dev/null
6465+++ b/u-boot-1.1.6/include/configs/IS4980.h
6466@@ -0,0 +1,378 @@
6467+/*
6468+ * U-boot - Configuration file for BF537 STAMP board
6469+ */
6470+
6471+#ifndef __CONFIG_IS4980_H__
6472+#define __CONFIG_IS4980_H__
6473+
6474+#include <asm/blackfin-config-pre.h>
6475+
6476+
6477+#ifndef __ADSPBF534__
6478+#define __ADSPBF534__
6479+#endif
6480+#define METROLOGIC_PLATFORM "IS4980"
6481+#define SUPPORT_NETWORKING 0
6482+#define CONFIG_SILENT_CONSOLE 1
6483+#define CONFIG_BAUDRATE 115200
6484+#define CONFIG_LOADADDR 0x800000
6485+
6486+#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
6487+ "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
6488+
6489+#define CFG_PROMPT "bootldr> "
6490+#define CONFIG_ZERO_BOOTDELAY_CHECK
6491+#define CONFIG_AUTOBOOT_KEYED 1
6492+#define CONFIG_AUTOBOOT_STOP_STR "\033"
6493+#define CONFIG_MEM_MT48LC16M16A2TG_75 1
6494+//#define CONFIG_MEM_IS42S16160B_7 1
6495+
6496+//#define CONFIG_DEBUG_EARLY_SERIAL 1
6497+//#define DEBUG_BOOTKEYS 1
6498+//#define DEBUG 1
6499+//#define DEBUG_METRO_IO 1
6500+//#define DEBUG_I2C 1
6501+
6502+// We don't have a parallel flash chip there
6503+#define CFG_NO_FLASH
6504+
6505+
6506+ /*
6507+ * Processor Settings
6508+ */
6509+#define CONFIG_BFIN_CPU bf534-0.2
6510+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
6511+
6512+
6513+/*
6514+ * Clock Settings
6515+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
6516+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
6517+ */
6518+/* CONFIG_CLKIN_HZ is any value in Hz */
6519+#define CONFIG_CLKIN_HZ 25000000
6520+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
6521+/* 1 = CLKIN / 2 */
6522+#define CONFIG_CLKIN_HALF 0
6523+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
6524+/* 1 = bypass PLL */
6525+#define CONFIG_PLL_BYPASS 0
6526+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
6527+/* Values can range from 0-63 (where 0 means 64) */
6528+#define CONFIG_VCO_MULT 20
6529+/* CCLK_DIV controls the core clock divider */
6530+/* Values can be 1, 2, 4, or 8 ONLY */
6531+#define CONFIG_CCLK_DIV 1
6532+/* SCLK_DIV controls the system clock divider */
6533+/* Values can range from 1-15 */
6534+#define CONFIG_SCLK_DIV 4
6535+
6536+
6537+/*
6538+ * Memory Settings
6539+ */
6540+#define CONFIG_MEM_ADD_WDTH 9
6541+#define CONFIG_MEM_SIZE 32
6542+
6543+//#define CONFIG_EBIU_SDRRC_VAL 0x306
6544+//#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
6545+//#define CONFIG_EBIU_SDBCTL_VAL (EBSZ_64 | EBCAW_10 | EBE)
6546+
6547+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
6548+//#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
6549+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
6550+
6551+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for monitor */
6552+#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 384 kB for malloc() (video/spi are big) */
6553+#define CFG_GBL_DATA_SIZE 0x4000
6554+
6555+
6556+/*
6557+ * Network Settings
6558+ */
6559+#if SUPPORT_NETWORKING
6560+#ifndef __ADSPBF534__
6561+#define ADI_CMDS_NETWORK 1
6562+#define CONFIG_BFIN_MAC
6563+#define CONFIG_NETCONSOLE 1
6564+#define CONFIG_NET_MULTI 1
6565+#else
6566+#define ADI_CMDS_NETWORK 0
6567+#endif
6568+#endif
6569+//#define CONFIG_HOSTNAME bf537-stamp
6570+/* Uncomment next line to use fixed MAC address */
6571+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
6572+
6573+
6574+/*
6575+ * Flash Settings
6576+ */
6577+#define CFG_FLASH_BASE 0x20000000
6578+#define CFG_FLASH_CFI /* The flash is CFI compatible */
6579+//#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
6580+//#define CFG_FLASH_PROTECTION
6581+#define CFG_MAX_FLASH_BANKS 1
6582+#define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
6583+#define FLASH_SIZE 0x800000
6584+#define CFG_FLASH_SIZE 0x800000
6585+
6586+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
6587+#define CFG_ENV_IS_IN_EEPROM 1
6588+#define CFG_ENV_OFFSET 0x4000
6589+#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
6590+#else
6591+#define CFG_ENV_IS_IN_FLASH 1
6592+#define CFG_ENV_ADDR 0x20004000
6593+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
6594+#endif
6595+#define CFG_ENV_SIZE 0x2000
6596+#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
6597+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
6598+#define ENV_IS_EMBEDDED
6599+#else
6600+#define ENV_IS_EMBEDDED_CUSTOM
6601+#endif
6602+
6603+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
6604+/* Values can range from 2-65535 */
6605+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
6606+#define CONFIG_SPI
6607+#define CONFIG_SPI_BAUD 2
6608+#define CONFIG_SPI_BAUD_INITBLOCK 3
6609+
6610+
6611+/*
6612+ * I2C Settings
6613+ */
6614+#define CONFIG_HARD_I2C 1 /* I2C TWI */
6615+#define CFG_I2C_SPEED 50000
6616+#define CFG_I2C_SLAVE 0
6617+
6618+
6619+/*
6620+ * NAND Settings
6621+ */
6622+/* #define CONFIG_BF537_NAND */
6623+#ifdef CONFIG_BF537_NAND
6624+# define ADD_NAND_CMD CFG_CMD_NAND
6625+#else
6626+# define ADD_NAND_CMD 0
6627+#endif
6628+
6629+#define CFG_NAND_ADDR 0x20212000
6630+#define CFG_NAND_BASE CFG_NAND_ADDR
6631+#define CFG_MAX_NAND_DEVICE 1
6632+#define SECTORSIZE 512
6633+#define ADDR_COLUMN 1
6634+#define ADDR_PAGE 2
6635+#define ADDR_COLUMN_PAGE 3
6636+#define NAND_ChipID_UNKNOWN 0x00
6637+#define NAND_MAX_FLOORS 1
6638+#define NAND_MAX_CHIPS 1
6639+#define BFIN_NAND_READY PF3
6640+
6641+#define NAND_WAIT_READY(nand) \
6642+ do { \
6643+ int timeout = 0; \
6644+ while(!(*pPORTFIO & PF3)) \
6645+ if (timeout++ > 100000) \
6646+ break; \
6647+ } while (0)
6648+
6649+#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
6650+#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
6651+
6652+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
6653+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
6654+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
6655+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
6656+
6657+
6658+/*
6659+ * CF-CARD IDE-HDD Support
6660+ */
6661+/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
6662+/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
6663+/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
6664+
6665+#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
6666+# define CONFIG_BFIN_IDE 1
6667+# define ADD_IDE_CMD CFG_CMD_IDE
6668+#else
6669+# define ADD_IDE_CMD 0
6670+#endif
6671+
6672+#if defined(CONFIG_BFIN_IDE)
6673+
6674+#define CONFIG_DOS_PARTITION 1
6675+/*
6676+ * IDE/ATA stuff
6677+ */
6678+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
6679+#undef CONFIG_IDE_LED /* no led for ide supported */
6680+#undef CONFIG_IDE_RESET /* no reset for ide supported */
6681+
6682+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
6683+#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
6684+
6685+#undef CONFIG_EBIU_AMBCTL1_VAL
6686+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
6687+
6688+#define CONFIG_CF_ATASEL_DIS 0x20311800
6689+#define CONFIG_CF_ATASEL_ENA 0x20311802
6690+
6691+#if defined(CONFIG_BFIN_TRUE_IDE)
6692+/*
6693+ * Note that these settings aren't for the most part used in include/ata.h
6694+ * when all of the ATA registers are setup
6695+ */
6696+#define CFG_ATA_BASE_ADDR 0x2031C000
6697+#define CFG_ATA_IDE0_OFFSET 0x0000
6698+#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
6699+#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
6700+#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
6701+#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
6702+#endif /* CONFIG_BFIN_TRUE_IDE */
6703+
6704+#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
6705+#define CFG_ATA_BASE_ADDR 0x20211800
6706+#define CFG_ATA_IDE0_OFFSET 0x0000
6707+#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
6708+#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
6709+#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
6710+#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
6711+#endif /* CONFIG_BFIN_CF_IDE */
6712+
6713+#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
6714+#define CFG_ATA_BASE_ADDR 0x20314000
6715+#define CFG_ATA_IDE0_OFFSET 0x0000
6716+#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
6717+#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
6718+#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
6719+#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
6720+
6721+#undef CONFIG_SCLK_DIV
6722+#define CONFIG_SCLK_DIV 8
6723+#endif /* CONFIG_BFIN_HDD_IDE */
6724+
6725+#endif /*CONFIG_BFIN_IDE */
6726+
6727+
6728+/*
6729+ * Misc Settings
6730+ */
6731+#define CONFIG_MISC_INIT_R
6732+//#define CONFIG_RTC_BFIN
6733+
6734+/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
6735+
6736+//#define ADI_CMDS_EXTRA (ADD_IDE_CMD | ADD_NAND_CMD)
6737+#define CONFIG_BFIN_COMMANDS \
6738+ ( CFG_BFIN_CMD_BOOTLDR | \
6739+ CFG_BFIN_CMD_CPLBINFO )
6740+
6741+/* Define if want to do post memory test */
6742+#undef CONFIG_POST
6743+#ifdef CONFIG_POST
6744+#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
6745+#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
6746+#endif
6747+
6748+
6749+/*
6750+ * Pull in common ADI header for remaining command/environment setup
6751+ */
6752+#include <configs/bfin_adi_common.h>
6753+
6754+#include <asm/blackfin-config-post.h>
6755+
6756+#include <asm/mem_init.h>
6757+
6758+
6759+/* Overrides common ADI header's command/environment setup */
6760+
6761+#ifdef CONFIG_BOOTDELAY
6762+#undef CONFIG_BOOTDELAY
6763+#endif
6764+#define CONFIG_BOOTDELAY 10
6765+
6766+#ifdef CONFIG_BOOTCOMMAND
6767+#undef CONFIG_BOOTCOMMAND
6768+#endif
6769+#define CONFIG_BOOTCOMMAND "run flashboot"
6770+
6771+#ifdef CONFIG_BOOTARGS
6772+#undef CONFIG_BOOTARGS
6773+#endif
6774+#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m lpj=496640"
6775+
6776+#ifdef CONFIG_EBIU_SDRRC_VAL
6777+#undef CONFIG_EBIU_SDRRC_VAL
6778+#endif
6779+#define CONFIG_EBIU_SDRRC_VAL mem_SDRRC
6780+
6781+#ifdef CONFIG_EBIU_SDGCTL_VAL
6782+#undef CONFIG_EBIU_SDGCTL_VAL
6783+#endif
6784+#define CONFIG_EBIU_SDGCTL_VAL mem_SDGCTL
6785+
6786+#ifdef CONFIG_EBIU_SDBCTL_VAL
6787+#undef CONFIG_EBIU_SDBCTL_VAL
6788+#endif
6789+#define CONFIG_EBIU_SDBCTL_VAL mem_SDBCTL
6790+
6791+#ifdef CONFIG_EBIU_AMBCTL0_VAL
6792+#undef CONFIG_EBIU_AMBCTL0_VAL
6793+#endif
6794+#define CONFIG_EBIU_AMBCTL0_VAL flash_EBIU_AMBCTL0
6795+
6796+#ifdef CFG_AUTOLOAD
6797+#undef CFG_AUTOLOAD
6798+#endif
6799+#define CFG_AUTOLOAD ""
6800+
6801+ /* CONFIG_SERIAL_BF537 no longer used*/
6802+//#define CONFIG_SERIAL_BF537 1
6803+
6804+#ifdef CONFIG_POST_TEST
6805+#undef CONFIG_POST_TEST
6806+#endif
6807+
6808+#define CONFIG_METROLOGIC_IO_INIT 1
6809+
6810+#define CONFIG_CORE_VOLTAGE_MILLIVOLT 1250
6811+#define CONFIG_DISABLE_CLKIN_OUTPUT 1
6812+
6813+//#define CONFIG_METROLOGIC_INTERFACE_DETECTION 1
6814+//#define CONFIG_SUPPORT_KBW 1
6815+//#define CONFIG_SUPPORT_IBM 1
6816+//#define CONFIG_SUPPORT_MULTIFUNC 1
6817+//#define CONFIG_SUPPORT_BLUETOOTH 1
6818+//#define CONFIG_RTS_DEFAULT_ASSERTED 1
6819+
6820+//#define KBCLOCK_PIN 25
6821+#define RTS_PIN 25
6822+//#define KBW_GATE_PIN 27
6823+#define IBM_RS4680_RESET_PIN 27
6824+#define FOCUS_KBWEN_PIN 24
6825+
6826+//#define BT_LDO_PIN 27
6827+//#define BT_RESET_PIN 26
6828+//#define BT_RDY_PIN 37
6829+//#define BT_CONN_PIN 35
6830+//#define BT_DSR_PIN 34
6831+//#define BT_SWITCH_PIN 2
6832+//#define TRIG_PIN 41
6833+//#define BLUE_LED_PIN 31
6834+//#define WHITE_LED_PIN 30
6835+//#define YELLOW_LED_PIN 29
6836+
6837+
6838+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
6839+//#define CFG_AUTOLOAD "no"
6840+
6841+
6842+/****************************************************************/
6843+
6844+#endif
6845diff --git a/u-boot-1.1.6/include/configs/Orbit3.h b/u-boot-1.1.6/include/configs/Orbit3.h
6846new file mode 100644
6847index 0000000..d7ea48a
6848--- /dev/null
6849+++ b/u-boot-1.1.6/include/configs/Orbit3.h
6850@@ -0,0 +1,378 @@
6851+/*
6852+ * U-boot - Configuration file for BF537 STAMP board
6853+ */
6854+
6855+#ifndef __CONFIG_ORBIT3_H__
6856+#define __CONFIG_ORBIT3_H__
6857+
6858+#include <asm/blackfin-config-pre.h>
6859+
6860+
6861+#ifndef __ADSPBF534__
6862+#define __ADSPBF534__
6863+#endif
6864+#define METROLOGIC_PLATFORM "Genesis"
6865+#define SUPPORT_NETWORKING 0
6866+#define CONFIG_SILENT_CONSOLE 1
6867+#define CONFIG_BAUDRATE 115200
6868+#define CONFIG_LOADADDR 0x800000
6869+
6870+#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
6871+ "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
6872+
6873+#define CFG_PROMPT "bootldr> "
6874+#define CONFIG_ZERO_BOOTDELAY_CHECK
6875+#define CONFIG_AUTOBOOT_KEYED 1
6876+#define CONFIG_AUTOBOOT_STOP_STR "\033"
6877+#define CONFIG_MEM_MT48LC16M16A2TG_75 1
6878+//#define CONFIG_MEM_IS42S16160B_7 1
6879+
6880+//#define CONFIG_DEBUG_EARLY_SERIAL 1
6881+//#define DEBUG_BOOTKEYS 1
6882+//#define DEBUG 1
6883+//#define DEBUG_METRO_IO 1
6884+//#define DEBUG_I2C 1
6885+
6886+// We don't have a parallel flash chip there
6887+#define CFG_NO_FLASH
6888+
6889+
6890+ /*
6891+ * Processor Settings
6892+ */
6893+#define CONFIG_BFIN_CPU bf534-0.2
6894+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
6895+
6896+
6897+/*
6898+ * Clock Settings
6899+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
6900+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
6901+ */
6902+/* CONFIG_CLKIN_HZ is any value in Hz */
6903+#define CONFIG_CLKIN_HZ 25000000
6904+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
6905+/* 1 = CLKIN / 2 */
6906+#define CONFIG_CLKIN_HALF 0
6907+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
6908+/* 1 = bypass PLL */
6909+#define CONFIG_PLL_BYPASS 0
6910+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
6911+/* Values can range from 0-63 (where 0 means 64) */
6912+#define CONFIG_VCO_MULT 20
6913+/* CCLK_DIV controls the core clock divider */
6914+/* Values can be 1, 2, 4, or 8 ONLY */
6915+#define CONFIG_CCLK_DIV 1
6916+/* SCLK_DIV controls the system clock divider */
6917+/* Values can range from 1-15 */
6918+#define CONFIG_SCLK_DIV 4
6919+
6920+
6921+/*
6922+ * Memory Settings
6923+ */
6924+#define CONFIG_MEM_ADD_WDTH 9
6925+#define CONFIG_MEM_SIZE 32
6926+
6927+//#define CONFIG_EBIU_SDRRC_VAL 0x306
6928+//#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
6929+//#define CONFIG_EBIU_SDBCTL_VAL (EBSZ_64 | EBCAW_10 | EBE)
6930+
6931+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
6932+//#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
6933+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
6934+
6935+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for monitor */
6936+#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 384 kB for malloc() (video/spi are big) */
6937+#define CFG_GBL_DATA_SIZE 0x4000
6938+
6939+
6940+/*
6941+ * Network Settings
6942+ */
6943+#if SUPPORT_NETWORKING
6944+#ifndef __ADSPBF534__
6945+#define ADI_CMDS_NETWORK 1
6946+#define CONFIG_BFIN_MAC
6947+#define CONFIG_NETCONSOLE 1
6948+#define CONFIG_NET_MULTI 1
6949+#else
6950+#define ADI_CMDS_NETWORK 0
6951+#endif
6952+#endif
6953+//#define CONFIG_HOSTNAME bf537-stamp
6954+/* Uncomment next line to use fixed MAC address */
6955+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
6956+
6957+
6958+/*
6959+ * Flash Settings
6960+ */
6961+#define CFG_FLASH_BASE 0x20000000
6962+#define CFG_FLASH_CFI /* The flash is CFI compatible */
6963+//#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
6964+//#define CFG_FLASH_PROTECTION
6965+#define CFG_MAX_FLASH_BANKS 1
6966+#define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
6967+#define FLASH_SIZE 0x800000
6968+#define CFG_FLASH_SIZE 0x800000
6969+
6970+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
6971+#define CFG_ENV_IS_IN_EEPROM 1
6972+#define CFG_ENV_OFFSET 0x4000
6973+#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
6974+#else
6975+#define CFG_ENV_IS_IN_FLASH 1
6976+#define CFG_ENV_ADDR 0x20004000
6977+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
6978+#endif
6979+#define CFG_ENV_SIZE 0x2000
6980+#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
6981+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
6982+#define ENV_IS_EMBEDDED
6983+#else
6984+#define ENV_IS_EMBEDDED_CUSTOM
6985+#endif
6986+
6987+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
6988+/* Values can range from 2-65535 */
6989+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
6990+#define CONFIG_SPI
6991+#define CONFIG_SPI_BAUD 2
6992+#define CONFIG_SPI_BAUD_INITBLOCK 3
6993+
6994+
6995+/*
6996+ * I2C Settings
6997+ */
6998+#define CONFIG_HARD_I2C 1 /* I2C TWI */
6999+#define CFG_I2C_SPEED 50000
7000+#define CFG_I2C_SLAVE 0
7001+
7002+
7003+/*
7004+ * NAND Settings
7005+ */
7006+/* #define CONFIG_BF537_NAND */
7007+#ifdef CONFIG_BF537_NAND
7008+# define ADD_NAND_CMD CFG_CMD_NAND
7009+#else
7010+# define ADD_NAND_CMD 0
7011+#endif
7012+
7013+#define CFG_NAND_ADDR 0x20212000
7014+#define CFG_NAND_BASE CFG_NAND_ADDR
7015+#define CFG_MAX_NAND_DEVICE 1
7016+#define SECTORSIZE 512
7017+#define ADDR_COLUMN 1
7018+#define ADDR_PAGE 2
7019+#define ADDR_COLUMN_PAGE 3
7020+#define NAND_ChipID_UNKNOWN 0x00
7021+#define NAND_MAX_FLOORS 1
7022+#define NAND_MAX_CHIPS 1
7023+#define BFIN_NAND_READY PF3
7024+
7025+#define NAND_WAIT_READY(nand) \
7026+ do { \
7027+ int timeout = 0; \
7028+ while(!(*pPORTFIO & PF3)) \
7029+ if (timeout++ > 100000) \
7030+ break; \
7031+ } while (0)
7032+
7033+#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
7034+#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
7035+
7036+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
7037+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
7038+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
7039+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
7040+
7041+
7042+/*
7043+ * CF-CARD IDE-HDD Support
7044+ */
7045+/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
7046+/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
7047+/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
7048+
7049+#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
7050+# define CONFIG_BFIN_IDE 1
7051+# define ADD_IDE_CMD CFG_CMD_IDE
7052+#else
7053+# define ADD_IDE_CMD 0
7054+#endif
7055+
7056+#if defined(CONFIG_BFIN_IDE)
7057+
7058+#define CONFIG_DOS_PARTITION 1
7059+/*
7060+ * IDE/ATA stuff
7061+ */
7062+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
7063+#undef CONFIG_IDE_LED /* no led for ide supported */
7064+#undef CONFIG_IDE_RESET /* no reset for ide supported */
7065+
7066+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
7067+#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
7068+
7069+#undef CONFIG_EBIU_AMBCTL1_VAL
7070+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
7071+
7072+#define CONFIG_CF_ATASEL_DIS 0x20311800
7073+#define CONFIG_CF_ATASEL_ENA 0x20311802
7074+
7075+#if defined(CONFIG_BFIN_TRUE_IDE)
7076+/*
7077+ * Note that these settings aren't for the most part used in include/ata.h
7078+ * when all of the ATA registers are setup
7079+ */
7080+#define CFG_ATA_BASE_ADDR 0x2031C000
7081+#define CFG_ATA_IDE0_OFFSET 0x0000
7082+#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
7083+#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
7084+#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
7085+#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
7086+#endif /* CONFIG_BFIN_TRUE_IDE */
7087+
7088+#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
7089+#define CFG_ATA_BASE_ADDR 0x20211800
7090+#define CFG_ATA_IDE0_OFFSET 0x0000
7091+#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
7092+#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
7093+#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
7094+#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
7095+#endif /* CONFIG_BFIN_CF_IDE */
7096+
7097+#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
7098+#define CFG_ATA_BASE_ADDR 0x20314000
7099+#define CFG_ATA_IDE0_OFFSET 0x0000
7100+#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
7101+#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
7102+#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
7103+#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
7104+
7105+#undef CONFIG_SCLK_DIV
7106+#define CONFIG_SCLK_DIV 8
7107+#endif /* CONFIG_BFIN_HDD_IDE */
7108+
7109+#endif /*CONFIG_BFIN_IDE */
7110+
7111+
7112+/*
7113+ * Misc Settings
7114+ */
7115+#define CONFIG_MISC_INIT_R
7116+//#define CONFIG_RTC_BFIN
7117+
7118+/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
7119+
7120+//#define ADI_CMDS_EXTRA (ADD_IDE_CMD | ADD_NAND_CMD)
7121+#define CONFIG_BFIN_COMMANDS \
7122+ ( CFG_BFIN_CMD_BOOTLDR | \
7123+ CFG_BFIN_CMD_CPLBINFO )
7124+
7125+/* Define if want to do post memory test */
7126+#undef CONFIG_POST
7127+#ifdef CONFIG_POST
7128+#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
7129+#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
7130+#endif
7131+
7132+
7133+/*
7134+ * Pull in common ADI header for remaining command/environment setup
7135+ */
7136+#include <configs/bfin_adi_common.h>
7137+
7138+#include <asm/blackfin-config-post.h>
7139+
7140+#include <asm/mem_init.h>
7141+
7142+
7143+/* Overrides common ADI header's command/environment setup */
7144+
7145+#ifdef CONFIG_BOOTDELAY
7146+#undef CONFIG_BOOTDELAY
7147+#endif
7148+#define CONFIG_BOOTDELAY 10
7149+
7150+#ifdef CONFIG_BOOTCOMMAND
7151+#undef CONFIG_BOOTCOMMAND
7152+#endif
7153+#define CONFIG_BOOTCOMMAND "run flashboot"
7154+
7155+#ifdef CONFIG_BOOTARGS
7156+#undef CONFIG_BOOTARGS
7157+#endif
7158+#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m lpj=496640"
7159+
7160+#ifdef CONFIG_EBIU_SDRRC_VAL
7161+#undef CONFIG_EBIU_SDRRC_VAL
7162+#endif
7163+#define CONFIG_EBIU_SDRRC_VAL mem_SDRRC
7164+
7165+#ifdef CONFIG_EBIU_SDGCTL_VAL
7166+#undef CONFIG_EBIU_SDGCTL_VAL
7167+#endif
7168+#define CONFIG_EBIU_SDGCTL_VAL mem_SDGCTL
7169+
7170+#ifdef CONFIG_EBIU_SDBCTL_VAL
7171+#undef CONFIG_EBIU_SDBCTL_VAL
7172+#endif
7173+#define CONFIG_EBIU_SDBCTL_VAL mem_SDBCTL
7174+
7175+#ifdef CONFIG_EBIU_AMBCTL0_VAL
7176+#undef CONFIG_EBIU_AMBCTL0_VAL
7177+#endif
7178+#define CONFIG_EBIU_AMBCTL0_VAL flash_EBIU_AMBCTL0
7179+
7180+#ifdef CFG_AUTOLOAD
7181+#undef CFG_AUTOLOAD
7182+#endif
7183+#define CFG_AUTOLOAD ""
7184+
7185+ /* CONFIG_SERIAL_BF537 no longer used*/
7186+//#define CONFIG_SERIAL_BF537 1
7187+
7188+#ifdef CONFIG_POST_TEST
7189+#undef CONFIG_POST_TEST
7190+#endif
7191+
7192+#define CONFIG_METROLOGIC_IO_INIT 1
7193+
7194+#define CONFIG_CORE_VOLTAGE_MILLIVOLT 1250
7195+#define CONFIG_DISABLE_CLKIN_OUTPUT 1
7196+
7197+//#define CONFIG_METROLOGIC_INTERFACE_DETECTION 1
7198+//#define CONFIG_SUPPORT_KBW 1
7199+//#define CONFIG_SUPPORT_IBM 1
7200+//#define CONFIG_SUPPORT_MULTIFUNC 1
7201+//#define CONFIG_SUPPORT_BLUETOOTH 1
7202+//#define CONFIG_RTS_DEFAULT_ASSERTED 1
7203+
7204+//#define KBCLOCK_PIN 25
7205+#define RTS_PIN 25
7206+//#define KBW_GATE_PIN 27
7207+#define IBM_RS4680_RESET_PIN 27
7208+#define FOCUS_KBWEN_PIN 24
7209+
7210+//#define BT_LDO_PIN 27
7211+//#define BT_RESET_PIN 26
7212+//#define BT_RDY_PIN 37
7213+//#define BT_CONN_PIN 35
7214+//#define BT_DSR_PIN 34
7215+//#define BT_SWITCH_PIN 2
7216+//#define TRIG_PIN 41
7217+//#define BLUE_LED_PIN 31
7218+//#define WHITE_LED_PIN 30
7219+//#define YELLOW_LED_PIN 29
7220+
7221+
7222+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
7223+//#define CFG_AUTOLOAD "no"
7224+
7225+
7226+/****************************************************************/
7227+
7228+#endif
7229diff --git a/u-boot-1.1.6/include/configs/VuQuest2D.h b/u-boot-1.1.6/include/configs/VuQuest2D.h
7230new file mode 100644
7231index 0000000..2d9995f
7232--- /dev/null
7233+++ b/u-boot-1.1.6/include/configs/VuQuest2D.h
7234@@ -0,0 +1,309 @@
7235+/*
7236+ * U-boot - Configuration file for BF533 STAMP board
7237+ */
7238+
7239+#ifndef __CONFIG_VUQUEST2D_H__
7240+#define __CONFIG_VUQUEST2D_H__
7241+
7242+#include <asm/blackfin-config-pre.h>
7243+
7244+
7245+#ifndef __ADSPBF531__
7246+#define __ADSPBF531__
7247+#endif
7248+#define METROLOGIC_PLATFORM "VuQuest2D"
7249+#define SUPPORT_NETWORKING 0
7250+#define CONFIG_SILENT_CONSOLE 1
7251+#define CONFIG_BAUDRATE 115200
7252+#define CONFIG_LOADADDR 0x800000
7253+
7254+//#define METROLOGIC_FLASH_BOOT_ENV_PARAM "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
7255+
7256+#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
7257+ "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
7258+
7259+#define CFG_PROMPT "bootldr> "
7260+#define CONFIG_ZERO_BOOTDELAY_CHECK
7261+#define CONFIG_AUTOBOOT_KEYED 1
7262+#define CONFIG_AUTOBOOT_STOP_STR "\033"
7263+#define CONFIG_MEM_MT48LC16M16A2TG_75 1
7264+//#define CONFIG_MEM_IS42S16160B_7 1
7265+
7266+//#define CONFIG_DEBUG_EARLY_SERIAL 1
7267+//#define DEBUG_BOOTKEYS 1
7268+//#define DEBUG 1
7269+
7270+// We don't have a parallel flash chip there
7271+#define CFG_NO_FLASH
7272+
7273+
7274+/*
7275+ * Processor Settings
7276+ */
7277+#define CONFIG_BFIN_CPU bf531-0.3
7278+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
7279+
7280+
7281+/*
7282+ * Clock Settings
7283+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
7284+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
7285+ */
7286+/* CONFIG_CLKIN_HZ is any value in Hz */
7287+#define CONFIG_CLKIN_HZ 25000000
7288+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
7289+/* 1 = CLKIN / 2 */
7290+#define CONFIG_CLKIN_HALF 0
7291+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
7292+/* 1 = bypass PLL */
7293+#define CONFIG_PLL_BYPASS 0
7294+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
7295+/* Values can range from 0-63 (where 0 means 64) */
7296+#define CONFIG_VCO_MULT 15
7297+/* CCLK_DIV controls the core clock divider */
7298+/* Values can be 1, 2, 4, or 8 ONLY */
7299+#define CONFIG_CCLK_DIV 1
7300+/* SCLK_DIV controls the system clock divider */
7301+/* Values can range from 1-15 */
7302+#define CONFIG_SCLK_DIV 3
7303+
7304+
7305+/*
7306+ * Memory Settings
7307+ */
7308+#define CONFIG_MEM_ADD_WDTH 9
7309+#define CONFIG_MEM_SIZE 32
7310+
7311+#define CONFIG_EBIU_SDRRC_VAL 0x268
7312+#define CONFIG_EBIU_SDGCTL_VAL 0x911109
7313+#define CONFIG_EBIU_SDBCTL_VAL (EBSZ_128 | EBCAW_11 | EBE)
7314+
7315+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
7316+#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
7317+#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
7318+
7319+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for monitor */
7320+#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 384 kB for malloc() (video/spi are big) */
7321+#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */
7322+
7323+
7324+/*
7325+ * Network Settings
7326+
7327+ */
7328+#if SUPPORT_NETWORKING
7329+
7330+#define ADI_CMDS_NETWORK 0
7331+#define CONFIG_DRIVER_SMC91111 0
7332+#define CONFIG_SMC91111_BASE 0x20300300
7333+#define SMC91111_EEPROM_INIT() { *pFIO_DIR = 0x01; *pFIO_FLAG_S = 0x01; SSYNC(); }
7334+
7335+#endif /* SUPPORT_NETWORKING */
7336+
7337+#define CONFIG_HOSTNAME bf533-stamp
7338+/* To remove hardcoding and enable MAC storage in EEPROM */
7339+/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
7340+
7341+
7342+/*
7343+ * Flash Settings
7344+ */
7345+#define CFG_FLASH_CFI /* The flash is CFI compatible */
7346+//#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
7347+#define CFG_FLASH_CFI_AMD_RESET
7348+
7349+#define CFG_FLASH_BASE 0x20000000
7350+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
7351+#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
7352+#define FLASH_SIZE 0x800000
7353+#define CFG_FLASH_SIZE 0x800000
7354+
7355+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
7356+#define CFG_ENV_IS_IN_EEPROM 1
7357+#define CFG_ENV_OFFSET 0x4000
7358+#else
7359+#define CFG_ENV_IS_IN_FLASH 1
7360+#define CFG_ENV_ADDR 0x20004000
7361+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
7362+#endif
7363+#define CFG_ENV_SIZE 0x2000
7364+#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
7365+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
7366+#define ENV_IS_EMBEDDED
7367+#else
7368+#define ENV_IS_EMBEDDED_CUSTOM
7369+#endif
7370+
7371+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
7372+/* Values can range from 2-65535 */
7373+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
7374+#define CONFIG_SPI
7375+#define CONFIG_SPI_BAUD 2
7376+#define CONFIG_SPI_BAUD_INITBLOCK 3
7377+#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
7378+
7379+
7380+/*
7381+ * I2C Settings
7382+ * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
7383+ */
7384+#define CONFIG_SOFT_I2C
7385+#define PF_SCL PF0
7386+#define PF_SDA PF1
7387+#ifdef CONFIG_SOFT_I2C
7388+#define I2C_INIT do { *pFIO_DIR |= PF_SCL; SSYNC(); } while (0)
7389+#define I2C_ACTIVE do { *pFIO_DIR |= PF_SDA; *pFIO_INEN &= ~PF_SDA; SSYNC(); } while (0)
7390+#define I2C_TRISTATE do { *pFIO_DIR &= ~PF_SDA; *pFIO_INEN |= PF_SDA; SSYNC(); } while (0)
7391+#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0)
7392+#define I2C_SDA(bit) \
7393+ do { \
7394+ if (bit) \
7395+ *pFIO_FLAG_S = PF_SDA; \
7396+ else \
7397+ *pFIO_FLAG_C = PF_SDA; \
7398+ SSYNC(); \
7399+ } while (0)
7400+#define I2C_SCL(bit) \
7401+ do { \
7402+ if (bit) \
7403+ *pFIO_FLAG_S = PF_SCL; \
7404+ else \
7405+ *pFIO_FLAG_C = PF_SCL; \
7406+ SSYNC(); \
7407+ } while (0)
7408+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
7409+
7410+#define CFG_I2C_SPEED 50000
7411+#define CFG_I2C_SLAVE 0
7412+#endif
7413+
7414+
7415+/*
7416+ * Compact Flash / IDE / ATA Settings
7417+ */
7418+
7419+/* Enabled below option for CF support */
7420+/* #define CONFIG_STAMP_CF */
7421+#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
7422+#define CONFIG_MISC_INIT_R
7423+#define CONFIG_DOS_PARTITION 1
7424+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
7425+#undef CONFIG_IDE_LED /* no led for ide supported */
7426+#undef CONFIG_IDE_RESET /* no reset for ide supported */
7427+
7428+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
7429+#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
7430+
7431+#define CFG_ATA_BASE_ADDR 0x20200000
7432+#define CFG_ATA_IDE0_OFFSET 0x0000
7433+
7434+#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
7435+#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
7436+#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
7437+
7438+#define CFG_ATA_STRIDE 2
7439+
7440+#undef CONFIG_EBIU_AMBCTL1_VAL
7441+#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
7442+#endif
7443+
7444+
7445+/*
7446+ * Misc Settings
7447+ */
7448+// #define CONFIG_RTC_BFIN
7449+
7450+#define CONFIG_BFIN_COMMANDS \
7451+ ( CFG_BFIN_CMD_CPLBINFO )
7452+
7453+/* FLASH/ETHERNET uses the same async bank */
7454+#define SHARED_RESOURCES 1
7455+
7456+#ifdef CONFIG_POST_TEST
7457+#undef CONFIG_POST_TEST
7458+#endif
7459+
7460+/* define to enable splash screen support */
7461+/* #define CONFIG_VIDEO */
7462+
7463+/*
7464+ * Pull in common ADI header for remaining command/environment setup
7465+ */
7466+#include <configs/bfin_adi_common.h>
7467+
7468+#include <asm/blackfin-config-post.h>
7469+
7470+#include <asm/mem_init.h>
7471+
7472+
7473+/* Overrides common ADI header's command/environment setup */
7474+
7475+#ifdef CONFIG_BOOTDELAY
7476+#undef CONFIG_BOOTDELAY
7477+#endif
7478+#define CONFIG_BOOTDELAY 0
7479+
7480+#ifdef CONFIG_BOOTCOMMAND
7481+#undef CONFIG_BOOTCOMMAND
7482+#endif
7483+#define CONFIG_BOOTCOMMAND "run flashboot"
7484+
7485+#ifdef CONFIG_BOOTARGS
7486+#undef CONFIG_BOOTARGS
7487+#endif
7488+#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m lpj=396288"
7489+
7490+#ifdef CONFIG_EBIU_SDRRC_VAL
7491+#undef CONFIG_EBIU_SDRRC_VAL
7492+#endif
7493+#define CONFIG_EBIU_SDRRC_VAL mem_SDRRC
7494+
7495+#ifdef CONFIG_EBIU_SDGCTL_VAL
7496+#undef CONFIG_EBIU_SDGCTL_VAL
7497+#endif
7498+#define CONFIG_EBIU_SDGCTL_VAL mem_SDGCTL
7499+
7500+#ifdef CONFIG_EBIU_SDBCTL_VAL
7501+#undef CONFIG_EBIU_SDBCTL_VAL
7502+#endif
7503+#define CONFIG_EBIU_SDBCTL_VAL mem_SDBCTL
7504+
7505+#ifdef CONFIG_EBIU_AMBCTL0_VAL
7506+#undef CONFIG_EBIU_AMBCTL0_VAL
7507+#endif
7508+#define CONFIG_EBIU_AMBCTL0_VAL flash_EBIU_AMBCTL0
7509+
7510+#ifdef CFG_AUTOLOAD
7511+#undef CFG_AUTOLOAD
7512+#endif
7513+#define CFG_AUTOLOAD ""
7514+
7515+ /* CONFIG_SERIAL_BF537 no longer used*/
7516+//#define CONFIG_SERIAL_BF537 1
7517+
7518+#define CONFIG_METROLOGIC_IO_INIT 1
7519+
7520+#define CONFIG_CORE_VOLTAGE_MILLIVOLT 1250
7521+#define CONFIG_DISABLE_CLKIN_OUTPUT 1
7522+
7523+#define CONFIG_METROLOGIC_INTERFACE_DETECTION 1
7524+#define CONFIG_METROLOGIC_VQ2D_REV 2
7525+//#define CONFIG_SUPPORT_KBW 1
7526+//#define CONFIG_SUPPORT_IBM 1
7527+//#define CONFIG_SUPPORT_MULTIFUNC 1
7528+//#define CONFIG_SUPPORT_BLUETOOTH 1
7529+//#define CONFIG_RTS_DEFAULT_ASSERTED 1
7530+
7531+//#define KBCLOCK_PIN 25
7532+#define RTS_PIN 6
7533+//#define KBW_GATE_PIN 27
7534+//#define IBM_RS4680_RESET_PIN 27
7535+//#define FOCUS_KBWEN_PIN 24
7536+
7537+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
7538+//#define CFG_AUTOLOAD "no"
7539+
7540+
7541+/****************************************************************/
7542+
7543+#endif
7544diff --git a/u-boot-1.1.6/include/configs/bf533-stamp.h b/u-boot-1.1.6/include/configs/bf533-stamp.h
7545index 2e6a51e..6b68418 100644
7546--- a/u-boot-1.1.6/include/configs/bf533-stamp.h
7547+++ b/u-boot-1.1.6/include/configs/bf533-stamp.h
7548@@ -8,6 +8,21 @@
7549 #include <asm/blackfin-config-pre.h>
7550
7551
7552+#ifndef __ADSPBF533__
7553+#define __ADSPBF533__
7554+#endif
7555+#define METROLOGIC_PLATFORM "ADI Eval Board"
7556+#define SUPPORT_NETWORKING 0
7557+#define CONFIG_SILENT_CONSOLE 1
7558+#define CONFIG_BAUDRATE 115200
7559+#define CONFIG_LOADADDR 0x800000
7560+#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
7561+ "flashboot=bootm 0x20060000\0"
7562+#define CFG_PROMPT "bootldr> "
7563+#define CONFIG_ZERO_BOOTDELAY_CHECK
7564+#define CONFIG_AUTOBOOT_KEYED 1
7565+#define CONFIG_AUTOBOOT_STOP_STR "\033"
7566+
7567 /*
7568 * Processor Settings
7569 */
7570@@ -36,8 +51,7 @@
7571 #define CONFIG_CCLK_DIV 1
7572 /* SCLK_DIV controls the system clock divider */
7573 /* Values can range from 1-15 */
7574-#define CONFIG_SCLK_DIV 5
7575-
7576+#define CONFIG_SCLK_DIV 4
7577
7578 /*
7579 * Memory Settings
7580@@ -61,10 +75,13 @@
7581 /*
7582 * Network Settings
7583 */
7584+#if SUPPORT_NETWORKING
7585 #define ADI_CMDS_NETWORK 1
7586 #define CONFIG_DRIVER_SMC91111 1
7587 #define CONFIG_SMC91111_BASE 0x20300300
7588 #define SMC91111_EEPROM_INIT() { *pFIO_DIR = 0x01; *pFIO_FLAG_S = 0x01; SSYNC(); }
7589+#endif /* SUPPORT_NETWORKING */
7590+
7591 #define CONFIG_HOSTNAME bf533-stamp
7592 /* To remove hardcoding and enable MAC storage in EEPROM */
7593 /* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
7594@@ -80,6 +97,8 @@
7595 #define CFG_FLASH_BASE 0x20000000
7596 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
7597 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
7598+#define FLASH_SIZE 0x800000
7599+#define CFG_FLASH_SIZE 0x800000
7600
7601 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
7602 #define CFG_ENV_IS_IN_EEPROM 1
7603@@ -173,7 +192,7 @@
7604 /*
7605 * Misc Settings
7606 */
7607-#define CONFIG_RTC_BFIN
7608+//#define CONFIG_RTC_BFIN
7609
7610 #define CONFIG_BFIN_COMMANDS \
7611 ( CFG_BFIN_CMD_CPLBINFO )
7612@@ -184,8 +203,6 @@
7613 /* define to enable splash screen support */
7614 /* #define CONFIG_VIDEO */
7615
7616-
7617-
7618 /*
7619 * Pull in common ADI header for remaining command/environment setup
7620 */
7621@@ -193,4 +210,24 @@
7622
7623 #include <asm/blackfin-config-post.h>
7624
7625+#include <asm/mem_init.h>
7626+
7627+
7628+/* Overrides common ADI header's command/environment setup */
7629+
7630+#ifdef CONFIG_BOOTDELAY
7631+#undef CONFIG_BOOTDELAY
7632+#endif
7633+#define CONFIG_BOOTDELAY 1
7634+
7635+#ifdef CONFIG_BOOTCOMMAND
7636+#undef CONFIG_BOOTCOMMAND
7637+#endif
7638+#define CONFIG_BOOTCOMMAND "run flashboot"
7639+
7640+#ifdef CONFIG_BOOTARGS
7641+#undef CONFIG_BOOTARGS
7642+#endif
7643+#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m"
7644+
7645 #endif
7646diff --git a/u-boot-1.1.6/include/configs/bf537-srv1.h b/u-boot-1.1.6/include/configs/bf537-srv1.h
7647index f7d5bba..83c78c8 100644
7648--- a/u-boot-1.1.6/include/configs/bf537-srv1.h
7649+++ b/u-boot-1.1.6/include/configs/bf537-srv1.h
7650@@ -155,28 +155,37 @@
7651 #endif
7652
7653 #ifdef CONFIG_BFIN_MAC
7654-# define CONFIG_BFIN_CMD (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_DHCP)
7655+# define CONFIG_BFIN_CMD (CONFIG_CMD_DFL | CFG_CMD_PING)
7656 #else
7657 # define CONFIG_BFIN_CMD (CONFIG_CMD_DFL & ~CFG_CMD_NET)
7658 #endif
7659
7660-#ifdef CFG_NO_FLASH
7661-# define CONFIG_BFIN_CMD2 (CONFIG_BFIN_CMD & ~(CFG_CMD_IMLS | CFG_CMD_FLASH))
7662-#else
7663-# define CONFIG_BFIN_CMD2 (CONFIG_BFIN_CMD | CFG_CMD_JFFS2)
7664+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) || (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
7665+#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \
7666+ CFG_CMD_ELF | \
7667+ CFG_CMD_I2C | \
7668+ CFG_CMD_CACHE | \
7669+ CFG_CMD_JFFS2 | \
7670+ CFG_CMD_EEPROM | \
7671+ CFG_CMD_DHCP | \
7672+ ADD_IDE_CMD | \
7673+ ADD_NAND_CMD | \
7674+ CFG_CMD_POST_DIAG | \
7675+ CFG_CMD_DATE)
7676+#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
7677+#define CONFIG_COMMANDS (( CONFIG_BFIN_CMD| \
7678+ CFG_CMD_ELF | \
7679+ CFG_CMD_I2C | \
7680+ CFG_CMD_CACHE | \
7681+ /* CFG_CMD_JFFS2 | */ \
7682+ CFG_CMD_EEPROM | \
7683+ /* ADD_IDE_CMD | */ \
7684+ CFG_CMD_DATE ) \
7685+ & \
7686+ /* no image ls */ ~(CFG_CMD_IMLS | CFG_CMD_FLASH) \
7687+ )
7688 #endif
7689
7690-#define CONFIG_COMMANDS \
7691- (CONFIG_BFIN_CMD2 | \
7692- CFG_CMD_ELF | \
7693- CFG_CMD_I2C | \
7694- CFG_CMD_CACHE | \
7695- CFG_CMD_EEPROM | \
7696- ADD_IDE_CMD | \
7697- ADD_NAND_CMD | \
7698- CFG_CMD_POST_DIAG | \
7699- CFG_CMD_DATE)
7700-
7701 #define CONFIG_BFIN_COMMANDS \
7702 ( CFG_BFIN_CMD_BOOTLDR | \
7703 CFG_BFIN_CMD_CPLBINFO )
7704@@ -189,7 +198,7 @@
7705 "update=tftpboot $(loadaddr) u-boot.bin;" \
7706 "protect off 0x20000000 0x2003FFFF;" \
7707 "erase 0x20000000 0x2003FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0"
7708-#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) || (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
7709+#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
7710 # define BOOT_ENV_SETTINGS \
7711 "update=tftpboot $(loadaddr) u-boot.ldr;" \
7712 "eeprom write $(loadaddr) 0x0 $(filesize);\0" \
7713@@ -243,18 +252,19 @@
7714
7715 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
7716 #define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
7717-#define CFG_MALLOC_LEN (384 << 10) /* Reserve 128 kB for malloc() */
7718+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
7719 #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
7720 #define CFG_GBL_DATA_SIZE 0x4000
7721 #define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
7722 #define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
7723
7724
7725-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
7726+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) || (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
7727+/* for bf537-stamp, UART boot mode still store env in flash */
7728 #define CFG_ENV_IS_IN_FLASH 1
7729 #define CFG_ENV_ADDR 0x20004000
7730 #define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
7731-#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) || (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
7732+#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
7733 #define CFG_ENV_IS_IN_EEPROM 1
7734 #define CFG_ENV_OFFSET 0x10000
7735 #define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
7736diff --git a/u-boot-1.1.6/include/configs/bf537-stamp.h b/u-boot-1.1.6/include/configs/bf537-stamp.h
7737index aa4925f..f98c145 100644
7738--- a/u-boot-1.1.6/include/configs/bf537-stamp.h
7739+++ b/u-boot-1.1.6/include/configs/bf537-stamp.h
7740@@ -8,7 +8,22 @@
7741 #include <asm/blackfin-config-pre.h>
7742
7743
7744-/*
7745+#ifndef __ADSPBF537__
7746+#define __ADSPBF537__
7747+#endif
7748+#define METROLOGIC_PLATFORM "ADI Eval Board"
7749+#define SUPPORT_NETWORKING 1
7750+#define CONFIG_SILENT_CONSOLE 1
7751+#define CONFIG_BAUDRATE 115200
7752+#define CONFIG_LOADADDR 0x800000
7753+#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
7754+ "flashboot=bootm 0x20060000\0"
7755+#define CFG_PROMPT "bootldr> "
7756+#define CONFIG_ZERO_BOOTDELAY_CHECK
7757+#define CONFIG_AUTOBOOT_KEYED 1
7758+#define CONFIG_AUTOBOOT_STOP_STR "\033"
7759+
7760+ /*
7761 * Processor Settings
7762 */
7763 #define CONFIG_BFIN_CPU bf537-0.2
7764@@ -36,7 +51,7 @@
7765 #define CONFIG_CCLK_DIV 1
7766 /* SCLK_DIV controls the system clock divider */
7767 /* Values can range from 1-15 */
7768-#define CONFIG_SCLK_DIV 5
7769+#define CONFIG_SCLK_DIV 4
7770
7771
7772 /*
7773@@ -61,11 +76,15 @@
7774 /*
7775 * Network Settings
7776 */
7777+#if SUPPORT_NETWORKING
7778 #ifndef __ADSPBF534__
7779 #define ADI_CMDS_NETWORK 1
7780 #define CONFIG_BFIN_MAC
7781 #define CONFIG_NETCONSOLE 1
7782 #define CONFIG_NET_MULTI 1
7783+#else
7784+#define ADI_CMDS_NETWORK 0
7785+#endif
7786 #endif
7787 #define CONFIG_HOSTNAME bf537-stamp
7788 /* Uncomment next line to use fixed MAC address */
7789@@ -78,9 +97,11 @@
7790 #define CFG_FLASH_BASE 0x20000000
7791 #define CFG_FLASH_CFI /* The flash is CFI compatible */
7792 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
7793-#define CFG_FLASH_PROTECTION
7794+//#define CFG_FLASH_PROTECTION
7795 #define CFG_MAX_FLASH_BANKS 1
7796 #define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
7797+#define FLASH_SIZE 0x800000
7798+#define CFG_FLASH_SIZE 0x800000
7799
7800 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
7801 #define CFG_ENV_IS_IN_EEPROM 1
7802@@ -228,11 +249,11 @@
7803 * Misc Settings
7804 */
7805 #define CONFIG_MISC_INIT_R
7806-#define CONFIG_RTC_BFIN
7807+//#define CONFIG_RTC_BFIN
7808
7809 /* #define CONFIG_BF537_STAMP_LEDCMD 1 */
7810
7811-#define ADI_CMDS_EXTRA (ADD_IDE_CMD | ADD_NAND_CMD)
7812+//#define ADI_CMDS_EXTRA (ADD_IDE_CMD | ADD_NAND_CMD)
7813 #define CONFIG_BFIN_COMMANDS \
7814 ( CFG_BFIN_CMD_BOOTLDR | \
7815 CFG_BFIN_CMD_CPLBINFO )
7816@@ -244,7 +265,6 @@
7817 #define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
7818 #endif
7819
7820-
7821 /*
7822 * Pull in common ADI header for remaining command/environment setup
7823 */
7824@@ -252,4 +272,24 @@
7825
7826 #include <asm/blackfin-config-post.h>
7827
7828+#include <asm/mem_init.h>
7829+
7830+
7831+/* Overrides common ADI header's command/environment setup */
7832+
7833+#ifdef CONFIG_BOOTDELAY
7834+#undef CONFIG_BOOTDELAY
7835+#endif
7836+#define CONFIG_BOOTDELAY 1
7837+
7838+#ifdef CONFIG_BOOTCOMMAND
7839+#undef CONFIG_BOOTCOMMAND
7840+#endif
7841+#define CONFIG_BOOTCOMMAND "run flashboot"
7842+
7843+#ifdef CONFIG_BOOTARGS
7844+#undef CONFIG_BOOTARGS
7845+#endif
7846+#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m"
7847+
7848 #endif
7849diff --git a/u-boot-1.1.6/include/configs/bfin_adi_common.h b/u-boot-1.1.6/include/configs/bfin_adi_common.h
7850index 1b4b851..faddc0e 100644
7851--- a/u-boot-1.1.6/include/configs/bfin_adi_common.h
7852+++ b/u-boot-1.1.6/include/configs/bfin_adi_common.h
7853@@ -9,10 +9,15 @@
7854 * Command Settings
7855 */
7856 #ifndef CONFIG_COMMANDS
7857+# ifdef CFG_NO_FLASH
7858+# define ADI_CMDS_BASE1 (CONFIG_CMD_DFL & ~(CFG_CMD_IMLS | CFG_CMD_FLASH))
7859+#else
7860+# define ADI_CMDS_BASE1 (CONFIG_CMD_DFL)
7861+# endif
7862 # if ADI_CMDS_NETWORK
7863-# define ADI_CMDS_BASE (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_DHCP)
7864+# define ADI_CMDS_BASE (ADI_CMDS_BASE1 | CFG_CMD_PING | CFG_CMD_DHCP)
7865 # else
7866-# define ADI_CMDS_BASE (CONFIG_CMD_DFL & ~CFG_CMD_NET)
7867+# define ADI_CMDS_BASE (ADI_CMDS_BASE1 & ~CFG_CMD_NET)
7868 # endif
7869 # ifdef CONFIG_RTC_BFIN
7870 # define ADI_CMDS_DATE (CFG_CMD_DATE)
7871@@ -144,9 +149,16 @@
7872 #else
7873 # define NETWORK_ENV_SETTINGS
7874 #endif
7875+
7876+#ifdef METROLOGIC_FLASH_BOOT_ENV_PARAM
7877+ #define EXTRA_ENV_SETTINGS METROLOGIC_FLASH_BOOT_ENV_PARAM
7878+#else
7879+ #define EXTRA_ENV_SETTINGS "flashboot=bootm 0x20060000\0"
7880+#endif
7881+
7882 #define CONFIG_EXTRA_ENV_SETTINGS \
7883 NETWORK_ENV_SETTINGS \
7884- "flashboot=bootm 0x20100000\0"
7885+ EXTRA_ENV_SETTINGS
7886
7887 /*
7888 * Network Settings
7889diff --git a/u-boot-1.1.6/include/flash.h b/u-boot-1.1.6/include/flash.h
7890index c9129cd..c35d87e 100644
7891--- a/u-boot-1.1.6/include/flash.h
7892+++ b/u-boot-1.1.6/include/flash.h
7893@@ -24,7 +24,6 @@
7894 #ifndef _FLASH_H_
7895 #define _FLASH_H_
7896
7897-#ifndef CFG_NO_FLASH
7898 /*-----------------------------------------------------------------------
7899 * FLASH Info: contains chip specific data, per FLASH bank
7900 */
7901@@ -49,6 +48,8 @@ typedef struct {
7902 #endif
7903 } flash_info_t;
7904
7905+#ifndef CFG_NO_FLASH
7906+
7907 /*
7908 * Values for the width of the port
7909 */
7910diff --git a/u-boot-1.1.6/include/metro_pf.h b/u-boot-1.1.6/include/metro_pf.h
7911new file mode 100644
7912index 0000000..f274139
7913--- /dev/null
7914+++ b/u-boot-1.1.6/include/metro_pf.h
7915@@ -0,0 +1,103 @@
7916+#ifndef METRO_PF_H
7917+#define METRO_PF_H
7918+
7919+
7920+#ifndef PF_bit
7921+#define PF_bit(pfx) ( 1 << (pfx & 0x0f) )
7922+#endif
7923+
7924+//#ifndef CSYNC
7925+//#define CSYNC asm("csync;")
7926+//#endif
7927+
7928+//#ifndef SSYNC
7929+//#define SSYNC asm("ssync;")
7930+//#endif
7931+
7932+
7933+#if (defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)) || \
7934+ defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
7935+
7936+#define Metro_set_pfx_level(pf_num, level) \
7937+{ \
7938+ if ((pf_num >= 0) && (pf_num < 48)) \
7939+ { \
7940+ if (level) \
7941+ { \
7942+ if (pf_num < 16) \
7943+ *pPORTFIO_SET = PF_bit(pf_num); \
7944+ else if (pf_num < 32) \
7945+ *pPORTGIO_SET = PF_bit(pf_num); \
7946+ else \
7947+ *pPORTHIO_SET = PF_bit(pf_num); \
7948+ } \
7949+ else \
7950+ { \
7951+ if (pf_num < 16) \
7952+ *pPORTFIO_CLEAR = PF_bit(pf_num); \
7953+ else if (pf_num < 32) \
7954+ *pPORTGIO_CLEAR = PF_bit(pf_num); \
7955+ else \
7956+ *pPORTHIO_CLEAR = PF_bit(pf_num); \
7957+ } \
7958+ SSYNC(); \
7959+ } \
7960+}
7961+
7962+/*
7963+ * Return value:
7964+ * 0: level low
7965+ * 1: level high
7966+ */
7967+#define Metro_get_pfx_level(pf_num) ( (pf_num < 16) ? \
7968+ ( ( (*pPORTFIO ^ *pPORTFIO_POLAR) & PF_bit(pf_num) ) ? 1 : 0) : \
7969+ (pf_num < 32) ? \
7970+ ( ( (*pPORTGIO ^ *pPORTGIO_POLAR) & PF_bit(pf_num) ) ? 1 : 0) : \
7971+ ( ( (*pPORTHIO ^ *pPORTHIO_POLAR) & PF_bit(pf_num) ) ? 1 : 0) )
7972+
7973+#elif (defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) || \
7974+defined(__ADSPBF531__)) || defined(__ADSPBF532__) || defined(__ADSPBF533__)
7975+
7976+#define Metro_set_pfx_level(pf_num, level) \
7977+{ \
7978+ if ((pf_num >= 0) && (pf_num < 16)) \
7979+ { \
7980+ if (level) \
7981+ *pFIO_FLAG_S = PF_bit(pf_num); \
7982+ else \
7983+ *pFIO_FLAG_C = PF_bit(pf_num); \
7984+ SSYNC(); \
7985+ } \
7986+}
7987+
7988+/*
7989+ * Return value:
7990+ * 0: level low
7991+ * 1: level high
7992+ */
7993+#define Metro_get_pfx_level(pf_num) ( ( (*pFIO_FLAG_D ^ *pFIO_POLAR) & PF_bit(pf_num) ) ? 1 : 0)
7994+
7995+#else
7996+
7997+#error "Platform not supported"
7998+
7999+#endif
8000+
8001+
8002+
8003+//#define GPDRX_OUT(gpio_pin) { Metro_set_pfx_dir(gpio_pin, 1, -1); }
8004+//#define GPDRX_IN(gpio_pin) { Metro_set_pfx_dir(gpio_pin, 0, -1); }
8005+
8006+//#define SET_PIN(gpio_pin) { Metro_set_pfx_level(gpio_pin, 1); }
8007+//#define CLR_PIN(gpio_pin) { Metro_set_pfx_level(gpio_pin, 0); }
8008+//#define GET_PIN_LEVEL(gpio_pin) ( Metro_get_pfx_level(gpio_pin) )
8009+
8010+extern int Metro_set_pfx_dir(int pf_num, int dir, int initial_val);
8011+extern int Metro_get_pfx_dir(int pf_num);
8012+
8013+extern int set_pfx_dir(int pf_num, int dir);
8014+extern int get_pfx_dir(int pf_num);
8015+extern int get_pfx_level(int pf_num);
8016+extern int set_pfx_level(int pf_num, int level);
8017+
8018+#endif /* METRO_PF_H */
8019diff --git a/u-boot-1.1.6/lib_blackfin/board.c b/u-boot-1.1.6/lib_blackfin/board.c
8020index 942bfbc..5d32f12 100644
8021--- a/u-boot-1.1.6/lib_blackfin/board.c
8022+++ b/u-boot-1.1.6/lib_blackfin/board.c
8023@@ -46,7 +46,15 @@
8024 int post_flag;
8025 #endif
8026
8027-const char version_string[] = U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ")";
8028+#define VERSION_STRING_FORMAT "%s (%s - %s)\n%s\n%s (%s)\n"
8029+#define METROLOGIC_NAME "Metrologic Instruments, Inc."
8030+#define METROLOGIC_VERSION "Alex_2008R1_Ver1"
8031+#ifndef METROLOGIC_PLATFORM
8032+#define METROLOGIC_PLATFORM "UNKNOWN_PLATFORM"
8033+#endif
8034+const char version_string[] = U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ") " METROLOGIC_NAME " " METROLOGIC_PLATFORM " " METROLOGIC_VERSION ;
8035+
8036+//const char version_string[] = U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ")";
8037
8038 __attribute__((always_inline))
8039 static inline void serial_early_puts(const char *s)
8040@@ -160,7 +168,9 @@ static void display_global_data(void)
8041 printf(" |-jt(%x): %x\n", gd->jt, *(gd->jt));
8042 printf(" \\-bd: %x\n", gd->bd);
8043 printf(" |-bi_baudrate: %x\n", bd->bi_baudrate);
8044+#if (CONFIG_COMMANDS & CFG_CMD_NET)
8045 printf(" |-bi_ip_addr: %x\n", bd->bi_ip_addr);
8046+#endif
8047 printf(" |-bi_enetaddr: %x %x %x %x %x %x\n",
8048 bd->bi_enetaddr[0], bd->bi_enetaddr[1],
8049 bd->bi_enetaddr[2], bd->bi_enetaddr[3],
8050@@ -464,6 +474,24 @@ void board_init_r(gd_t * id, ulong dest_addr)
8051 post_run(NULL, POST_RAM | post_bootmode_get(0));
8052 #endif
8053
8054+#if defined(CONFIG_METROLOGIC_IO_INIT)
8055+ /* miscellaneous platform dependent initialisations */
8056+#if defined(DEBUG_METRO_IO)
8057+ printf("start metrologic_io_init()\r\n");
8058+#endif
8059+ udelay(50 * 1000);
8060+ metrologic_io_init();
8061+#if defined(DEBUG_METRO_IO)
8062+ printf("done metrologic_io_init()\r\n");
8063+#endif
8064+#endif
8065+
8066+#if defined(CONFIG_CORE_VOLTAGE_MILLIVOLT)
8067+ program_vrctl(CONFIG_CORE_VOLTAGE_MILLIVOLT);
8068+#elif defined(CONFIG_DISABLE_CLKIN_OUTPUT)
8069+ program_vrctl(0);
8070+#endif // CONFIG_CORE_VOLTAGE_MILLIVOLT
8071+
8072 /* main_loop() can return to retry autoboot, if so just run it again. */
8073 for (;;) {
8074 main_loop();
8075diff --git a/u-boot-1.1.6/uses.mak b/u-boot-1.1.6/uses.mak
8076new file mode 100644
8077index 0000000..84483e4
8078--- /dev/null
8079+++ b/u-boot-1.1.6/uses.mak
8080@@ -0,0 +1,5 @@
8081+KERNEL_REV = 2007R1/Bfin_422
8082+TOOLCHAIN_REV = Ver_2008R1.5
8083+
8084+
8085+CROSS_COMPILE_PATH = /usr/src/blackfin/ADI_release/tools/$(TOOLCHAIN_REV)/bfin-uclinux/bin
8086--
80871.6.0.2
8088
random patches; mostly (all?) dead