scummvm random work
[patches.git] / blackfin-serial-cts-rts-sep-ports.patch
1 --- uClinux-dist/linux-2.6.x/drivers/serial/Kconfig
2 +++ uClinux-dist/linux-2.6.x/drivers/serial/Kconfig
3 @@ -1003,8 +1003,8 @@ config BFIN_UART0_CTSRTS
4 bool "CTS and RTS setting for UART0"
5 depends on BFIN_UART_CTSRTS
6
7 -config BFIN_UART0_CTSRTS_PORT
8 - string "UART0 GPIO port for CTS and RTS"
9 +config BFIN_UART0_CTS_PORT
10 + string "UART0 GPIO port for CTS"
11 default 'G' if (BF534||BF536||BF537)
12 default 'F' if (BF531||BF532||BF533)
13 depends on BFIN_UART0_CTSRTS
14 @@ -1020,6 +1020,16 @@ config BFIN_UART0_CTS
15 help
16 This is the UART0 CTS bit number in the select GPIO port.
17
18 +config BFIN_UART0_RTS_PORT
19 + string "UART0 GPIO port for RTS"
20 + default 'G' if (BF534||BF536||BF537)
21 + default 'F' if (BF531||BF532||BF533)
22 + depends on BFIN_UART0_CTSRTS
23 + help
24 + This is GPIO port used by CTS and RTS of UART0.
25 + On BF531,532,533, only 'F' is supported.
26 + On BF534,536,537, 'F', 'G' and 'H' are supported.
27 +
28 config BFIN_UART0_RTS
29 int "UART0 RTS control bit in GPIO port"
30 depends on BFIN_UART0_CTSRTS
31 --- uClinux-dist/linux-2.6.x/drivers/serial/bfin_serial_5xx.c
32 +++ uClinux-dist/linux-2.6.x/drivers/serial/bfin_serial_5xx.c
33 @@ -272,33 +272,53 @@ static inline void bfin_uart_write_PORTI
34 # endif
35 }
36
37 -static inline void bfin_uart_portio_ctsrts_init(char *port, unsigned short cts, unsigned short rts)
38 +static inline void bfin_uart_portio_cts_init(const char *port, const unsigned short gpio)
39 {
40 # if defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
41 switch(port[0]) {
42 case 'F':
43 - bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~(1 << cts));
44 - bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | (1 << cts));
45 - bfin_write_PORTFIO_MASKA_SET(bfin_read_PORTFIO_MASKA_SET() & ~(1 << cts));
46 - bfin_write_PORTFIO_MASKB_SET(bfin_read_PORTFIO_MASKB_SET() & ~(1 << cts));
47 - bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | (1 << rts));
48 - bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~((1 << rts)|(1 << cts)|0x3));
49 + bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~(1 << gpio));
50 + bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | (1 << gpio));
51 + bfin_write_PORTFIO_MASKA_SET(bfin_read_PORTFIO_MASKA_SET() & ~(1 << gpio));
52 + bfin_write_PORTFIO_MASKB_SET(bfin_read_PORTFIO_MASKB_SET() & ~(1 << gpio));
53 + bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~((1 << gpio)|0x3));
54 break;
55 case 'G':
56 - bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() & ~(1 << cts));
57 - bfin_write_PORTGIO_INEN(bfin_read_PORTGIO_INEN() | (1 << cts));
58 - bfin_write_PORTGIO_MASKA_SET(bfin_read_PORTGIO_MASKA_SET() & ~(1 << cts));
59 - bfin_write_PORTGIO_MASKB_SET(bfin_read_PORTGIO_MASKB_SET() & ~(1 << cts));
60 - bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | (1 << rts));
61 - bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~((1 << rts)|(1 << cts)|0x3));
62 + bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() & ~(1 << gpio));
63 + bfin_write_PORTGIO_INEN(bfin_read_PORTGIO_INEN() | (1 << gpio));
64 + bfin_write_PORTGIO_MASKA_SET(bfin_read_PORTGIO_MASKA_SET() & ~(1 << gpio));
65 + bfin_write_PORTGIO_MASKB_SET(bfin_read_PORTGIO_MASKB_SET() & ~(1 << gpio));
66 + bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~((1 << gpio)|0x3));
67 break;
68 case 'H':
69 - bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~(1 << cts));
70 - bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | (1 << cts));
71 - bfin_write_PORTHIO_MASKA_SET(bfin_read_PORTHIO_MASKA_SET() & ~(1 << cts));
72 - bfin_write_PORTHIO_MASKB_SET(bfin_read_PORTHIO_MASKB_SET() & ~(1 << cts));
73 - bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | (1 << rts));
74 - bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~((1 << rts)|(1 << cts)|0x3));
75 + bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~(1 << gpio));
76 + bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | (1 << gpio));
77 + bfin_write_PORTHIO_MASKA_SET(bfin_read_PORTHIO_MASKA_SET() & ~(1 << gpio));
78 + bfin_write_PORTHIO_MASKB_SET(bfin_read_PORTHIO_MASKB_SET() & ~(1 << gpio));
79 + bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~((1 << gpio)|0x3));
80 + break;
81 + default:
82 + break;
83 + }
84 + SSYNC;
85 +# endif
86 +}
87 +
88 +static inline void bfin_uart_portio_rts_init(const char *port, const unsigned short gpio)
89 +{
90 +# if defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
91 + switch(port[0]) {
92 + case 'F':
93 + bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | (1 << gpio));
94 + bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~((1 << gpio)|0x3));
95 + break;
96 + case 'G':
97 + bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | (1 << gpio));
98 + bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~((1 << gpio)|0x3));
99 + break;
100 + case 'H':
101 + bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | (1 << gpio));
102 + bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~((1 << gpio)|0x3));
103 break;
104 default:
105 break;
106 @@ -320,13 +340,13 @@ static inline void bfin_setsignal(struct
107 switch(info->line) {
108 # ifdef CONFIG_BFIN_UART0_CTSRTS
109 case 0:
110 - port = CONFIG_BFIN_UART0_CTSRTS_PORT;
111 + port = CONFIG_BFIN_UART0_RTS_PORT;
112 rts_mask = (1 << CONFIG_BFIN_UART0_RTS);
113 break;
114 # endif
115 # ifdef CONFIG_BFIN_UART1_CTSRTS
116 case 1:
117 - port = CONFIG_BFIN_UART1_CTSRTS_PORT;
118 + port = CONFIG_BFIN_UART1_RTS_PORT;
119 rts_mask = (1 << CONFIG_BFIN_UART1_RTS);
120 break;
121 # endif
122 @@ -359,13 +379,13 @@ static inline int bfin_getsignal(struct
123 switch(info->line) {
124 # ifdef CONFIG_BFIN_UART0_CTSRTS
125 case 0:
126 - port = CONFIG_BFIN_UART0_CTSRTS_PORT;
127 + port = CONFIG_BFIN_UART0_CTS_PORT;
128 cts_mask = (1 << CONFIG_BFIN_UART0_CTS);
129 break;
130 # endif
131 # ifdef CONFIG_BFIN_UART1_CTSRTS
132 case 1:
133 - port = CONFIG_BFIN_UART1_CTSRTS_PORT;
134 + port = CONFIG_BFIN_UART1_CTS_PORT;
135 cts_mask = (1 << CONFIG_BFIN_UART1_CTS);
136 break;
137 # endif
138 @@ -2005,8 +2025,8 @@ int rs_open(struct tty_struct *tty, stru
139 }
140 }
141 #if defined(CONFIG_BFIN_UART0_CTSRTS)
142 - bfin_uart_portio_ctsrts_init(CONFIG_BFIN_UART0_CTSRTS_PORT,
143 - CONFIG_BFIN_UART0_CTS, CONFIG_BFIN_UART0_RTS);
144 + bfin_uart_portio_cts_init(CONFIG_BFIN_UART0_CTS_PORT, CONFIG_BFIN_UART0_CTS);
145 + bfin_uart_portio_rts_init(CONFIG_BFIN_UART0_RTS_PORT, CONFIG_BFIN_UART0_RTS);
146 #endif
147 }
148 #if defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
149 @@ -2025,8 +2045,8 @@ int rs_open(struct tty_struct *tty, stru
150 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0xc);
151 SSYNC;
152 # if defined(CONFIG_BFIN_UART1_CTSRTS)
153 - bfin_uart_portio_ctsrts_init(CONFIG_BFIN_UART1_CTSRTS_PORT,
154 - CONFIG_BFIN_UART1_CTS, CONFIG_BFIN_UART1_RTS);
155 + bfin_uart_portio_cts_init(CONFIG_BFIN_UART1_CTS_PORT, CONFIG_BFIN_UART1_CTS);
156 + bfin_uart_portio_rts_init(CONFIG_BFIN_UART1_RTS_PORT, CONFIG_BFIN_UART1_RTS);
157 # endif
158 }
159 #endif
160 @@ -2311,8 +2331,8 @@ int bfin_console_setup(struct console *c
161 #endif
162 SSYNC;
163 #ifdef CONFIG_BFIN_UART0_CTSRTS
164 - bfin_uart_portio_ctsrts_init(CONFIG_BFIN_UART0_CTSRTS_PORT,
165 - CONFIG_BFIN_UART0_CTS, CONFIG_BFIN_UART0_RTS);
166 + bfin_uart_portio_cts_init(CONFIG_BFIN_UART0_CTS_PORT, CONFIG_BFIN_UART0_CTS);
167 + bfin_uart_portio_rts_init(CONFIG_BFIN_UART0_RTS_PORT, CONFIG_BFIN_UART0_RTS);
168 #endif
169 }
170 #if defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
171 @@ -2321,8 +2341,8 @@ int bfin_console_setup(struct console *c
172 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0xc);
173 SSYNC;
174 # ifdef CONFIG_BFIN_UART1_CTSRTS
175 - bfin_uart_portio_ctsrts_init(CONFIG_BFIN_UART1_CTSRTS_PORT,
176 - CONFIG_BFIN_UART1_CTS, CONFIG_BFIN_UART1_RTS);
177 + bfin_uart_portio_cts_init(CONFIG_BFIN_UART1_CTS_PORT, CONFIG_BFIN_UART1_CTS);
178 + bfin_uart_portio_rts_init(CONFIG_BFIN_UART1_RTS_PORT, CONFIG_BFIN_UART1_RTS);
179 # endif
180 }
181 #endif