1 --- uCam.c.orig 2006-10-04 18:44:26.000000000 +0200
2 +++ uCam.c 2006-10-04 18:58:00.000000000 +0200
12 struct pt_regs *regs )
16 + struct uCam_buffer *tmp_buf;
17 ppi_device_t *pdev = (ppi_device_t*)dev_id;
19 BUG_ON(dev_id == NULL);
21 + // Acknowledge DMA Interrupt
22 + clear_dma_irqstat(CH_PPI);
24 status = bfin_read_PPI_STATUS();
26 #if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
27 bfin_write_PPI_STATUS(0xFFFF); //BF537/6/4 PPI_STATUS is Write to Clear
28 #endif // CONFIG_BF537/6/4
31 - DPRINTK("-->ppifcd_irq_error: PPI Status = 0x%X \n", status);
34 bfin_write_PPI_CONTROL(pdev->ppi_control & ~PORT_EN);
36 - DPRINTK("-->ppifcd_irq_error: buf [0x%p]\n", uCam_dev->dma_buf->data);
38 + DPRINTK("->ppifcd_irq: pdev->done=%d (%ld)\n", pdev->done, jiffies*1000/HZ);
40 + uCam_dev->dma_buf->state = FRAME_DONE;
41 + DPRINTK("->ppifcd_irq: active buffer [0x%p] done\n",
42 + uCam_dev->dma_buf->data);
43 + DPRINTK("->ppifcd_irq: next [0x%p] state %d\n",
44 + uCam_dev->next_buf->data,
45 + uCam_dev->next_buf->state);
47 + if( waitqueue_active(&uCam_dev->dma_buf->wq) )
48 + wake_up_interruptible(&uCam_dev->dma_buf->wq);
50 + if( uCam_dev->next_buf->state == FRAME_READY ) { // if next frame is ready for grabbing
51 + DPRINTK("->ppifcd_irq: initiating next grab [0x%p]\n", uCam_dev->next_buf->data);
52 + tmp_buf = uCam_dev->dma_buf;
53 + uCam_dev->dma_buf = uCam_dev->next_buf;
54 + uCam_dev->next_buf = tmp_buf;
55 + uCam_dev->dma_buf->state = FRAME_GRABBING;
56 + count = ppi2dma(uCam_dev->ppidev, uCam_dev->dma_buf->data, uCam_dev->size);
60 + kill_fasync( &(pdev->fasyc), SIGIO, POLLIN );
61 + wake_up_interruptible( pdev->rx_avail );
71 +// struct pt_regs *regs )
73 +// ppi_device_t *pdev = (ppi_device_t*)dev_id;
75 +// BUG_ON(dev_id == NULL);
77 +// status = bfin_read_PPI_STATUS();
79 +//#if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
80 +// bfin_write_PPI_STATUS(0xFFFF); //BF537/6/4 PPI_STATUS is Write to Clear
81 +//#endif // CONFIG_BF537/6/4
84 +// DPRINTK("-->ppifcd_irq_error: PPI Status = 0x%X \n", status);
87 +// bfin_write_PPI_CONTROL(pdev->ppi_control & ~PORT_EN);
89 +// DPRINTK("-->ppifcd_irq_error: buf [0x%p]\n", uCam_dev->dma_buf->data);
91 +// return IRQ_HANDLED;