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Commit | Line | Data |
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5e993f12 | 1 | Index: cpu/bf548/init_sdram.S |
2 | =================================================================== | |
3 | --- cpu/bf548/init_sdram.S (revision 817) | |
4 | +++ cpu/bf548/init_sdram.S (working copy) | |
5 | @@ -38,6 +38,15 @@ init_sdram: | |
6 | [--SP] = (R7:0); | |
7 | [--SP] = (P5:0); | |
8 | ||
9 | +#if (BFIN_BOOT_MODE == BFIN_UART_BOOT) | |
10 | + /* force RTS rather than relying on auto RTS */ | |
11 | + P3.h = hi(UART1_MCR) | |
12 | + P3.l = lo(UART1_MCR) | |
13 | + R0 = w[P3]; | |
14 | + bitset(R0, 5); | |
15 | + w[p3] = R0; | |
16 | +#endif | |
17 | + | |
18 | /************************************************* | |
19 | * System interrupt wakeup registers (SIC_IWRx) * | |
20 | * Required for PLL_CTL and VR_CTL configuration * | |
21 | @@ -239,8 +248,17 @@ test_failed: | |
22 | r0.l = 0x0080; /* Test failed, light on LED2 */ | |
23 | w[p0]= r0; | |
24 | ssync | |
25 | - | |
26 | ddr_init_end: | |
27 | + | |
28 | +#if (BFIN_BOOT_MODE == BFIN_UART_BOOT) | |
29 | + /* clear forced RTS rather than relying on auto RTS */ | |
30 | + P3.h = hi(UART1_MCR) | |
31 | + P3.l = lo(UART1_MCR) | |
32 | + R0 = w[P3]; | |
33 | + bitclr(R0, 5); | |
34 | + w[p3] = R0; | |
35 | +#endif | |
36 | + | |
37 | (P5:0) = [SP++]; | |
38 | (R7:0) = [SP++]; | |
39 | RETS = [SP++]; |