--- /dev/null
+From 9ecb85954275f5a62293e1416dba107058609117 Mon Sep 17 00:00:00 2001
+From: Mike Frysinger <vapier@gentoo.org>
+Date: Tue, 14 Oct 2008 18:06:33 -0400
+Subject: [PATCH] metrologic fork
+
+---
+ u-boot-1.1.6/Makefile | 22 +-
+ u-boot-1.1.6/board/Focus/Focus.c | 516 +++++++++++++++++++
+ u-boot-1.1.6/board/Focus/Makefile | 59 +++
+ u-boot-1.1.6/board/IS4980/IS4980.c | 516 +++++++++++++++++++
+ u-boot-1.1.6/board/IS4980/Makefile | 59 +++
+ u-boot-1.1.6/board/Orbit3/Makefile | 59 +++
+ u-boot-1.1.6/board/Orbit3/Orbit3.c | 516 +++++++++++++++++++
+ u-boot-1.1.6/board/VuQuest2D/Makefile | 59 +++
+ u-boot-1.1.6/board/VuQuest2D/VuQuest2D.c | 418 +++++++++++++++
+ u-boot-1.1.6/board/VuQuest2D/VuQuest2D.h | 53 ++
+ u-boot-1.1.6/board/VuQuest2D/config.mk | 15 +
+ u-boot-1.1.6/board/VuQuest2D/spi.c | 533 ++++++++++++++++++++
+ u-boot-1.1.6/board/VuQuest2D/spi_flash.c | 2 +
+ u-boot-1.1.6/board/VuQuest2D/u-boot.lds.S | 136 +++++
+ u-boot-1.1.6/board/VuQuest2D/video.c | 187 +++++++
+ u-boot-1.1.6/board/VuQuest2D/video.h | 25 +
+ u-boot-1.1.6/common/Makefile | 2 +-
+ u-boot-1.1.6/common/cmd_bdinfo.c | 40 +-
+ u-boot-1.1.6/common/cmd_bootm.c | 13 +
+ u-boot-1.1.6/common/cmd_eeprom.c | 12 +
+ u-boot-1.1.6/common/cmd_load.c | 456 +++++++++++++++++
+ u-boot-1.1.6/common/cmd_mem.c | 96 ++++
+ u-boot-1.1.6/common/interface_select.c | 526 +++++++++++++++++++
+ u-boot-1.1.6/common/main.c | 123 +++++-
+ u-boot-1.1.6/common/metro_pf.c | 318 ++++++++++++
+ u-boot-1.1.6/cpu/blackfin/i2c.c | 36 ++-
+ u-boot-1.1.6/cpu/blackfin/serial.c | 82 +++
+ u-boot-1.1.6/examples/Makefile | 14 +
+ u-boot-1.1.6/include/Metrologic_Hardware.h | 69 +++
+ .../include/asm-blackfin/blackfin-config-post.h | 50 +--
+ .../include/asm-blackfin/blackfin_clocks.h | 56 ++
+ u-boot-1.1.6/include/asm-blackfin/mem_init.h | 338 +++++++++++++
+ u-boot-1.1.6/include/configs/Focus.h | 381 ++++++++++++++
+ u-boot-1.1.6/include/configs/IS4980.h | 378 ++++++++++++++
+ u-boot-1.1.6/include/configs/Orbit3.h | 378 ++++++++++++++
+ u-boot-1.1.6/include/configs/VuQuest2D.h | 309 ++++++++++++
+ u-boot-1.1.6/include/configs/bf533-stamp.h | 47 ++-
+ u-boot-1.1.6/include/configs/bf537-srv1.h | 50 ++-
+ u-boot-1.1.6/include/configs/bf537-stamp.h | 52 ++-
+ u-boot-1.1.6/include/configs/bfin_adi_common.h | 18 +-
+ u-boot-1.1.6/include/flash.h | 3 +-
+ u-boot-1.1.6/include/metro_pf.h | 103 ++++
+ u-boot-1.1.6/lib_blackfin/board.c | 30 ++-
+ u-boot-1.1.6/uses.mak | 5 +
+ 44 files changed, 7051 insertions(+), 109 deletions(-)
+ create mode 100644 u-boot-1.1.6/board/Focus/Focus.c
+ create mode 100644 u-boot-1.1.6/board/Focus/Makefile
+ create mode 100644 u-boot-1.1.6/board/IS4980/IS4980.c
+ create mode 100644 u-boot-1.1.6/board/IS4980/Makefile
+ create mode 100644 u-boot-1.1.6/board/Orbit3/Makefile
+ create mode 100644 u-boot-1.1.6/board/Orbit3/Orbit3.c
+ create mode 100644 u-boot-1.1.6/board/VuQuest2D/Makefile
+ create mode 100644 u-boot-1.1.6/board/VuQuest2D/VuQuest2D.c
+ create mode 100644 u-boot-1.1.6/board/VuQuest2D/VuQuest2D.h
+ create mode 100644 u-boot-1.1.6/board/VuQuest2D/config.mk
+ create mode 100644 u-boot-1.1.6/board/VuQuest2D/spi.c
+ create mode 100644 u-boot-1.1.6/board/VuQuest2D/spi_flash.c
+ create mode 100644 u-boot-1.1.6/board/VuQuest2D/u-boot.lds.S
+ create mode 100644 u-boot-1.1.6/board/VuQuest2D/video.c
+ create mode 100644 u-boot-1.1.6/board/VuQuest2D/video.h
+ create mode 100644 u-boot-1.1.6/common/interface_select.c
+ create mode 100644 u-boot-1.1.6/common/metro_pf.c
+ create mode 100644 u-boot-1.1.6/include/Metrologic_Hardware.h
+ create mode 100644 u-boot-1.1.6/include/asm-blackfin/blackfin_clocks.h
+ create mode 100644 u-boot-1.1.6/include/asm-blackfin/mem_init.h
+ create mode 100644 u-boot-1.1.6/include/configs/Focus.h
+ create mode 100644 u-boot-1.1.6/include/configs/IS4980.h
+ create mode 100644 u-boot-1.1.6/include/configs/Orbit3.h
+ create mode 100644 u-boot-1.1.6/include/configs/VuQuest2D.h
+ create mode 100644 u-boot-1.1.6/include/metro_pf.h
+ create mode 100644 u-boot-1.1.6/uses.mak
+
+diff --git a/u-boot-1.1.6/Makefile b/u-boot-1.1.6/Makefile
+index b3502bb..e4e761d 100644
+--- a/u-boot-1.1.6/Makefile
++++ b/u-boot-1.1.6/Makefile
+@@ -1,3 +1,4 @@
++include uses.mak
+ #
+ # (C) Copyright 2000-2006
+ # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+@@ -147,7 +148,7 @@ ifeq ($(ARCH),microblaze)
+ CROSS_COMPILE = mb-
+ endif
+ ifeq ($(ARCH),blackfin)
+-CROSS_COMPILE = bfin-uclinux-
++CROSS_COMPILE = $(CROSS_COMPILE_PATH)/bfin-uclinux-
+ endif
+ ifeq ($(ARCH),avr32)
+ CROSS_COMPILE = avr32-
+@@ -191,9 +192,21 @@ endif
+ LIBS += lib_$(ARCH)/lib$(ARCH).a
+ LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
+ fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a
++
++ifneq ($(BOARD), IS4980)
++ifneq ($(BOARD), Orbit3)
++ifneq ($(BOARD), VuQuest2D)
++ifneq ($(BOARD), Focus)
++ifneq ($(BOARD), bf533-stamp)
+ LIBS += net/libnet.a
+ LIBS += disk/libdisk.a
+ LIBS += rtc/librtc.a
++endif
++endif
++endif
++endif
++endif
++
+ LIBS += dtt/libdtt.a
+ LIBS += drivers/libdrivers.a
+ LIBS += drivers/nand/libnand.a
+@@ -2264,6 +2277,9 @@ BFIN_BOARDS += cm-bf533 cm-bf537e cm-bf548 cm-bf561
+ # Misc third party boards
+ BFIN_BOARDS += bf537-minotaur bf537-srv1
+
++# Metrologic boards
++BFIN_BOARDS += Focus Orbit3 VuQuest2D IS4980
++
+ $(BFIN_BOARDS:%=%_config) : unconfig
+ @$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
+ @[ "$(SRCTREE)" != "$(OBJTREE)" ] && LNPREFIX="../../include2/asm/" || LNPREFIX="" ; \
+@@ -2321,6 +2337,10 @@ clean:
+ rm -f $(obj)board/cm-bf537e/u-boot.lds
+ rm -f $(obj)board/cm-bf548/u-boot.lds
+ rm -f $(obj)board/cm-bf561/u-boot.lds
++ rm -f $(obj)board/Focus/u-boot.lds
++ rm -f $(obj)board/Orbit3/u-boot.lds
++ rm -f $(obj)board/IS4980/u-boot.lds
++ rm -f $(obj)board/VuQuest2D/u-boot.lds
+ rm -f $(obj)cpu/blackfin/bootrom-asm-offsets.[chs] $(obj).syms.u-boot.S
+ rm -f $(obj)include/bmp_logo.h
+ rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
+diff --git a/u-boot-1.1.6/board/Focus/Focus.c b/u-boot-1.1.6/board/Focus/Focus.c
+new file mode 100644
+index 0000000..d2ab196
+--- /dev/null
++++ b/u-boot-1.1.6/board/Focus/Focus.c
+@@ -0,0 +1,516 @@
++/*
++ * U-boot - Focus.c
++ *
++ * Copyright (c) 2008 Metrologic Instruments Inc.
++ * Copyright (c) 2005-2007 Analog Devices Inc.
++ *
++ * (C) Copyright 2000-2004
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
++ * MA 02110-1301 USA
++ */
++
++#include <common.h>
++#include <config.h>
++#include <command.h>
++#include <asm/blackfin.h>
++#include <asm/io.h>
++#include <linux/etherdevice.h>
++
++#define POST_WORD_ADDR 0xFF903FFC
++
++int checkboard(void)
++{
++ printf("Board: Metrologic Focus Decode Board\n");
++ printf(" Support: http://www.metrologic.com/\n");
++ return 0;
++}
++
++#if defined(CONFIG_BFIN_IDE)
++
++void cf_outb(unsigned char val, volatile unsigned char *addr)
++{
++ *(addr) = val;
++ SSYNC();
++}
++
++unsigned char cf_inb(volatile unsigned char *addr)
++{
++ volatile unsigned char c;
++
++ c = *(addr);
++ SSYNC();
++
++ return c;
++}
++
++void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
++{
++ int i;
++
++ for (i = 0; i < words; i++)
++ *(sect_buf + i) = *(addr);
++ SSYNC();
++}
++
++void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
++{
++ int i;
++
++ for (i = 0; i < words; i++)
++ *(addr) = *(sect_buf + i);
++ SSYNC();
++}
++#endif /* CONFIG_BFIN_IDE */
++
++long int initdram(int board_type)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++#ifdef DEBUG
++ int brate;
++ char *tmp = getenv("baudrate");
++ brate = simple_strtoul(tmp, NULL, 16);
++ printf("Serial Port initialized with Baud rate = %x\n", brate);
++ printf("SDRAM attributes:\n");
++ printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
++ "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
++ 3, 3, 6, 2, 3);
++ printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
++ printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
++#endif
++ gd->bd->bi_memstart = CFG_SDRAM_BASE;
++ gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
++ return CFG_MAX_RAM_SIZE;
++}
++
++int board_get_enetaddr(uchar *mac_addr)
++{
++#ifdef CFG_NO_FLASH
++# define USE_MAC_IN_FLASH 0
++#else
++# define USE_MAC_IN_FLASH 1
++#endif
++ if (USE_MAC_IN_FLASH) {
++ /* we cram the MAC in the last flash sector */
++ uchar *board_mac_addr = (uchar *)0x203F0000;
++
++ if (is_valid_ether_addr(board_mac_addr)) {
++ memcpy(mac_addr, board_mac_addr, 6);
++ return 0;
++ }
++ }
++
++ puts("Warning: Generating 'random' MAC address\n");
++
++ /* make something up */
++ const char s[] = __DATE__;
++ size_t i;
++ u32 cycles;
++ for (i = 0; i < 6; ++i) {
++ asm("%0 = CYCLES;" : "=r" (cycles));
++ mac_addr[i] = cycles ^ s[i];
++ }
++ mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */
++ return 0;
++}
++
++void board_reset(void)
++{ /* FIXME: Alex Au: Don't know if we need to use this workaround... */
++ /* workaround for weak pull ups on ssel */
++ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
++ bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10);
++ bfin_write_PORTFIO_SET(PF10);
++ udelay(1);
++ }
++}
++
++
++
++#ifdef CONFIG_METROLOGIC_IO_INIT
++
++int metrologic_io_init(void)
++{
++ /* Port F:
++
++ 0 (out) <<< Host RS232 TX >>>
++ 1 (in) <<< Host RS232 RX >>>
++ 2 (out) <<< I/O TX >>> / RDATA [h] (bfin_serial driver takes care of FER)
++ 3 (in) <<< I/O RX >>> / CLKOUT (bfin_serial driver takes care of FER)
++ 4 (out) BEEP [l]
++ 5 (out) Target [l]
++ 6 (out) cam_sync [l]
++ 7 (out) PSOC RESET [l]
++ 8 (in) <<< PPI_VSYNC >>> [later, input]
++ 9 (in) <<< PPI_HSYNC >>> [later, input]
++ 10 (out) <<< SPI_CS >>>
++ 11 (out) <<< SPI_MOSI >>>
++ 12 (in) <<< SPI_MISO >>>
++ 13 (out) <<< SPI_CLOCK >>>
++ 14 (out) SPI_WP [h]
++ 15 (in) <<< PPI_Clock >>> [later, input]
++
++ */
++
++ *pPORTF_FER = PF0|PF1|PF2|PF3|PF10|PF11|PF12|PF13; /* PPI enabled in image device driver */
++ *pPORTFIO_DIR |= PF4|PF5|PF6|PF7|PF14;
++ *pPORTFIO_DIR &= ~(PF8|PF9|PF15);
++ *pPORTFIO_INEN &= ~(PF4|PF5|PF6|PF7|PF14 | PF8|PF9|PF15);
++ *pPORTFIO &= ~(PF4|PF5|PF6|PF7);
++ *pPORTFIO |= PF14;
++
++ /* Port G:
++
++ 0 (in) <<< PPI_Data >>> [later, input]
++ 1 (in) <<< PPI_Data >>> [later, input]
++ 2 (in) <<< PPI_Data >>> [later, input]
++ 3 (in) <<< PPI_Data >>> [later, input]
++ 4 (in) <<< PPI_Data >>> [later, input]
++ 5 (in) <<< PPI_Data >>> [later, input]
++ 6 (in) <<< PPI_Data >>> [later, input]
++ 7 (in) <<< PPI_Data >>> [later, input]
++ 8 (out) FOCUS_KBWEN [l] when all I/O are set, then low
++ 9 (out) HOSTRTS ( Leave as input / output high until polarity is known )
++ 10 (out) FOCUS_IORTS ( Leave as input / output high until polarity is known )
++ 11 (out) FOCUS_KBWGATE [l]
++ 12 (out) LED Voltage Enable [h]
++ 13 (out) LED yellow [h]
++ 14 (out) LED white [h]
++ 15 (out) LED Blue [h]
++
++ */
++
++ *pPORTG_FER = 0;
++ *pPORTGIO_DIR = PG8|PG9|PG10|PG11|PG12|PG13|PG14|PG15;
++ *pPORTGIO_INEN = 0;
++ *pPORTGIO |= PG9|PG10|PG12|PG13|PG14|PG15;
++ *pPORTGIO &= ~(PG8|PG11);
++
++ /* Port H:
++
++ 0 (out) KBW_PCClk [l]
++ 1 (out) KBS_PCDATA [l]
++ 2 (in) IBM_Reset
++ 3 (in) DTR_IN
++ 4 (in) PC_DET / IBM/USB_EN
++ 5 (in) CLKIN
++ 6 (in) IR_IN
++ 7 (in) I/O CTS / SDATA
++ 8 (in) HOST CTS
++ 9 (in) BUTTON
++ 10 (in) READ SWITCH
++ 11 (out) FRAM_WP [h]
++ 12 (in) IR NEAR / FAR
++ 13 (out) Ocillator En. (Active high) [h]
++ 14 (out) Sensor Standby (Active low-Micron) [h]
++ 15 (out) Sensor Reset (Active High-Micron)[l]
++
++ */
++
++ *pPORTH_FER = 0;
++ *pPORTHIO_DIR = PH0|PH1|PH11|PH13|PH14|PH15;
++ *pPORTHIO_INEN = PH2|PH3|PH4|PH5|PH6|PH7|PH8|PH9|PH10|PH12;
++ *pPORTHIO |= PH11|PH13|PH14;
++ *pPORTHIO &= ~(PH0|PH1|PH15);
++
++ __builtin_bfin_ssync();
++
++#if defined(DEBUG_METRO_IO)
++ printf("start Configure_Interface_IO()\r\n");
++#endif
++ Configure_Interface_IO();
++#if defined(DEBUG_METRO_IO)
++ printf("done Configure_Interface_IO()\r\n");
++#endif
++
++ return 0;
++
++}
++
++#endif /* CONFIG_METROLOGIC_IO_INIT */
++#if defined(CONFIG_MISC_INIT_R)
++/* miscellaneous platform dependent initialisations */
++int misc_init_r(void)
++{
++#ifndef CFG_NO_FLASH
++ /* we use the last sector for the MAC address / POST DXE */
++ extern flash_info_t flash_info[];
++ flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
++#endif
++
++#if defined(CONFIG_BFIN_IDE)
++#if defined(CONFIG_BFIN_TRUE_IDE)
++ /* Enable ATASEL when in True IDE mode */
++ printf("Using CF True IDE Mode\n");
++ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
++ udelay(1000);
++#elif defined(CONFIG_BFIN_CF_IDE)
++ /* Disable ATASEL when we're in Common Memory Mode */
++ printf("Using CF Common Memory Mode\n");
++ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
++ udelay(1000);
++#elif defined(CONFIG_BFIN_HDD_IDE)
++ printf("Using HDD IDE Mode\n");
++#endif
++ ide_init();
++#endif /* CONFIG_BFIN_IDE */
++ return 0;
++}
++#endif /* CONFIG_MISC_INIT_R */
++
++#ifdef CONFIG_POST
++#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
++/* Using sw10-PF5 as the hotkey */
++int post_hotkeys_pressed(void)
++{
++ return 0;
++}
++#else
++/* Using sw10-PF5 as the hotkey */
++int post_hotkeys_pressed(void)
++{
++ int delay = 3;
++ int i;
++ unsigned short value;
++
++ *pPORTF_FER &= ~PF5;
++ *pPORTFIO_DIR &= ~PF5;
++ *pPORTFIO_INEN |= PF5;
++
++ printf("########Press SW10 to enter Memory POST########: %2d ", delay);
++ while (delay--) {
++ for (i = 0; i < 100; i++) {
++ value = *pPORTFIO & PF5;
++ if (value != 0) {
++ break;
++ }
++ udelay(10000);
++ }
++ printf("\b\b\b%2d ", delay);
++ }
++ printf("\b\b\b 0");
++ printf("\n");
++ if (value == 0)
++ return 0;
++ else {
++ printf("Hotkey has been pressed, Enter POST . . . . . .\n");
++ return 1;
++ }
++}
++#endif
++#endif
++
++#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
++void post_word_store(ulong a)
++{
++ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
++ *save_addr = a;
++}
++
++ulong post_word_load(void)
++{
++ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
++ return *save_addr;
++}
++#endif
++
++#ifdef CONFIG_POST
++int uart_post_test(int flags)
++{
++ return 0;
++}
++
++#define BLOCK_SIZE 0x10000
++#define VERIFY_ADDR 0x2000000
++extern int erase_block_flash(int);
++extern int write_data(long lStart, long lCount, uchar * pnData);
++int flash_post_test(int flags)
++{
++ unsigned short *pbuf, *temp;
++ int offset, n, i;
++ int value = 0;
++ int result = 0;
++ printf("\n");
++ pbuf = (unsigned short *)VERIFY_ADDR;
++ temp = pbuf;
++ for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
++ offset = (n - 7) * BLOCK_SIZE;
++ printf("--------Erase block:%2d..", n);
++ erase_block_flash(n);
++ printf("OK\r");
++ printf("--------Program block:%2d...", n);
++ write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
++ printf("OK\r");
++ printf("--------Verify block:%2d...", n);
++ for (i = 0; i < BLOCK_SIZE; i += 2) {
++ if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
++ *temp++) {
++ value = 1;
++ result = 1;
++ }
++ }
++ if (value)
++ printf("failed\n");
++ else
++ printf("OK %3d%%\r",
++ (int)(
++ (n + 1 -
++ FLASH_START_POST_BLOCK) *
++ 100 / (FLASH_END_POST_BLOCK -
++ FLASH_START_POST_BLOCK)));
++
++ temp = pbuf;
++ value = 0;
++ }
++ printf("\n");
++ if (result)
++ return -1;
++ else
++ return 0;
++}
++
++/****************************************************
++ * LED1 ---- PF6 LED2 ---- PF7 *
++ * LED3 ---- PF8 LED4 ---- PF9 *
++ * LED5 ---- PF10 LED6 ---- PF11 *
++ ****************************************************/
++int led_post_test(int flags)
++{
++ *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
++ *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
++ *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
++ *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
++ udelay(1000000);
++ printf("LED1 on");
++ *pPORTFIO |= PF6;
++ udelay(1000000);
++ printf("\b\b\b\b\b\b\b");
++ printf("LED2 on");
++ *pPORTFIO |= PF7;
++ udelay(1000000);
++ printf("\b\b\b\b\b\b\b");
++ printf("LED3 on");
++ *pPORTFIO |= PF8;
++ udelay(1000000);
++ printf("\b\b\b\b\b\b\b");
++ printf("LED4 on");
++ *pPORTFIO |= PF9;
++ udelay(1000000);
++ printf("\b\b\b\b\b\b\b");
++ printf("LED5 on");
++ *pPORTFIO |= PF10;
++ udelay(1000000);
++ printf("\b\b\b\b\b\b\b");
++ printf("lED6 on");
++ *pPORTFIO |= PF11;
++ printf("\b\b\b\b\b\b\b ");
++ return 0;
++}
++
++/************************************************
++ * SW10 ---- PF5 SW11 ---- PF4 *
++ * SW12 ---- PF3 SW13 ---- PF2 *
++ ************************************************/
++int button_post_test(int flags)
++{
++ int i, delay = 5;
++ unsigned short value = 0;
++ int result = 0;
++
++ *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
++ *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
++ *pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
++
++ printf("\n--------Press SW10: %2d ", delay);
++ while (delay--) {
++ for (i = 0; i < 100; i++) {
++ value = *pPORTFIO & PF5;
++ if (value != 0) {
++ break;
++ }
++ udelay(10000);
++ }
++ printf("\b\b\b%2d ", delay);
++ }
++ if (value != 0)
++ printf("\b\bOK");
++ else {
++ result = -1;
++ printf("\b\bfailed");
++ }
++
++ delay = 5;
++ printf("\n--------Press SW11: %2d ", delay);
++ while (delay--) {
++ for (i = 0; i < 100; i++) {
++ value = *pPORTFIO & PF4;
++ if (value != 0) {
++ break;
++ }
++ udelay(10000);
++ }
++ printf("\b\b\b%2d ", delay);
++ }
++ if (value != 0)
++ printf("\b\bOK");
++ else {
++ result = -1;
++ printf("\b\bfailed");
++ }
++
++ delay = 5;
++ printf("\n--------Press SW12: %2d ", delay);
++ while (delay--) {
++ for (i = 0; i < 100; i++) {
++ value = *pPORTFIO & PF3;
++ if (value != 0) {
++ break;
++ }
++ udelay(10000);
++ }
++ printf("\b\b\b%2d ", delay);
++ }
++ if (value != 0)
++ printf("\b\bOK");
++ else {
++ result = -1;
++ printf("\b\bfailed");
++ }
++
++ delay = 5;
++ printf("\n--------Press SW13: %2d ", delay);
++ while (delay--) {
++ for (i = 0; i < 100; i++) {
++ value = *pPORTFIO & PF2;
++ if (value != 0) {
++ break;
++ }
++ udelay(10000);
++ }
++ printf("\b\b\b%2d ", delay);
++ }
++ if (value != 0)
++ printf("\b\bOK");
++ else {
++ result = -1;
++ printf("\b\bfailed");
++ }
++ printf("\n");
++ return result;
++}
++#endif
+diff --git a/u-boot-1.1.6/board/Focus/Makefile b/u-boot-1.1.6/board/Focus/Makefile
+new file mode 100644
+index 0000000..4d03b2c
+--- /dev/null
++++ b/u-boot-1.1.6/board/Focus/Makefile
+@@ -0,0 +1,59 @@
++#
++# U-boot - Makefile
++#
++# Copyright (c) 2005-2007 Analog Device Inc.
++#
++# (C) Copyright 2000-2006
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).a
++
++COBJS := $(BOARD).o post-memory.o spi_flash.o cmd_bf537led.o nand.o
++#COBJS := $(BOARD).o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
++
++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++SOBJS := $(addprefix $(obj),$(SOBJS))
++
++$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
++
++u-boot.lds: u-boot.lds.S
++ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
++ mv -f $@.tmp $@
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/u-boot-1.1.6/board/IS4980/IS4980.c b/u-boot-1.1.6/board/IS4980/IS4980.c
+new file mode 100644
+index 0000000..4836853
+--- /dev/null
++++ b/u-boot-1.1.6/board/IS4980/IS4980.c
+@@ -0,0 +1,516 @@
++/*
++ * U-boot - Orbit3.c
++ *
++ * Copyright (c) 2008 Metrologic Instruments Inc.
++ * Copyright (c) 2005-2007 Analog Devices Inc.
++ *
++ * (C) Copyright 2000-2004
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
++ * MA 02110-1301 USA
++ */
++
++#include <common.h>
++#include <config.h>
++#include <command.h>
++#include <asm/blackfin.h>
++#include <asm/io.h>
++#include <linux/etherdevice.h>
++
++#define POST_WORD_ADDR 0xFF903FFC
++
++int checkboard(void)
++{
++ printf("Board: Metrologic Genesis Decode Board\n");
++ printf(" Support: http://www.metrologic.com/\n");
++ return 0;
++}
++
++#if defined(CONFIG_BFIN_IDE)
++
++void cf_outb(unsigned char val, volatile unsigned char *addr)
++{
++ *(addr) = val;
++ SSYNC();
++}
++
++unsigned char cf_inb(volatile unsigned char *addr)
++{
++ volatile unsigned char c;
++
++ c = *(addr);
++ SSYNC();
++
++ return c;
++}
++
++void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
++{
++ int i;
++
++ for (i = 0; i < words; i++)
++ *(sect_buf + i) = *(addr);
++ SSYNC();
++}
++
++void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
++{
++ int i;
++
++ for (i = 0; i < words; i++)
++ *(addr) = *(sect_buf + i);
++ SSYNC();
++}
++#endif /* CONFIG_BFIN_IDE */
++
++long int initdram(int board_type)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++#ifdef DEBUG
++ int brate;
++ char *tmp = getenv("baudrate");
++ brate = simple_strtoul(tmp, NULL, 16);
++ printf("Serial Port initialized with Baud rate = %x\n", brate);
++ printf("SDRAM attributes:\n");
++ printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
++ "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
++ 3, 3, 6, 2, 3);
++ printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
++ printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
++#endif
++ gd->bd->bi_memstart = CFG_SDRAM_BASE;
++ gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
++ return CFG_MAX_RAM_SIZE;
++}
++
++int board_get_enetaddr(uchar *mac_addr)
++{
++#ifdef CFG_NO_FLASH
++# define USE_MAC_IN_FLASH 0
++#else
++# define USE_MAC_IN_FLASH 1
++#endif
++ if (USE_MAC_IN_FLASH) {
++ /* we cram the MAC in the last flash sector */
++ uchar *board_mac_addr = (uchar *)0x203F0000;
++
++ if (is_valid_ether_addr(board_mac_addr)) {
++ memcpy(mac_addr, board_mac_addr, 6);
++ return 0;
++ }
++ }
++
++ puts("Warning: Generating 'random' MAC address\n");
++
++ /* make something up */
++ const char s[] = __DATE__;
++ size_t i;
++ u32 cycles;
++ for (i = 0; i < 6; ++i) {
++ asm("%0 = CYCLES;" : "=r" (cycles));
++ mac_addr[i] = cycles ^ s[i];
++ }
++ mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */
++ return 0;
++}
++
++void board_reset(void)
++{ /* FIXME: Alex Au: Don't know if we need to use this workaround... */
++ /* workaround for weak pull ups on ssel */
++ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
++ bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10);
++ bfin_write_PORTFIO_SET(PF10);
++ udelay(1);
++ }
++}
++
++
++
++#ifdef CONFIG_METROLOGIC_IO_INIT
++
++int metrologic_io_init(void)
++{
++ /* Port F:
++
++ 0 (out) <<< Host RS232 TX >>>
++ 1 (in) <<< Host RS232 RX >>>
++ 2 (out) <<< White LED (PWM) >>> [h] turns on LED
++ 3 (Out) <<< Blue LED (PWM) >>> [h] turns on LED
++ 4 (out) BEEP [l]
++ 5 (out) Target [l]
++ 6 (out) cam_sync [l]
++ 7 (out) Force On [l]
++ 8 (in) <<< PPI_VSYNC >>> [later, input]
++ 9 (in) <<< PPI_HSYNC >>> [later, input]
++ 10 (out) <<< SPI_CS >>>
++ 11 (out) <<< SPI_MOSI >>>
++ 12 (in) <<< SPI_MISO >>>
++ 13 (out) <<< SPI_CLOCK >>>
++ 14 (out) SPI_WP [h]
++ 15 (in) <<< PPI_Clock >>> [later, input]
++
++ */
++
++ *pPORTF_FER = PF0|PF1|PF10|PF11|PF12|PF13; /* PPI enabled in image device driver */
++ *pPORTFIO_DIR |= PF4|PF5|PF6|PF7|PF14;
++ *pPORTFIO_DIR &= ~(PF2|PF3|PF8|PF9|PF15);
++ *pPORTFIO_INEN &= ~(PF2|PF3|PF4|PF5|PF6|PF7|PF8|PF9|PF14|PF15);
++ *pPORTFIO &= ~(PF4|PF5|PF6|PF7);
++ *pPORTFIO |= PF14;
++
++ /* Port G:
++
++ 0 (in) <<< PPI_Data >>> [later, input]
++ 1 (in) <<< PPI_Data >>> [later, input]
++ 2 (in) <<< PPI_Data >>> [later, input]
++ 3 (in) <<< PPI_Data >>> [later, input]
++ 4 (in) <<< PPI_Data >>> [later, input]
++ 5 (in) <<< PPI_Data >>> [later, input]
++ 6 (in) <<< PPI_Data >>> [later, input]
++ 7 (in) <<< PPI_Data >>> [later, input]
++ 8 (out) DEC_KB_PASS_EN (Act. L) [l] (switch closed)
++ 9 (out) HOSTRTS ( Leave as input / output high until polarity is known )
++ *10 (out) LED_HIGH_V [h] (video low, snap-shot high) / (USB high)
++ *11 (out) RESET IF (active H) [l]
++ 12 (out) LED Voltage Enable [h]
++ 13 (in) USB_KBW_BF (0=KBW;1=USB)
++ 14 (in) BUF_PC_CLOCK_COL
++ 15 (in) BUF_BSY_OR_LPD
++
++ */
++
++ *pPORTG_FER = 0;
++ *pPORTGIO_DIR = PG8|PG9|PG10|PG11|PG12;
++ *pPORTGIO_INEN = PG13|PG14|PG15;
++ *pPORTGIO |= PG9|PG10|PG12;
++ *pPORTGIO &= ~(PG8|PG11);
++
++ /* Port H:
++
++ *0 (in) BUF_PC_DATA_COL
++ *1 (out) DEC_KB_CLOCK_BASE [l]*
++ *2 (out) DEC_KB_DATA_BASE [l]*
++ *3 (out) DEC_PC_CLOCK_BASE [l]*
++ *4 (out) DEC_PC_DATA_BASE [l]*
++ *5 (out) DEC_LT_PEN_BASE [l]*
++ 6 (in) IR_IN
++ *7 (out) DEC_REQ_UC [l]*
++ 8 (in) HOST CTS
++ 9 (in) BUTTON
++ *10 (in) BUF_SPI_REQ
++ *11 (in) BUF_EP_FULL_PAUSE
++ *12 (out) Ocillator En. (Active high) [h]
++ 13 (out) DC Mode (Active low) [h]
++ *14 (out) NEAR_SEL [l]
++ *15 (in) DEC_DTR_FULL
++
++ */
++
++ *pPORTH_FER = 0;
++ *pPORTHIO_DIR = PH1|PH2|PH3|PH4|PH5|PH7|PH12|PH13|PH14;
++ *pPORTHIO_INEN = ~(PH1|PH2|PH3|PH4|PH5|PH7|PH12|PH13|PH14);
++ *pPORTHIO |= PH12|PH13;
++ *pPORTHIO &= ~(PH1|PH2|PH3|PH4|PH5|PH7|PH14);
++
++ __builtin_bfin_ssync();
++
++#if defined(DEBUG_METRO_IO)
++ printf("start Configure_Interface_IO()\r\n");
++#endif
++ Configure_Interface_IO();
++#if defined(DEBUG_METRO_IO)
++ printf("done Configure_Interface_IO()\r\n");
++#endif
++
++ return 0;
++
++}
++
++#endif /* CONFIG_METROLOGIC_IO_INIT */
++#if defined(CONFIG_MISC_INIT_R)
++/* miscellaneous platform dependent initialisations */
++int misc_init_r(void)
++{
++#ifndef CFG_NO_FLASH
++ /* we use the last sector for the MAC address / POST DXE */
++ extern flash_info_t flash_info[];
++ flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
++#endif
++
++#if defined(CONFIG_BFIN_IDE)
++#if defined(CONFIG_BFIN_TRUE_IDE)
++ /* Enable ATASEL when in True IDE mode */
++ printf("Using CF True IDE Mode\n");
++ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
++ udelay(1000);
++#elif defined(CONFIG_BFIN_CF_IDE)
++ /* Disable ATASEL when we're in Common Memory Mode */
++ printf("Using CF Common Memory Mode\n");
++ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
++ udelay(1000);
++#elif defined(CONFIG_BFIN_HDD_IDE)
++ printf("Using HDD IDE Mode\n");
++#endif
++ ide_init();
++#endif /* CONFIG_BFIN_IDE */
++ return 0;
++}
++#endif /* CONFIG_MISC_INIT_R */
++
++#ifdef CONFIG_POST
++#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
++/* Using sw10-PF5 as the hotkey */
++int post_hotkeys_pressed(void)
++{
++ return 0;
++}
++#else
++/* Using sw10-PF5 as the hotkey */
++int post_hotkeys_pressed(void)
++{
++ int delay = 3;
++ int i;
++ unsigned short value;
++
++ *pPORTF_FER &= ~PF5;
++ *pPORTFIO_DIR &= ~PF5;
++ *pPORTFIO_INEN |= PF5;
++
++ printf("########Press SW10 to enter Memory POST########: %2d ", delay);
++ while (delay--) {
++ for (i = 0; i < 100; i++) {
++ value = *pPORTFIO & PF5;
++ if (value != 0) {
++ break;
++ }
++ udelay(10000);
++ }
++ printf("\b\b\b%2d ", delay);
++ }
++ printf("\b\b\b 0");
++ printf("\n");
++ if (value == 0)
++ return 0;
++ else {
++ printf("Hotkey has been pressed, Enter POST . . . . . .\n");
++ return 1;
++ }
++}
++#endif
++#endif
++
++#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
++void post_word_store(ulong a)
++{
++ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
++ *save_addr = a;
++}
++
++ulong post_word_load(void)
++{
++ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
++ return *save_addr;
++}
++#endif
++
++#ifdef CONFIG_POST
++int uart_post_test(int flags)
++{
++ return 0;
++}
++
++#define BLOCK_SIZE 0x10000
++#define VERIFY_ADDR 0x2000000
++extern int erase_block_flash(int);
++extern int write_data(long lStart, long lCount, uchar * pnData);
++int flash_post_test(int flags)
++{
++ unsigned short *pbuf, *temp;
++ int offset, n, i;
++ int value = 0;
++ int result = 0;
++ printf("\n");
++ pbuf = (unsigned short *)VERIFY_ADDR;
++ temp = pbuf;
++ for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
++ offset = (n - 7) * BLOCK_SIZE;
++ printf("--------Erase block:%2d..", n);
++ erase_block_flash(n);
++ printf("OK\r");
++ printf("--------Program block:%2d...", n);
++ write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
++ printf("OK\r");
++ printf("--------Verify block:%2d...", n);
++ for (i = 0; i < BLOCK_SIZE; i += 2) {
++ if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
++ *temp++) {
++ value = 1;
++ result = 1;
++ }
++ }
++ if (value)
++ printf("failed\n");
++ else
++ printf("OK %3d%%\r",
++ (int)(
++ (n + 1 -
++ FLASH_START_POST_BLOCK) *
++ 100 / (FLASH_END_POST_BLOCK -
++ FLASH_START_POST_BLOCK)));
++
++ temp = pbuf;
++ value = 0;
++ }
++ printf("\n");
++ if (result)
++ return -1;
++ else
++ return 0;
++}
++
++/****************************************************
++ * LED1 ---- PF6 LED2 ---- PF7 *
++ * LED3 ---- PF8 LED4 ---- PF9 *
++ * LED5 ---- PF10 LED6 ---- PF11 *
++ ****************************************************/
++int led_post_test(int flags)
++{
++ *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
++ *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
++ *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
++ *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
++ udelay(1000000);
++ printf("LED1 on");
++ *pPORTFIO |= PF6;
++ udelay(1000000);
++ printf("\b\b\b\b\b\b\b");
++ printf("LED2 on");
++ *pPORTFIO |= PF7;
++ udelay(1000000);
++ printf("\b\b\b\b\b\b\b");
++ printf("LED3 on");
++ *pPORTFIO |= PF8;
++ udelay(1000000);
++ printf("\b\b\b\b\b\b\b");
++ printf("LED4 on");
++ *pPORTFIO |= PF9;
++ udelay(1000000);
++ printf("\b\b\b\b\b\b\b");
++ printf("LED5 on");
++ *pPORTFIO |= PF10;
++ udelay(1000000);
++ printf("\b\b\b\b\b\b\b");
++ printf("lED6 on");
++ *pPORTFIO |= PF11;
++ printf("\b\b\b\b\b\b\b ");
++ return 0;
++}
++
++/************************************************
++ * SW10 ---- PF5 SW11 ---- PF4 *
++ * SW12 ---- PF3 SW13 ---- PF2 *
++ ************************************************/
++int button_post_test(int flags)
++{
++ int i, delay = 5;
++ unsigned short value = 0;
++ int result = 0;
++
++ *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
++ *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
++ *pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
++
++ printf("\n--------Press SW10: %2d ", delay);
++ while (delay--) {
++ for (i = 0; i < 100; i++) {
++ value = *pPORTFIO & PF5;
++ if (value != 0) {
++ break;
++ }
++ udelay(10000);
++ }
++ printf("\b\b\b%2d ", delay);
++ }
++ if (value != 0)
++ printf("\b\bOK");
++ else {
++ result = -1;
++ printf("\b\bfailed");
++ }
++
++ delay = 5;
++ printf("\n--------Press SW11: %2d ", delay);
++ while (delay--) {
++ for (i = 0; i < 100; i++) {
++ value = *pPORTFIO & PF4;
++ if (value != 0) {
++ break;
++ }
++ udelay(10000);
++ }
++ printf("\b\b\b%2d ", delay);
++ }
++ if (value != 0)
++ printf("\b\bOK");
++ else {
++ result = -1;
++ printf("\b\bfailed");
++ }
++
++ delay = 5;
++ printf("\n--------Press SW12: %2d ", delay);
++ while (delay--) {
++ for (i = 0; i < 100; i++) {
++ value = *pPORTFIO & PF3;
++ if (value != 0) {
++ break;
++ }
++ udelay(10000);
++ }
++ printf("\b\b\b%2d ", delay);
++ }
++ if (value != 0)
++ printf("\b\bOK");
++ else {
++ result = -1;
++ printf("\b\bfailed");
++ }
++
++ delay = 5;
++ printf("\n--------Press SW13: %2d ", delay);
++ while (delay--) {
++ for (i = 0; i < 100; i++) {
++ value = *pPORTFIO & PF2;
++ if (value != 0) {
++ break;
++ }
++ udelay(10000);
++ }
++ printf("\b\b\b%2d ", delay);
++ }
++ if (value != 0)
++ printf("\b\bOK");
++ else {
++ result = -1;
++ printf("\b\bfailed");
++ }
++ printf("\n");
++ return result;
++}
++#endif
+diff --git a/u-boot-1.1.6/board/IS4980/Makefile b/u-boot-1.1.6/board/IS4980/Makefile
+new file mode 100644
+index 0000000..4d03b2c
+--- /dev/null
++++ b/u-boot-1.1.6/board/IS4980/Makefile
+@@ -0,0 +1,59 @@
++#
++# U-boot - Makefile
++#
++# Copyright (c) 2005-2007 Analog Device Inc.
++#
++# (C) Copyright 2000-2006
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).a
++
++COBJS := $(BOARD).o post-memory.o spi_flash.o cmd_bf537led.o nand.o
++#COBJS := $(BOARD).o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
++
++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++SOBJS := $(addprefix $(obj),$(SOBJS))
++
++$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
++
++u-boot.lds: u-boot.lds.S
++ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
++ mv -f $@.tmp $@
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/u-boot-1.1.6/board/Orbit3/Makefile b/u-boot-1.1.6/board/Orbit3/Makefile
+new file mode 100644
+index 0000000..4d03b2c
+--- /dev/null
++++ b/u-boot-1.1.6/board/Orbit3/Makefile
+@@ -0,0 +1,59 @@
++#
++# U-boot - Makefile
++#
++# Copyright (c) 2005-2007 Analog Device Inc.
++#
++# (C) Copyright 2000-2006
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).a
++
++COBJS := $(BOARD).o post-memory.o spi_flash.o cmd_bf537led.o nand.o
++#COBJS := $(BOARD).o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
++
++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++SOBJS := $(addprefix $(obj),$(SOBJS))
++
++$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
++
++u-boot.lds: u-boot.lds.S
++ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
++ mv -f $@.tmp $@
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/u-boot-1.1.6/board/Orbit3/Orbit3.c b/u-boot-1.1.6/board/Orbit3/Orbit3.c
+new file mode 100644
+index 0000000..b40b20c
+--- /dev/null
++++ b/u-boot-1.1.6/board/Orbit3/Orbit3.c
+@@ -0,0 +1,516 @@
++/*
++ * U-boot - Orbit3.c
++ *
++ * Copyright (c) 2008 Metrologic Instruments Inc.
++ * Copyright (c) 2005-2007 Analog Devices Inc.
++ *
++ * (C) Copyright 2000-2004
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
++ * MA 02110-1301 USA
++ */
++
++#include <common.h>
++#include <config.h>
++#include <command.h>
++#include <asm/blackfin.h>
++#include <asm/io.h>
++#include <linux/etherdevice.h>
++
++#define POST_WORD_ADDR 0xFF903FFC
++
++int checkboard(void)
++{
++ printf("Board: Metrologic Genesis Decode Board\n");
++ printf(" Support: http://www.metrologic.com/\n");
++ return 0;
++}
++
++#if defined(CONFIG_BFIN_IDE)
++
++void cf_outb(unsigned char val, volatile unsigned char *addr)
++{
++ *(addr) = val;
++ SSYNC();
++}
++
++unsigned char cf_inb(volatile unsigned char *addr)
++{
++ volatile unsigned char c;
++
++ c = *(addr);
++ SSYNC();
++
++ return c;
++}
++
++void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
++{
++ int i;
++
++ for (i = 0; i < words; i++)
++ *(sect_buf + i) = *(addr);
++ SSYNC();
++}
++
++void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
++{
++ int i;
++
++ for (i = 0; i < words; i++)
++ *(addr) = *(sect_buf + i);
++ SSYNC();
++}
++#endif /* CONFIG_BFIN_IDE */
++
++long int initdram(int board_type)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++#ifdef DEBUG
++ int brate;
++ char *tmp = getenv("baudrate");
++ brate = simple_strtoul(tmp, NULL, 16);
++ printf("Serial Port initialized with Baud rate = %x\n", brate);
++ printf("SDRAM attributes:\n");
++ printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
++ "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
++ 3, 3, 6, 2, 3);
++ printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
++ printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
++#endif
++ gd->bd->bi_memstart = CFG_SDRAM_BASE;
++ gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
++ return CFG_MAX_RAM_SIZE;
++}
++
++int board_get_enetaddr(uchar *mac_addr)
++{
++#ifdef CFG_NO_FLASH
++# define USE_MAC_IN_FLASH 0
++#else
++# define USE_MAC_IN_FLASH 1
++#endif
++ if (USE_MAC_IN_FLASH) {
++ /* we cram the MAC in the last flash sector */
++ uchar *board_mac_addr = (uchar *)0x203F0000;
++
++ if (is_valid_ether_addr(board_mac_addr)) {
++ memcpy(mac_addr, board_mac_addr, 6);
++ return 0;
++ }
++ }
++
++ puts("Warning: Generating 'random' MAC address\n");
++
++ /* make something up */
++ const char s[] = __DATE__;
++ size_t i;
++ u32 cycles;
++ for (i = 0; i < 6; ++i) {
++ asm("%0 = CYCLES;" : "=r" (cycles));
++ mac_addr[i] = cycles ^ s[i];
++ }
++ mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */
++ return 0;
++}
++
++void board_reset(void)
++{ /* FIXME: Alex Au: Don't know if we need to use this workaround... */
++ /* workaround for weak pull ups on ssel */
++ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
++ bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10);
++ bfin_write_PORTFIO_SET(PF10);
++ udelay(1);
++ }
++}
++
++
++
++#ifdef CONFIG_METROLOGIC_IO_INIT
++
++int metrologic_io_init(void)
++{
++ /* Port F:
++
++ 0 (out) <<< Host RS232 TX >>>
++ 1 (in) <<< Host RS232 RX >>>
++ 2 (out) <<< White LED (PWM) >>> [l]
++ 3 (Out) <<< Blue LED (PWM) >>> [l]
++ 4 (out) BEEP [l]
++ 5 (out) Target [l]
++ 6 (out) cam_sync [l]
++ 7 (out) Force On [l]
++ 8 (in) <<< PPI_VSYNC >>> [later, input]
++ 9 (in) <<< PPI_HSYNC >>> [later, input]
++ 10 (out) <<< SPI_CS >>>
++ 11 (out) <<< SPI_MOSI >>>
++ 12 (in) <<< SPI_MISO >>>
++ 13 (out) <<< SPI_CLOCK >>>
++ 14 (out) SPI_WP [h]
++ 15 (in) <<< PPI_Clock >>> [later, input]
++
++ */
++
++ *pPORTF_FER = PF0|PF1|PF10|PF11|PF12|PF13; /* PPI enabled in image device driver */
++ *pPORTFIO_DIR |= PF4|PF5|PF6|PF7|PF14;
++ *pPORTFIO_DIR &= ~(PF2|PF3|PF8|PF9|PF15);
++ *pPORTFIO_INEN &= ~(PF2|PF3|PF4|PF5|PF6|PF7|PF8|PF9|PF14|PF15);
++ *pPORTFIO &= ~(PF4|PF5|PF6|PF7);
++ *pPORTFIO |= PF14;
++
++ /* Port G:
++
++ 0 (in) <<< PPI_Data >>> [later, input]
++ 1 (in) <<< PPI_Data >>> [later, input]
++ 2 (in) <<< PPI_Data >>> [later, input]
++ 3 (in) <<< PPI_Data >>> [later, input]
++ 4 (in) <<< PPI_Data >>> [later, input]
++ 5 (in) <<< PPI_Data >>> [later, input]
++ 6 (in) <<< PPI_Data >>> [later, input]
++ 7 (in) <<< PPI_Data >>> [later, input]
++ *8 (out) DEC_KB_PASS_EN(N) [h]
++ 9 (out) HOSTRTS ( Leave as input / output high until polarity is known )
++ *10 (out) LED_HIGH_V [h] (video low, snap-shot high) / (USB high)
++ *11 (out) RESET IF (active H) [l]
++ 12 (out) LED Voltage Enable [h]
++ 13 (in) Spare ? Yellow LED ?
++ 14 (out) BUF_PC_DATA_COL [h]
++ 15 (in) IF_BUSY_LT_PEN_DATA
++
++ */
++
++ *pPORTG_FER = 0;
++ *pPORTGIO_DIR = PG8|PG9|PG10|PG11|PG12|PG14;
++ *pPORTGIO_INEN = PG15;
++ *pPORTGIO |= PG8|PG9|PG10|PG12|PG14;
++ *pPORTGIO &= ~(PG11);
++
++ /* Port H:
++
++ *0 (in) BUF_PC_DATA_COL
++ *1 (out) DEC_KB_CLOCK_BASE [l]*
++ *2 (out) DEC_KB_DATA_BASE [l]*
++ *3 (out) DEC_PC_CLOCK_BASE [l]*
++ *4 (out) DEC_PC_DATA_BASE [l]*
++ *5 (out) DEC_LT_PEN_BASE [l]*
++ 6 (in) IR_IN
++ *7 (out) DEC_REQ_UC [l]*
++ 8 (in) HOST CTS
++ 9 (in) BUTTON
++ *10 (in) BUF_SPI_REQ
++ *11 (in) BUF_EP_FULL_PAUSE
++ *12 (out) Ocillator En. (Active high) [h]
++ 13 (out) DC Mode (Active low) [h]
++ *14 (out) NEAR_SEL [l]
++ *15 (in) DEC_DTR_FULL
++
++ */
++
++ *pPORTH_FER = 0;
++ *pPORTHIO_DIR = PH1|PH2|PH3|PH4|PH5|PH7|PH12|PH13|PH14;
++ *pPORTHIO_INEN = ~(PH1|PH2|PH3|PH4|PH5|PH7|PH12|PH13|PH14);
++ *pPORTHIO |= PH12|PH13;
++ *pPORTHIO &= ~(PH1|PH2|PH3|PH4|PH5|PH7|PH14);
++
++ __builtin_bfin_ssync();
++
++#if defined(DEBUG_METRO_IO)
++ printf("start Configure_Interface_IO()\r\n");
++#endif
++ Configure_Interface_IO();
++#if defined(DEBUG_METRO_IO)
++ printf("done Configure_Interface_IO()\r\n");
++#endif
++
++ return 0;
++
++}
++
++#endif /* CONFIG_METROLOGIC_IO_INIT */
++#if defined(CONFIG_MISC_INIT_R)
++/* miscellaneous platform dependent initialisations */
++int misc_init_r(void)
++{
++#ifndef CFG_NO_FLASH
++ /* we use the last sector for the MAC address / POST DXE */
++ extern flash_info_t flash_info[];
++ flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
++#endif
++
++#if defined(CONFIG_BFIN_IDE)
++#if defined(CONFIG_BFIN_TRUE_IDE)
++ /* Enable ATASEL when in True IDE mode */
++ printf("Using CF True IDE Mode\n");
++ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
++ udelay(1000);
++#elif defined(CONFIG_BFIN_CF_IDE)
++ /* Disable ATASEL when we're in Common Memory Mode */
++ printf("Using CF Common Memory Mode\n");
++ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
++ udelay(1000);
++#elif defined(CONFIG_BFIN_HDD_IDE)
++ printf("Using HDD IDE Mode\n");
++#endif
++ ide_init();
++#endif /* CONFIG_BFIN_IDE */
++ return 0;
++}
++#endif /* CONFIG_MISC_INIT_R */
++
++#ifdef CONFIG_POST
++#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
++/* Using sw10-PF5 as the hotkey */
++int post_hotkeys_pressed(void)
++{
++ return 0;
++}
++#else
++/* Using sw10-PF5 as the hotkey */
++int post_hotkeys_pressed(void)
++{
++ int delay = 3;
++ int i;
++ unsigned short value;
++
++ *pPORTF_FER &= ~PF5;
++ *pPORTFIO_DIR &= ~PF5;
++ *pPORTFIO_INEN |= PF5;
++
++ printf("########Press SW10 to enter Memory POST########: %2d ", delay);
++ while (delay--) {
++ for (i = 0; i < 100; i++) {
++ value = *pPORTFIO & PF5;
++ if (value != 0) {
++ break;
++ }
++ udelay(10000);
++ }
++ printf("\b\b\b%2d ", delay);
++ }
++ printf("\b\b\b 0");
++ printf("\n");
++ if (value == 0)
++ return 0;
++ else {
++ printf("Hotkey has been pressed, Enter POST . . . . . .\n");
++ return 1;
++ }
++}
++#endif
++#endif
++
++#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
++void post_word_store(ulong a)
++{
++ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
++ *save_addr = a;
++}
++
++ulong post_word_load(void)
++{
++ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
++ return *save_addr;
++}
++#endif
++
++#ifdef CONFIG_POST
++int uart_post_test(int flags)
++{
++ return 0;
++}
++
++#define BLOCK_SIZE 0x10000
++#define VERIFY_ADDR 0x2000000
++extern int erase_block_flash(int);
++extern int write_data(long lStart, long lCount, uchar * pnData);
++int flash_post_test(int flags)
++{
++ unsigned short *pbuf, *temp;
++ int offset, n, i;
++ int value = 0;
++ int result = 0;
++ printf("\n");
++ pbuf = (unsigned short *)VERIFY_ADDR;
++ temp = pbuf;
++ for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
++ offset = (n - 7) * BLOCK_SIZE;
++ printf("--------Erase block:%2d..", n);
++ erase_block_flash(n);
++ printf("OK\r");
++ printf("--------Program block:%2d...", n);
++ write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
++ printf("OK\r");
++ printf("--------Verify block:%2d...", n);
++ for (i = 0; i < BLOCK_SIZE; i += 2) {
++ if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
++ *temp++) {
++ value = 1;
++ result = 1;
++ }
++ }
++ if (value)
++ printf("failed\n");
++ else
++ printf("OK %3d%%\r",
++ (int)(
++ (n + 1 -
++ FLASH_START_POST_BLOCK) *
++ 100 / (FLASH_END_POST_BLOCK -
++ FLASH_START_POST_BLOCK)));
++
++ temp = pbuf;
++ value = 0;
++ }
++ printf("\n");
++ if (result)
++ return -1;
++ else
++ return 0;
++}
++
++/****************************************************
++ * LED1 ---- PF6 LED2 ---- PF7 *
++ * LED3 ---- PF8 LED4 ---- PF9 *
++ * LED5 ---- PF10 LED6 ---- PF11 *
++ ****************************************************/
++int led_post_test(int flags)
++{
++ *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
++ *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
++ *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
++ *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
++ udelay(1000000);
++ printf("LED1 on");
++ *pPORTFIO |= PF6;
++ udelay(1000000);
++ printf("\b\b\b\b\b\b\b");
++ printf("LED2 on");
++ *pPORTFIO |= PF7;
++ udelay(1000000);
++ printf("\b\b\b\b\b\b\b");
++ printf("LED3 on");
++ *pPORTFIO |= PF8;
++ udelay(1000000);
++ printf("\b\b\b\b\b\b\b");
++ printf("LED4 on");
++ *pPORTFIO |= PF9;
++ udelay(1000000);
++ printf("\b\b\b\b\b\b\b");
++ printf("LED5 on");
++ *pPORTFIO |= PF10;
++ udelay(1000000);
++ printf("\b\b\b\b\b\b\b");
++ printf("lED6 on");
++ *pPORTFIO |= PF11;
++ printf("\b\b\b\b\b\b\b ");
++ return 0;
++}
++
++/************************************************
++ * SW10 ---- PF5 SW11 ---- PF4 *
++ * SW12 ---- PF3 SW13 ---- PF2 *
++ ************************************************/
++int button_post_test(int flags)
++{
++ int i, delay = 5;
++ unsigned short value = 0;
++ int result = 0;
++
++ *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
++ *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
++ *pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
++
++ printf("\n--------Press SW10: %2d ", delay);
++ while (delay--) {
++ for (i = 0; i < 100; i++) {
++ value = *pPORTFIO & PF5;
++ if (value != 0) {
++ break;
++ }
++ udelay(10000);
++ }
++ printf("\b\b\b%2d ", delay);
++ }
++ if (value != 0)
++ printf("\b\bOK");
++ else {
++ result = -1;
++ printf("\b\bfailed");
++ }
++
++ delay = 5;
++ printf("\n--------Press SW11: %2d ", delay);
++ while (delay--) {
++ for (i = 0; i < 100; i++) {
++ value = *pPORTFIO & PF4;
++ if (value != 0) {
++ break;
++ }
++ udelay(10000);
++ }
++ printf("\b\b\b%2d ", delay);
++ }
++ if (value != 0)
++ printf("\b\bOK");
++ else {
++ result = -1;
++ printf("\b\bfailed");
++ }
++
++ delay = 5;
++ printf("\n--------Press SW12: %2d ", delay);
++ while (delay--) {
++ for (i = 0; i < 100; i++) {
++ value = *pPORTFIO & PF3;
++ if (value != 0) {
++ break;
++ }
++ udelay(10000);
++ }
++ printf("\b\b\b%2d ", delay);
++ }
++ if (value != 0)
++ printf("\b\bOK");
++ else {
++ result = -1;
++ printf("\b\bfailed");
++ }
++
++ delay = 5;
++ printf("\n--------Press SW13: %2d ", delay);
++ while (delay--) {
++ for (i = 0; i < 100; i++) {
++ value = *pPORTFIO & PF2;
++ if (value != 0) {
++ break;
++ }
++ udelay(10000);
++ }
++ printf("\b\b\b%2d ", delay);
++ }
++ if (value != 0)
++ printf("\b\bOK");
++ else {
++ result = -1;
++ printf("\b\bfailed");
++ }
++ printf("\n");
++ return result;
++}
++#endif
+diff --git a/u-boot-1.1.6/board/VuQuest2D/Makefile b/u-boot-1.1.6/board/VuQuest2D/Makefile
+new file mode 100644
+index 0000000..1a924d9
+--- /dev/null
++++ b/u-boot-1.1.6/board/VuQuest2D/Makefile
+@@ -0,0 +1,59 @@
++#
++# U-boot - Makefile
++#
++# Copyright (c) 2005-2008 Analog Device Inc.
++#
++# (C) Copyright 2000-2006
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).a
++
++#COBJS := $(BOARD).o spi_flash.o video.o
++COBJS := $(BOARD).o spi.o video.o
++
++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++SOBJS := $(addprefix $(obj),$(SOBJS))
++
++$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
++
++u-boot.lds: u-boot.lds.S
++ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
++ mv -f $@.tmp $@
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.c b/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.c
+new file mode 100644
+index 0000000..04647d7
+--- /dev/null
++++ b/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.c
+@@ -0,0 +1,418 @@
++/*
++ * U-boot - stamp.c STAMP board specific routines
++ *
++ * Copyright (c) 2005-2007 Analog Devices Inc.
++ *
++ * (C) Copyright 2000-2004
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
++ * MA 02110-1301 USA
++ */
++
++#include <common.h>
++#include <asm/blackfin.h>
++#include <asm/io.h>
++#include <asm/mach-common/bits/ebiu.h>
++#include "VuQuest2D.h"
++#include "Metrologic_Hardware.h"
++
++#define STATUS_LED_OFF 0
++#define STATUS_LED_ON 1
++
++#ifdef CONFIG_SHOW_BOOT_PROGRESS
++# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
++#else
++# define SHOW_BOOT_PROGRESS(arg)
++#endif
++
++#ifdef CONFIG_METROLOGIC_IO_INIT
++void set_VQ_default_io(void);
++#endif
++
++extern void Configure_Interface_IO(void);
++extern void Configure_RTS_Pin(void);
++extern int get_pfx_level(int pf_num);
++
++#if (CONFIG_METROLOGIC_VQ2D_REV > 1)
++
++int
++Read_VQ_AtoD(void)
++{
++#define VQ2D_RTS_PIN 6
++ int fio_dir = *pFIO_DIR;
++ int fio_ilen = *pFIO_INEN;
++ int pf6_level;
++
++ *pFIO_DIR &= ~(PF6);
++ *pFIO_INEN |= PF6;
++
++ pf6_level = get_pfx_level(VQ2D_RTS_PIN);
++
++ *pFIO_DIR = fio_dir;
++ *pFIO_INEN = fio_ilen;
++
++ if (pf6_level == 0)
++ { /* RS232 */
++ return (241 + 255) / 2;
++ }
++ else
++ { /* USB */
++ return (113 + 127) / 2;
++ }
++}
++
++void
++Configure_VQ2D_Interface_IO(int interface_board)
++{
++ if (interface_board == RS232_BOARD)
++ {
++#define PWR_DWN_PIN 9
++#define PWR_ON_PIN 5
++ Configure_RTS_Pin();
++
++ *pFIO_DIR |= PF9;
++ *pFIO_INEN &= ~PF9;
++ *pFIO_FLAG_D |= PF5;
++ *pFIO_FLAG_D &= ~PF9; /* PWR_DWN will be turned off at img.ko */
++ }
++ else
++ { /* USB board */
++#define SLAVE_BUSY_PIN 9
++
++ *pFIO_DIR &= ~(PF9);
++ }
++
++ /* power down pin handled by silabs */
++}
++
++#endif /* #if (CONFIG_METROLOGIC_VQ2D_REV > 1) */
++
++int checkboard(void)
++{
++ printf("CPU: ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28);
++ printf("Board: Metrologic VuQuest2D decode board\n");
++ printf(" Support: http://www.metrologic.com/\n");
++ return 0;
++}
++
++long int initdram(int board_type)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++#ifdef DEBUG
++ printf("SDRAM attributes:\n");
++ printf
++ (" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
++ "CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11),
++ (SDRAM_tRAS >> 6), (SDRAM_tWR >> 19), (SDRAM_CL >> 2));
++ printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
++ printf("Bank size = %d MB\n", 128);
++#endif
++ gd->bd->bi_memstart = CFG_SDRAM_BASE;
++ gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
++ return (gd->bd->bi_memsize);
++}
++
++void swap_to(int device_id)
++{
++#ifdef CONFIG_METROLOGIC_IO_INIT
++ if (device_id == FLASH)
++ {
++ bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF2);
++ SSYNC();
++ bfin_write_FIO_FLAG_S(PF2);
++ SSYNC();
++ }
++#else
++ bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0);
++ SSYNC();
++ bfin_write_FIO_FLAG_C(PF1);
++ if (device_id == ETHERNET)
++ bfin_write_FIO_FLAG_S(PF0);
++ else if (device_id == FLASH)
++ bfin_write_FIO_FLAG_C(PF0);
++ else
++ printf("Unknown device to switch\n");
++ SSYNC();
++#endif
++}
++
++#if defined(CONFIG_MISC_INIT_R)
++/* miscellaneous platform dependent initialisations */
++int misc_init_r(void)
++{
++ int i;
++ int cf_stat = 0;
++
++ /* Check whether CF card is inserted */
++ *pFIO_EDGE = FIO_EDGE_CF_BITS;
++ *pFIO_POLAR = FIO_POLAR_CF_BITS;
++ for (i = 0; i < 0x300; i++)
++ asm("nop;");
++
++ if ((*pFIO_FLAG_S) & CF_STAT_BITS) {
++ cf_stat = 0;
++ } else {
++ cf_stat = 1;
++ }
++
++ *pFIO_EDGE = FIO_EDGE_BITS;
++ *pFIO_POLAR = FIO_POLAR_BITS;
++
++ if (cf_stat) {
++ printf("Booting from COMPACT flash\n");
++
++ for (i = 0; i < 0x1000; i++)
++ asm("nop;");
++ for (i = 0; i < 0x1000; i++)
++ asm("nop;");
++ for (i = 0; i < 0x1000; i++)
++ asm("nop;");
++
++ serial_setbrg();
++ ide_init();
++
++ setenv("bootargs", "");
++ setenv("bootcmd",
++ "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
++ } else {
++ printf("Booting from FLASH\n");
++ }
++ return 0;
++}
++#endif
++
++#ifdef CONFIG_STAMP_CF
++
++void cf_outb(unsigned char val, volatile unsigned char *addr)
++{
++ /*
++ * Set PF1 PF0 respectively to 0 1 to divert address
++ * to the expansion memory banks
++ */
++ *pFIO_FLAG_S = CF_PF0;
++ *pFIO_FLAG_C = CF_PF1;
++ SSYNC();
++
++ *(addr) = val;
++ SSYNC();
++
++ /* Setback PF1 PF0 to 0 0 to address external
++ * memory banks */
++ *(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0;
++ SSYNC();
++}
++
++unsigned char cf_inb(volatile unsigned char *addr)
++{
++ volatile unsigned char c;
++
++ *pFIO_FLAG_S = CF_PF0;
++ *pFIO_FLAG_C = CF_PF1;
++ SSYNC();
++
++ c = *(addr);
++ SSYNC();
++
++ *pFIO_FLAG_C = CF_PF1_PF0;
++ SSYNC();
++
++ return c;
++}
++
++void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
++{
++ int i;
++
++ *pFIO_FLAG_S = CF_PF0;
++ *pFIO_FLAG_C = CF_PF1;
++ SSYNC();
++
++ for (i = 0; i < words; i++) {
++ *(sect_buf + i) = *(addr);
++ SSYNC();
++ }
++
++ *pFIO_FLAG_C = CF_PF1_PF0;
++ SSYNC();
++}
++
++void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
++{
++ int i;
++
++ *pFIO_FLAG_S = CF_PF0;
++ *pFIO_FLAG_C = CF_PF1;
++ SSYNC();
++
++ for (i = 0; i < words; i++) {
++ *(addr) = *(sect_buf + i);
++ SSYNC();
++ }
++
++ *pFIO_FLAG_C = CF_PF1_PF0;
++ SSYNC();
++}
++#endif
++
++#ifdef CONFIG_METROLOGIC_IO_INIT
++
++void set_VQ_default_io(void)
++{
++ /* Port F:
++ 0 - (Out?) I2C Clock
++ 1 - (In?) I2C Data
++ 2 - (Out) SPI chip select
++ 3 - (In?) nWake / PPI_FS3
++ 4 - (Out) Target Pin
++ 5 - (Out) nGoodRead
++ 6 - (Out) RTS
++ 7 - (In) CTS
++ 8 - (Out) Minflash / IllumOn
++ 9 - (Out?) nPowerDown (RS232) / (In) Slave_Busy (USB)
++ 10 - (Out) CamSync
++ 11 - (In) nTrigger (Input to decode)
++
++ 12 - (In) PPI Data
++ 13 - (In) PPI Data
++ 14 - (In) PPI Data
++ 15 - (In) PPI Data
++
++ */
++
++
++
++
++
++#if (CONFIG_METROLOGIC_VQ2D_REV > 1)
++ *pFIO_DIR |= PF0|PF1|PF2|PF4|PF5|PF8|PF10;
++ *pFIO_DIR &= ~(PF3 | PF6|PF9 | PF12|PF13|PF14|PF15);
++#else
++ *pFIO_DIR |= PF0|PF1|PF2|PF4|PF5|PF8|PF9|PF10;
++ *pFIO_DIR &= ~(PF3 | PF12|PF13|PF14|PF15);
++#endif
++
++ *pFIO_EDGE = 0;
++
++
++
++#if (CONFIG_METROLOGIC_VQ2D_REV > 1)
++ *pFIO_INEN &= ~(PF0|PF1|PF2 | PF4|PF5|PF8|PF10 | PF12|PF13|PF14|PF15);
++ *pFIO_INEN |= PF3 | PF6 | PF7 | PF9 | PF11;
++#else
++ *pFIO_INEN &= ~(PF0|PF1|PF2 | PF4|PF5|PF6|PF8|PF9|PF10);
++ *pFIO_INEN |= PF3 | PF7 | PF11;
++#endif
++
++
++
++
++
++
++
++
++
++
++ *pFIO_POLAR = 0;
++ *pFIO_FLAG_D &= ~(PF0|PF1 | PF4|PF8|PF10);
++#if (CONFIG_METROLOGIC_VQ2D_REV > 1)
++ *pFIO_FLAG_D |= PF2;
++ *pFIO_FLAG_D &= ~PF5;
++#else
++ *pFIO_FLAG_D |= PF2|PF5|PF9;
++#endif
++
++
++ __builtin_bfin_ssync();
++}
++
++int metrologic_io_init(void)
++{
++ set_VQ_default_io();
++
++ Configure_Interface_IO();
++
++
++
++ return 0;
++
++
++
++}
++
++#endif /* CONFIG_METROLOGIC_IO_INIT */
++
++void stamp_led_set(int LED1, int LED2, int LED3)
++{
++#ifndef CONFIG_METROLOGIC_IO_INIT
++ *pFIO_INEN &= ~(PF2 | PF3 | PF4);
++ *pFIO_DIR |= (PF2 | PF3 | PF4);
++
++ if (LED1 == STATUS_LED_OFF)
++ *pFIO_FLAG_S = PF2;
++ else
++ *pFIO_FLAG_C = PF2;
++ if (LED2 == STATUS_LED_OFF)
++ *pFIO_FLAG_S = PF3;
++ else
++ *pFIO_FLAG_C = PF3;
++ if (LED3 == STATUS_LED_OFF)
++ *pFIO_FLAG_S = PF4;
++ else
++ *pFIO_FLAG_C = PF4;
++ SSYNC();
++#endif
++}
++
++void show_boot_progress(int status)
++{
++ switch (status) {
++ case 1:
++ stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
++ break;
++ case 2:
++ stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
++ break;
++ case 3:
++ stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
++ break;
++ case 4:
++ stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
++ break;
++ case 5:
++ case 6:
++ stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
++ break;
++ case 7:
++ case 8:
++ stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
++ break;
++ case 9:
++ case 10:
++ case 11:
++ case 12:
++ case 13:
++ case 14:
++ case 15:
++ stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_OFF);
++ break;
++ default:
++ stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
++ break;
++ }
++}
+diff --git a/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.h b/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.h
+new file mode 100644
+index 0000000..96f7aa7
+--- /dev/null
++++ b/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.h
+@@ -0,0 +1,53 @@
++/*
++ * U-boot - stamp.h
++ *
++ * Copyright (c) 2005-2007 Analog Devices Inc.
++ *
++ * (C) Copyright 2000-2004
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
++ * MA 02110-1301 USA
++ */
++
++#ifndef __VUQUEST2D_H__
++#define __VUQUEST2D_H__
++
++extern void init_Flags(void);
++
++extern volatile unsigned long *ambctl0;
++extern volatile unsigned long *ambctl1;
++extern volatile unsigned long *amgctl;
++
++/* Definitions used in Compact Flash Boot support */
++#define FIO_EDGE_CF_BITS 0x0000
++#define FIO_POLAR_CF_BITS 0x0000
++#define FIO_EDGE_BITS 0x1E0
++#define FIO_POLAR_BITS 0x160
++
++/* Compact flash status bits in status register */
++#define CF_STAT_BITS 0x00000060
++
++/* CF Flags used to switch between expansion and external
++ * memory banks
++ */
++#define CF_PF0 0x0001
++#define CF_PF1 0x0002
++#define CF_PF1_PF0 0x0003
++
++#endif
+diff --git a/u-boot-1.1.6/board/VuQuest2D/config.mk b/u-boot-1.1.6/board/VuQuest2D/config.mk
+new file mode 100644
+index 0000000..2afee57
+--- /dev/null
++++ b/u-boot-1.1.6/board/VuQuest2D/config.mk
+@@ -0,0 +1,15 @@
++#
++# Copyright (c) 2005-2008 Analog Device Inc.
++#
++# (C) Copyright 2001
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# Licensed under the GPL-2 or later.
++#
++
++# This is not actually used for Blackfin boards so do not change it
++#TEXT_BASE = do-not-use-me
++
++# Set some default LDR flags based on boot mode.
++LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
++LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
+diff --git a/u-boot-1.1.6/board/VuQuest2D/spi.c b/u-boot-1.1.6/board/VuQuest2D/spi.c
+new file mode 100644
+index 0000000..908d4e1
+--- /dev/null
++++ b/u-boot-1.1.6/board/VuQuest2D/spi.c
+@@ -0,0 +1,533 @@
++/****************************************************************************
++ * SPI flash driver for M25P64
++ ****************************************************************************/
++#include <common.h>
++#include <linux/ctype.h>
++#include <asm/mach-common/bits/spi.h>
++
++#if defined(CONFIG_SPI)
++
++//Application definitions
++
++#define NUM_SECTORS 128 /* number of sectors */
++#define SECTOR_SIZE 0x10000
++#define NOP_NUM 1000
++
++#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL) //Settings to the SPI_CTL
++#define TIMOD01 (0x01) //stes the SPI to work with core instructions
++
++//Flash commands
++#define SPI_WREN (0x06) //Set Write Enable Latch
++#define SPI_WRDI (0x04) //Reset Write Enable Latch
++#define SPI_RDSR (0x05) //Read Status Register
++#define SPI_WRSR (0x01) //Write Status Register
++#define SPI_READ (0x03) //Read data from memory
++#define SPI_FAST_READ (0x0B) //Read data from memory
++#define SPI_PP (0x02) //Program Data into memory
++#define SPI_SE (0xD8) //Erase one sector in memory
++#define SPI_BE (0xC7) //Erase all memory
++#define WIP (0x1) //Check the write in progress bit of the SPI status register
++#define WEL (0x2) //Check the write enable bit of the SPI status register
++
++#define TIMEOUT 350000000
++
++typedef enum
++{
++ NO_ERR,
++ POLL_TIMEOUT,
++ INVALID_SECTOR,
++ INVALID_BLOCK,
++}ERROR_CODE;
++
++
++void spi_init_f (void);
++void spi_init_r (void);
++ssize_t spi_read (uchar *, int, uchar *, int);
++ssize_t spi_write (uchar *, int, uchar *, int);
++
++char ReadStatusRegister(void);
++void Wait_For_SPIF(void);
++void SetupSPI( const int spi_setting );
++void SPI_OFF(void);
++void SendSingleCommand( const int iCommand );
++
++ERROR_CODE GetSectorNumber( unsigned long ulOffset, int *pnSector );
++ERROR_CODE EraseBlock( int nBlock );
++ERROR_CODE ReadData( unsigned long ulStart, long lCount,int *pnData );
++ERROR_CODE WriteData( unsigned long ulStart, long lCount, int *pnData );
++ERROR_CODE Wait_For_Status( char Statusbit );
++ERROR_CODE Wait_For_WEL(void);
++
++/* -------------------
++ * Variables
++ * ------------------- */
++
++/* **************************************************************************
++ *
++ * Function: spi_init_f
++ *
++ * Description: Init SPI-Controller (ROM part)
++ *
++ * return: ---
++ *
++ * *********************************************************************** */
++void spi_init_f (void)
++{
++}
++
++/* **************************************************************************
++ *
++ * Function: spi_init_r
++ *
++ * Description: Init SPI-Controller (RAM part) -
++ * The malloc engine is ready and we can move our buffers to
++ * normal RAM
++ *
++ * return: ---
++ *
++ * *********************************************************************** */
++void spi_init_r (void)
++{
++ return;
++}
++
++/****************************************************************************
++ * Function: spi_write
++ **************************************************************************** */
++ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
++{
++ unsigned long offset;
++ int start_block,end_block;
++ int start_byte,end_byte;
++ ERROR_CODE result = NO_ERR;
++ uchar temp[SECTOR_SIZE];
++ int i,num;
++
++ offset = addr[0]<<16 | addr[1] <<8 | addr[2];
++ /* Get the start block number */
++ GetSectorNumber(offset, &start_block);
++ /* Get the end block number */
++ GetSectorNumber(offset + len, &end_block);
++
++ for(num = start_block;num <= end_block;num ++){
++ ReadData(num*SECTOR_SIZE,SECTOR_SIZE,(int *)temp);
++ start_byte = num*SECTOR_SIZE;
++ end_byte = (num+1) * SECTOR_SIZE -1;
++ if(start_byte < offset) start_byte = offset;
++ if( end_byte > (offset+len)) end_byte = (offset+len-1);
++ for(i=start_byte;i<=end_byte;i++)
++ temp[i-num*SECTOR_SIZE] = buffer[i - offset];
++ EraseBlock(num);
++ result = WriteData(num*SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
++ if(result != NO_ERR)
++ return 0;
++ printf(".");
++ }
++ return len;
++}
++
++/****************************************************************************
++ * Function: spi_read
++ **************************************************************************** */
++ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
++{
++ unsigned long offset;
++ offset = addr[0]<<16 | addr[1] <<8 | addr[2];
++ ReadData ( offset, len, (int *)buffer );
++ return len;
++}
++
++void SendSingleCommand( const int iCommand )
++{
++ unsigned short dummy;
++
++ /*turns on the SPI in single write mode*/
++ SetupSPI( (COMMON_SPI_SETTINGS|TIMOD01) );
++
++ /*sends the actual command to the SPI TX register*/
++ *pSPI_TDBR = iCommand;
++ __builtin_bfin_ssync();
++
++ /*The SPI status register will be polled to check the SPIF bit*/
++ Wait_For_SPIF();
++
++ dummy = *pSPI_RDBR;
++
++ /*The SPI will be turned off*/
++ SPI_OFF();
++
++}
++
++void SetupSPI( const int spi_setting )
++{
++
++ if(icache_status()||dcache_status())
++ udelay(CONFIG_CCLK_HZ/50000000);
++ /*sets up the PF2 to be the slave select of the SPI */
++ *pSPI_FLG = 0xFB04;
++ *pSPI_BAUD = CONFIG_SPI_BAUD;
++ *pSPI_CTL = spi_setting;
++ __builtin_bfin_ssync();
++}
++
++void SPI_OFF(void)
++{
++
++ *pSPI_CTL = 0x0400; /* disable SPI*/
++ *pSPI_FLG = 0;
++ *pSPI_BAUD = 0;
++ __builtin_bfin_ssync();
++ udelay(CONFIG_CCLK_HZ/50000000);
++
++}
++
++void Wait_For_SPIF(void)
++{
++ unsigned short dummyread;
++ while( (*pSPI_STAT&TXS));
++ while(!(*pSPI_STAT&SPIF));
++ while(!(*pSPI_STAT&RXS));
++ dummyread = *pSPI_RDBR; // Read dummy to empty the receive register
++
++}
++
++ERROR_CODE Wait_For_WEL(void)
++{
++ int i;
++ char status_register = 0;
++ ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash*/
++
++ for(i = 0; i < TIMEOUT; i++)
++ {
++ status_register = ReadStatusRegister();
++ if( (status_register & WEL) )
++ {
++ ErrorCode = NO_ERR; /* tells us if there was an error erasing flash*/
++ break;
++ }
++ ErrorCode = POLL_TIMEOUT; /* Time out error*/
++ };
++
++ return ErrorCode;
++}
++
++ERROR_CODE Wait_For_Status( char Statusbit )
++{
++ int i;
++ char status_register = 0xFF;
++ ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
++
++ for(i = 0; i < TIMEOUT; i++)
++ {
++ status_register = ReadStatusRegister();
++ if( !(status_register & Statusbit) )
++ {
++ ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
++ break;
++ }
++ ErrorCode = POLL_TIMEOUT; /* Time out error */
++ };
++
++
++ return ErrorCode;
++}
++
++
++char ReadStatusRegister(void)
++{
++ char status_register = 0;
++
++ SetupSPI( (COMMON_SPI_SETTINGS|TIMOD01) ); /* Turn on the SPI */
++
++ *pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */
++ __builtin_bfin_ssync();
++ Wait_For_SPIF(); /*wait until the instruction has been sent*/
++ *pSPI_TDBR = 0; /*send dummy to receive the status register*/
++ __builtin_bfin_ssync();
++ Wait_For_SPIF(); /*wait until the data has been sent*/
++ status_register = *pSPI_RDBR; /*read the status register*/
++
++ SPI_OFF(); /* Turn off the SPI */
++
++ return status_register;
++}
++
++ERROR_CODE GetSectorNumber( unsigned long ulOffset, int *pnSector )
++{
++ int nSector = 0;
++ ERROR_CODE ErrorCode = NO_ERR;
++
++ if(ulOffset > (NUM_SECTORS*0x10000 -1)){
++ ErrorCode = INVALID_SECTOR;
++ return ErrorCode;
++ }
++
++ nSector = (int)ulOffset/0x10000;
++ *pnSector = nSector;
++
++ // ok
++ return ErrorCode;
++}
++
++ERROR_CODE EraseBlock( int nBlock )
++{
++ unsigned long ulSectorOff = 0x0, ShiftValue;
++ ERROR_CODE ErrorCode = NO_ERR;
++
++
++ // if the block is invalid just return
++ if ( (nBlock < 0) || (nBlock > NUM_SECTORS) )
++ {
++ ErrorCode = INVALID_BLOCK; // tells us if there was an error erasing flash
++ return ErrorCode;
++ }
++
++ // figure out the offset of the block in flash
++ if ( (nBlock >= 0) && (nBlock < NUM_SECTORS) )
++ {
++ ulSectorOff = (nBlock * SECTOR_SIZE);
++
++ }
++ else
++ {
++ ErrorCode = INVALID_BLOCK; // tells us if there was an error erasing flash
++ return ErrorCode;
++ }
++
++ // A write enable instruction must previously have been executed
++ SendSingleCommand(SPI_WREN);
++
++ //The status register will be polled to check the write enable latch "WREN"
++ ErrorCode = Wait_For_WEL();
++
++ if( POLL_TIMEOUT == ErrorCode )
++ {
++ printf("SPI Erase block error\n");
++ return ErrorCode;
++ }
++ else
++
++
++ //Turn on the SPI to send single commands
++ SetupSPI( (COMMON_SPI_SETTINGS|TIMOD01) );
++
++ // Send the erase block command to the flash followed by the 24 address
++ // to point to the start of a sector.
++ *pSPI_TDBR = SPI_SE;
++ __builtin_bfin_ssync();
++ Wait_For_SPIF();
++ ShiftValue = (ulSectorOff >> 16); // Send the highest byte of the 24 bit address at first
++ *pSPI_TDBR = ShiftValue;
++ __builtin_bfin_ssync();
++ Wait_For_SPIF(); // Wait until the instruction has been sent
++ ShiftValue = (ulSectorOff >> 8); // Send the middle byte of the 24 bit address at second
++ *pSPI_TDBR = ShiftValue;
++ __builtin_bfin_ssync();
++ Wait_For_SPIF(); // Wait until the instruction has been sent
++ *pSPI_TDBR = ulSectorOff; // Send the lowest byte of the 24 bit address finally
++ __builtin_bfin_ssync();
++ Wait_For_SPIF(); // Wait until the instruction has been sent
++
++ //Turns off the SPI
++ SPI_OFF();
++
++ // Poll the status register to check the Write in Progress bit
++ // Sector erase takes time
++ ErrorCode = Wait_For_Status(WIP);
++
++ // block erase should be complete
++ return ErrorCode;
++}
++
++/*****************************************************************************
++* ERROR_CODE ReadData()
++*
++* Read a value from flash for verify purpose
++*
++* Inputs: unsigned long ulStart - holds the SPI start address
++* int pnData - pointer to store value read from flash
++* long lCount - number of elements to read
++***************************************************************************** */
++ERROR_CODE ReadData( unsigned long ulStart, long lCount,int *pnData )
++{
++ unsigned long ShiftValue;
++ char *cnData,ReadValue;
++ int i;
++
++ cnData = (char *)pnData; /* Pointer cast to be able to increment byte wise */
++
++ // Start SPI interface
++ SetupSPI( (COMMON_SPI_SETTINGS|TIMOD01) );
++
++#ifdef CONFIG_SERIAL_BF537_USE_FAST_READ
++ *pSPI_TDBR = SPI_FAST_READ; // Send the read command to SPI device
++#else
++ *pSPI_TDBR = SPI_READ; // Send the read command to SPI device
++#endif
++ __builtin_bfin_ssync();
++ Wait_For_SPIF(); // Wait until the instruction has been sent
++ ShiftValue = (ulStart >> 16); // Send the highest byte of the 24 bit address at first
++ *pSPI_TDBR = ShiftValue; // Send the byte to the SPI device
++ __builtin_bfin_ssync();
++ Wait_For_SPIF(); // Wait until the instruction has been sent
++ ShiftValue = (ulStart >> 8); // Send the middle byte of the 24 bit address at second
++ *pSPI_TDBR = ShiftValue; // Send the byte to the SPI device
++ __builtin_bfin_ssync();
++ Wait_For_SPIF(); // Wait until the instruction has been sent
++ *pSPI_TDBR = ulStart; // Send the lowest byte of the 24 bit address finally
++ __builtin_bfin_ssync();
++ Wait_For_SPIF(); // Wait until the instruction has been sent
++
++#ifdef CONFIG_SERIAL_BF537_USE_FAST_READ
++ *pSPI_TDBR = 0; // Send dummy for FAST_READ
++ __builtin_bfin_ssync();
++ Wait_For_SPIF(); // Wait until the instruction has been sent
++#endif
++
++ // After the SPI device address has been placed on the MOSI pin the data can be
++ // received on the MISO pin.
++ for (i=0; i<lCount; i++)
++ {
++ *pSPI_TDBR = 0; //send dummy
++ __builtin_bfin_ssync();
++ while(!(*pSPI_STAT&RXS));
++ *cnData++ = *pSPI_RDBR; //read
++
++ if((i>=SECTOR_SIZE)&&(i%SECTOR_SIZE == 0))
++ printf(".");
++ }
++
++ SPI_OFF(); // Turn off the SPI
++
++ return NO_ERR;
++}
++
++ERROR_CODE WriteFlash ( unsigned long ulStartAddr, long lTransferCount, int *iDataSource, long *lWriteCount )
++{
++
++ unsigned long ulWAddr;
++ long lWTransferCount = 0;
++ int i;
++ char iData;
++ char *temp = (char *)iDataSource;
++ ERROR_CODE ErrorCode = NO_ERR; // tells us if there was an error erasing flash
++
++ // First, a Write Enable Command must be sent to the SPI.
++ SendSingleCommand(SPI_WREN);
++
++ // Second, the SPI Status Register will be tested whether the
++ // Write Enable Bit has been set.
++ ErrorCode = Wait_For_WEL();
++ if( POLL_TIMEOUT == ErrorCode )
++ {
++ printf("SPI Write Time Out\n");
++ return ErrorCode;
++ }
++ else
++ // Third, the 24 bit address will be shifted out the SPI MOSI bytewise.
++ SetupSPI( (COMMON_SPI_SETTINGS|TIMOD01) ); // Turns the SPI on
++ *pSPI_TDBR = SPI_PP;
++ __builtin_bfin_ssync();
++ Wait_For_SPIF(); //wait until the instruction has been sent
++ ulWAddr = (ulStartAddr >> 16);
++ *pSPI_TDBR = ulWAddr;
++ __builtin_bfin_ssync();
++ Wait_For_SPIF(); //wait until the instruction has been sent
++ ulWAddr = (ulStartAddr >> 8);
++ *pSPI_TDBR = ulWAddr;
++ __builtin_bfin_ssync();
++ Wait_For_SPIF(); //wait until the instruction has been sent
++ ulWAddr = ulStartAddr;
++ *pSPI_TDBR = ulWAddr;
++ __builtin_bfin_ssync();
++ Wait_For_SPIF(); //wait until the instruction has been sent
++ // Fourth, maximum number of 256 bytes will be taken from the Buffer
++ // and sent to the SPI device.
++ for (i=0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++)
++ {
++ iData = *temp;
++ *pSPI_TDBR = iData;
++ __builtin_bfin_ssync();
++ Wait_For_SPIF(); //wait until the instruction has been sent
++ temp++;
++ }
++
++ SPI_OFF(); // Turns the SPI off
++
++ // Sixth, the SPI Write in Progress Bit must be toggled to ensure the
++ // programming is done before start of next transfer.
++ ErrorCode = Wait_For_Status(WIP);
++
++ if( POLL_TIMEOUT == ErrorCode )
++ {
++ printf("SPI Program Time out!\n");
++ return ErrorCode;
++ }
++ else
++
++ *lWriteCount = lWTransferCount;
++
++ return ErrorCode;
++}
++
++
++ERROR_CODE WriteData( unsigned long ulStart, long lCount, int *pnData )
++{
++
++ unsigned long ulWStart = ulStart;
++ long lWCount = lCount, lWriteCount;
++ long *pnWriteCount = &lWriteCount;
++
++ ERROR_CODE ErrorCode = NO_ERR;
++
++ while (lWCount != 0)
++ {
++ ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
++
++ // After each function call of WriteFlash the counter must be adjusted
++ lWCount -= *pnWriteCount;
++
++ // Also, both address pointers must be recalculated.
++ ulWStart += *pnWriteCount;
++ pnData += *pnWriteCount/4;
++ }
++
++ // return the appropriate error code
++ return ErrorCode;
++}
++
++/*
++ * Spit out some useful information about the SPI eeprom
++ */
++int eeprom_info(void)
++{
++#if (1)
++ return 1;
++#else
++
++ int ret = 0;
++
++ SPI_INIT();
++
++ if (spi_detect_part())
++ ret = 1;
++ else
++ printf("SPI Device: %s 0x%02X (%s) 0x%02X 0x%02X\n"
++ "Parameters: num sectors = %i, sector size = %i, write size = %i\n"
++ "Flash Size: %i mbit (%i mbyte)\n"
++ "Status: 0x%02X\n",
++ flash.flash->name, flash.manufacturer_id, flash.manufacturer->name,
++ flash.device_id1, flash.device_id2, flash.num_sectors,
++ flash.sector_size, flash.write_length,
++ (flash.num_sectors * flash.sector_size) >> 17,
++ (flash.num_sectors * flash.sector_size) >> 20,
++ read_status_register());
++
++ SPI_DEINIT();
++
++ return ret;
++#endif
++}
++
++
++#endif /* CONFIG_SPI */
+diff --git a/u-boot-1.1.6/board/VuQuest2D/spi_flash.c b/u-boot-1.1.6/board/VuQuest2D/spi_flash.c
+new file mode 100644
+index 0000000..8784741
+--- /dev/null
++++ b/u-boot-1.1.6/board/VuQuest2D/spi_flash.c
+@@ -0,0 +1,2 @@
++/* Share the spi flash code */
++#include "../bf537-stamp/spi_flash.c"
+diff --git a/u-boot-1.1.6/board/VuQuest2D/u-boot.lds.S b/u-boot-1.1.6/board/VuQuest2D/u-boot.lds.S
+new file mode 100644
+index 0000000..01780c5
+--- /dev/null
++++ b/u-boot-1.1.6/board/VuQuest2D/u-boot.lds.S
+@@ -0,0 +1,136 @@
++/*
++ * U-boot - u-boot.lds.S
++ *
++ * Copyright (c) 2005-2008 Analog Device Inc.
++ *
++ * (C) Copyright 2000-2004
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <asm/blackfin.h>
++#undef ALIGN
++
++/* If we don't actually load anything into L1 data, this will avoid
++ * a syntax error. If we do actually load something into L1 data,
++ * we'll get a linker memory load error (which is what we'd want).
++ * This is here in the first place so we can quickly test building
++ * for different CPU's which may lack non-cache L1 data.
++ */
++#ifndef L1_DATA_B_SRAM
++# define L1_DATA_B_SRAM CFG_MONITOR_BASE
++# define L1_DATA_B_SRAM_SIZE 0
++#endif
++
++OUTPUT_ARCH(bfin)
++
++/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
++MEMORY
++{
++ ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
++ l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
++ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
++}
++
++SECTIONS
++{
++ .text :
++ {
++#ifdef ENV_IS_EMBEDDED
++ /* WARNING - the following is hand-optimized to fit within
++ * the sector before the environment sector. If it throws
++ * an error during compilation remove an object here to get
++ * it linked after the configuration sector.
++ */
++
++ cpu/blackfin/start.o (.text)
++ cpu/blackfin/traps.o (.text)
++ cpu/blackfin/interrupt.o (.text)
++ cpu/blackfin/serial.o (.text)
++ common/dlmalloc.o (.text)
++ lib_generic/crc32.o (.text)
++
++ . = DEFINED(env_offset) ? env_offset : .;
++ common/environment.o (.text)
++#endif
++
++ *(.text .text.*)
++ } >ram
++
++ .rodata :
++ {
++ . = ALIGN(4);
++ *(.rodata .rodata.*)
++ *(.rodata1)
++ *(.eh_frame)
++ . = ALIGN(4);
++ } >ram
++
++ .data :
++ {
++ . = ALIGN(256);
++ *(.data .data.*)
++ *(.data1)
++ *(.sdata)
++ *(.sdata2)
++ *(.dynamic)
++ CONSTRUCTORS
++ } >ram
++
++ .u_boot_cmd :
++ {
++ ___u_boot_cmd_start = .;
++ *(.u_boot_cmd)
++ ___u_boot_cmd_end = .;
++ } >ram
++
++ .text_l1 :
++ {
++ . = ALIGN(4);
++ __stext_l1 = .;
++ *(.l1.text)
++ . = ALIGN(4);
++ __etext_l1 = .;
++ } >l1_code AT>ram
++ __stext_l1_lma = LOADADDR(.text_l1);
++
++ .data_l1 :
++ {
++ . = ALIGN(4);
++ __sdata_l1 = .;
++ *(.l1.data)
++ *(.l1.bss)
++ . = ALIGN(4);
++ __edata_l1 = .;
++ } >l1_data AT>ram
++ __sdata_l1_lma = LOADADDR(.data_l1);
++
++ .bss :
++ {
++ . = ALIGN(4);
++ __bss_start = .;
++ *(.sbss) *(.scommon)
++ *(.dynbss)
++ *(.bss .bss.*)
++ *(COMMON)
++ __bss_end = .;
++ } >ram
++}
+diff --git a/u-boot-1.1.6/board/VuQuest2D/video.c b/u-boot-1.1.6/board/VuQuest2D/video.c
+new file mode 100644
+index 0000000..2d6f7a4
+--- /dev/null
++++ b/u-boot-1.1.6/board/VuQuest2D/video.c
+@@ -0,0 +1,187 @@
++/*
++ * (C) Copyright 2000
++ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
++ * (C) Copyright 2002
++ * Wolfgang Denk, wd@denx.de
++ * (C) Copyright 2006
++ * Aubrey Li, aubrey.li@analog.com
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <stdarg.h>
++#include <common.h>
++#include <config.h>
++#include <malloc.h>
++#include <asm/blackfin.h>
++#include <asm/mach-common/bits/dma.h>
++#include <i2c.h>
++#include <linux/types.h>
++#include <devices.h>
++
++int gunzip(void *, int, unsigned char *, unsigned long *);
++
++#ifdef CONFIG_VIDEO
++
++#define DMA_SIZE16 2
++
++#include <asm/mach-common/bits/ppi.h>
++
++#define NTSC_FRAME_ADDR 0x06000000
++#include "video.h"
++
++/* NTSC OUTPUT SIZE 720 * 240 */
++#define VERTICAL 2
++#define HORIZONTAL 4
++
++int is_vblank_line(const int line)
++{
++ /*
++ * This array contains a single bit for each line in
++ * an NTSC frame.
++ */
++ if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
++ return true;
++
++ return false;
++}
++
++int NTSC_framebuffer_init(char *base_address)
++{
++ const int NTSC_frames = 1;
++ const int NTSC_lines = 525;
++ char *dest = base_address;
++ int frame_num, line_num;
++
++ for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
++ for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
++ unsigned int code;
++ int offset = 0;
++ int i;
++
++ if (is_vblank_line(line_num))
++ offset++;
++
++ if (line_num > 266 || line_num < 3)
++ offset += 2;
++
++ /* Output EAV code */
++ code = SystemCodeMap[offset].EAV;
++ write_dest_byte((char)(code >> 24) & 0xff);
++ write_dest_byte((char)(code >> 16) & 0xff);
++ write_dest_byte((char)(code >> 8) & 0xff);
++ write_dest_byte((char)(code) & 0xff);
++
++ /* Output horizontal blanking */
++ for (i = 0; i < 67 * 2; ++i) {
++ write_dest_byte(0x80);
++ write_dest_byte(0x10);
++ }
++
++ /* Output SAV */
++ code = SystemCodeMap[offset].SAV;
++ write_dest_byte((char)(code >> 24) & 0xff);
++ write_dest_byte((char)(code >> 16) & 0xff);
++ write_dest_byte((char)(code >> 8) & 0xff);
++ write_dest_byte((char)(code) & 0xff);
++
++ /* Output empty horizontal data */
++ for (i = 0; i < 360 * 2; ++i) {
++ write_dest_byte(0x80);
++ write_dest_byte(0x10);
++ }
++ }
++ }
++
++ return dest - base_address;
++}
++
++void fill_frame(char *Frame, int Value)
++{
++ int *OddPtr32;
++ int OddLine;
++ int *EvenPtr32;
++ int EvenLine;
++ int i;
++ int *data;
++ int m, n;
++
++ /* fill odd and even frames */
++ for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
++ OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
++ EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
++ for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
++ *OddPtr32 = Value;
++ *EvenPtr32 = Value;
++ }
++ }
++
++ for (m = 0; m < VERTICAL; m++) {
++ data = (int *)u_boot_logo.data;
++ for (OddLine = (22 + m), EvenLine = (285 + m);
++ OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
++ OddLine += VERTICAL, EvenLine += VERTICAL) {
++ OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
++ EvenPtr32 =
++ (int *)((Frame + ((EvenLine) * 1716)) + 276);
++ for (i = 0; i < u_boot_logo.width / 2; i++) {
++ /* enlarge one pixel to m x n */
++ for (n = 0; n < HORIZONTAL; n++) {
++ *OddPtr32++ = *data;
++ *EvenPtr32++ = *data;
++ }
++ data++;
++ }
++ }
++ }
++}
++
++static void video_init(char *NTSCFrame)
++{
++ NTSCFrame = (char *)NTSC_FRAME_ADDR;
++ NTSC_framebuffer_init(NTSCFrame);
++ fill_frame(NTSCFrame, BLUE);
++
++ bfin_write_PPI_CONTROL(0x0082);
++ bfin_write_PPI_FRAME(0x020D);
++
++ bfin_write_DMA0_START_ADDR(NTSCFrame);
++ bfin_write_DMA0_X_COUNT(0x035A);
++ bfin_write_DMA0_X_MODIFY(0x0002);
++ bfin_write_DMA0_Y_COUNT(0x020D);
++ bfin_write_DMA0_Y_MODIFY(0x0002);
++ bfin_write_DMA0_CONFIG(0x1015);
++ bfin_write_PPI_CONTROL(0x0083);
++}
++
++int drv_video_init(void)
++{
++ device_t videodev;
++
++ video_init((void *)NTSC_FRAME_ADDR);
++
++ memset(&videodev, 0, sizeof(videodev));
++ strcpy(videodev.name, "video");
++ videodev.ext = DEV_EXT_VIDEO;
++ videodev.flags = DEV_FLAGS_SYSTEM;
++
++ return device_register(&videodev);
++}
++
++#endif
+diff --git a/u-boot-1.1.6/board/VuQuest2D/video.h b/u-boot-1.1.6/board/VuQuest2D/video.h
+new file mode 100644
+index 0000000..d5a8bc8
+--- /dev/null
++++ b/u-boot-1.1.6/board/VuQuest2D/video.h
+@@ -0,0 +1,25 @@
++#include <video_logo.h>
++#define write_dest_byte(val) {*dest++=val;}
++#define BLACK (0x01800180) /* black pixel pattern */
++#define BLUE (0x296E29F0) /* blue pixel pattern */
++#define RED (0x51F0515A) /* red pixel pattern */
++#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */
++#define GREEN (0x91229136) /* green pixel pattern */
++#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
++#define YELLOW (0xD292D210) /* yellow pixel pattern */
++#define WHITE (0xFE80FE80) /* white pixel pattern */
++
++#define true 1
++#define false 0
++
++typedef struct {
++ unsigned int SAV;
++ unsigned int EAV;
++} SystemCodeType;
++
++const SystemCodeType SystemCodeMap[4] = {
++ {0xFF000080, 0xFF00009D},
++ {0xFF0000AB, 0xFF0000B6},
++ {0xFF0000C7, 0xFF0000DA},
++ {0xFF0000EC, 0xFF0000F1}
++};
+diff --git a/u-boot-1.1.6/common/Makefile b/u-boot-1.1.6/common/Makefile
+index f848123..c9cdabd 100644
+--- a/u-boot-1.1.6/common/Makefile
++++ b/u-boot-1.1.6/common/Makefile
+@@ -51,7 +51,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \
+ memsize.o miiphybb.o miiphyutil.o \
+ s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
+ usb.o usb_kbd.o usb_storage.o \
+- virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o
++ virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o interface_select.o metro_pf.o
+
+ SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
+ OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
+diff --git a/u-boot-1.1.6/common/cmd_bdinfo.c b/u-boot-1.1.6/common/cmd_bdinfo.c
+index bba7b75..3b1fcfc 100644
+--- a/u-boot-1.1.6/common/cmd_bdinfo.c
++++ b/u-boot-1.1.6/common/cmd_bdinfo.c
+@@ -91,36 +91,38 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ print_str ("pevfreq", strmhz(buf, bd->bi_pevfreq));
+ #endif
+
++#if (CONFIG_COMMANDS & CFG_CMD_NET)
+ puts ("ethaddr =");
+ for (i=0; i<6; ++i) {
+ printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
+ }
+
+-#if defined(CONFIG_HAS_ETH1)
++ #if defined(CONFIG_HAS_ETH1)
+ puts ("\neth1addr =");
+ for (i=0; i<6; ++i) {
+ printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
+ }
+-#endif
++ #endif
+
+-#if defined(CONFIG_HAS_ETH2)
++ #if defined(CONFIG_HAS_ETH2)
+ puts ("\neth2addr =");
+ for (i=0; i<6; ++i) {
+ printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
+ }
+-#endif
++ #endif
+
+-#if defined(CONFIG_HAS_ETH3)
++ #if defined(CONFIG_HAS_ETH3)
+ puts ("\neth3addr =");
+ for (i=0; i<6; ++i) {
+ printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]);
+ }
+-#endif
++ #endif
+
+-#ifdef CONFIG_HERMES
++ #ifdef CONFIG_HERMES
+ print_str ("ethspeed", strmhz(buf, bd->bi_ethspeed));
+-#endif
++ #endif
+ puts ("\nIP addr = "); print_IPaddr (bd->bi_ip_addr);
++#endif /* (CONFIG_COMMANDS & CFG_CMD_NET) */
+ printf ("\nbaudrate = %6ld bps\n", bd->bi_baudrate );
+ return 0;
+ }
+@@ -138,12 +140,13 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ print_num ("flashsize", (ulong)bd->bi_flashsize);
+ print_num ("flashoffset", (ulong)bd->bi_flashoffset);
+
++#if (CONFIG_COMMANDS & CFG_CMD_NET)
+ puts ("ethaddr =");
+ for (i=0; i<6; ++i) {
+ printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
+ }
+- puts ("\nip_addr = ");
+- print_IPaddr (bd->bi_ip_addr);
++ puts ("\nip_addr = "); print_IPaddr (bd->bi_ip_addr);
++#endif
+ printf ("\nbaudrate = %ld bps\n", bd->bi_baudrate);
+
+ return 0;
+@@ -167,13 +170,12 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ print_num ("sram size", (ulong)bd->bi_sramsize);
+ #endif
+
+-#if defined(CFG_CMD_NET)
++#if (CONFIG_COMMANDS & CFG_CMD_NET)
+ puts ("ethaddr =");
+ for (i=0; i<6; ++i) {
+ printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
+ }
+- puts ("\nip_addr = ");
+- print_IPaddr (bd->bi_ip_addr);
++ puts ("\nip_addr = "); print_IPaddr (bd->bi_ip_addr);
+ #endif
+
+ printf ("\nbaudrate = %ld bps\n", bd->bi_baudrate);
+@@ -202,11 +204,12 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ print_num("flashsize", (ulong)bd->bi_flashsize);
+ print_num("flashoffset", (ulong)bd->bi_flashoffset);
+
++#if (CONFIG_COMMANDS & CFG_CMD_NET)
+ puts("ethaddr =");
+ for (i = 0; i < 6; ++i)
+ printf("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
+- puts("\nip_addr = ");
+- print_IPaddr(bd->bi_ip_addr);
++ puts("\nip_addr = "); print_IPaddr(bd->bi_ip_addr);
++#endif
+ printf("\nbaudrate = %d bps\n", bd->bi_baudrate);
+
+ return 0;
+@@ -226,12 +229,13 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ print_num ("flashsize", (ulong)bd->bi_flashsize);
+ print_num ("flashoffset", (ulong)bd->bi_flashoffset);
+
++#if (CONFIG_COMMANDS & CFG_CMD_NET)
+ puts ("ethaddr =");
+ for (i=0; i<6; ++i) {
+ printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
+ }
+- puts ("\nip_addr = ");
+- print_IPaddr (bd->bi_ip_addr);
++ puts ("\nip_addr = "); print_IPaddr (bd->bi_ip_addr);
++#endif
+ printf ("\nbaudrate = %d bps\n", bd->bi_baudrate);
+
+ return 0;
+@@ -255,6 +259,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ print_num("-> size", bd->bi_dram[i].size);
+ }
+
++#if (CONFIG_COMMANDS & CFG_CMD_NET)
+ puts ("ethaddr =");
+ for (i=0; i<6; ++i) {
+ printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
+@@ -262,6 +267,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ puts ( "\n"
+ "ip_addr = ");
+ print_IPaddr (bd->bi_ip_addr);
++#endif
+ printf ("\n"
+ "baudrate = %d bps\n", bd->bi_baudrate);
+
+diff --git a/u-boot-1.1.6/common/cmd_bootm.c b/u-boot-1.1.6/common/cmd_bootm.c
+index e6fe472..8711ff4 100644
+--- a/u-boot-1.1.6/common/cmd_bootm.c
++++ b/u-boot-1.1.6/common/cmd_bootm.c
+@@ -150,6 +150,13 @@ image_header_t header;
+
+ ulong load_addr = CFG_LOAD_ADDR; /* Default Load Address */
+
++#if defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
++
++extern int Get_Interface_AtoD_Value(void);
++extern void Send_Interface_AtoD_to_kernel(void);
++
++#endif
++
+ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ {
+ ulong iflag;
+@@ -415,6 +422,12 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ #ifdef CONFIG_SILENT_CONSOLE
+ fixup_silent_linux();
+ #endif
++#if defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
++ if (Get_Interface_AtoD_Value() >= 0)
++ {
++ Send_Interface_AtoD_to_kernel();
++ }
++#endif
+ do_bootm_linux (cmdtp, flag, argc, argv,
+ addr, len_ptr, verify);
+ break;
+diff --git a/u-boot-1.1.6/common/cmd_eeprom.c b/u-boot-1.1.6/common/cmd_eeprom.c
+index cb7963f..84d65aa 100644
+--- a/u-boot-1.1.6/common/cmd_eeprom.c
++++ b/u-boot-1.1.6/common/cmd_eeprom.c
+@@ -42,6 +42,14 @@
+ #include <command.h>
+ #include <i2c.h>
+
++#define DEBUG_BOOT_PERFORMANCE 1
++
++#if (DEBUG_BOOT_PERFORMANCE)
++#include <Metrologic_Hardware.h>
++#include <metro_pf.h>
++#endif
++
++
+ #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) || defined(CFG_ENV_IS_IN_EEPROM)
+
+ extern void eeprom_init (void);
+@@ -139,6 +147,10 @@ int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt
+ unsigned blk_off;
+ int rcode = 0;
+
++
++#if (DEBUG_BOOT_PERFORMANCE) && defined(__ADSPBF531__)
++ *pFIO_FLAG_D |= (PF4); /* Assert Aiming_On */
++#endif
+ /* Read data until done or would cross a page boundary.
+ * We must write the address again when changing pages
+ * because the next page may be in a different device.
+diff --git a/u-boot-1.1.6/common/cmd_load.c b/u-boot-1.1.6/common/cmd_load.c
+index f63b8e8..0c64bc9 100644
+--- a/u-boot-1.1.6/common/cmd_load.c
++++ b/u-boot-1.1.6/common/cmd_load.c
+@@ -25,11 +25,14 @@
+ * Serial up- and download support
+ */
+ #include <common.h>
++#include <watchdog.h>
+ #include <command.h>
+ #include <s_record.h>
+ #include <net.h>
+ #include <exports.h>
+ #include <xyzModem.h>
++#include <asm/mach-common/bits/bootrom.h>
++#include <Metrologic_Hardware.h>
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+@@ -84,9 +87,11 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ if (load_baudrate != current_baudrate) {
+ printf ("## Switch baudrate to %d bps and press ENTER ...\n",
+ load_baudrate);
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
+ udelay(50000);
+ gd->baudrate = load_baudrate;
+ serial_setbrg ();
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
+ udelay(50000);
+ for (;;) {
+ if (getc() == '\r')
+@@ -127,9 +132,11 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ if (load_baudrate != current_baudrate) {
+ printf ("## Switch baudrate to %d bps and press ESC ...\n",
+ current_baudrate);
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
+ udelay (50000);
+ gd->baudrate = current_baudrate;
+ serial_setbrg ();
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
+ udelay (50000);
+ for (;;) {
+ if (getc() == 0x1B) /* ESC */
+@@ -282,9 +289,11 @@ int do_save_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ if (save_baudrate != current_baudrate) {
+ printf ("## Switch baudrate to %d bps and press ENTER ...\n",
+ save_baudrate);
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
+ udelay(50000);
+ gd->baudrate = save_baudrate;
+ serial_setbrg ();
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
+ udelay(50000);
+ for (;;) {
+ if (getc() == '\r')
+@@ -311,9 +320,11 @@ int do_save_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ if (save_baudrate != current_baudrate) {
+ printf ("## Switch baudrate to %d bps and press ESC ...\n",
+ (int)current_baudrate);
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
+ udelay (50000);
+ gd->baudrate = current_baudrate;
+ serial_setbrg ();
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
+ udelay (50000);
+ for (;;) {
+ if (getc() == 0x1B) /* ESC */
+@@ -466,9 +477,11 @@ int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ if (load_baudrate != current_baudrate) {
+ printf ("## Switch baudrate to %d bps and press ENTER ...\n",
+ load_baudrate);
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
+ udelay(50000);
+ gd->baudrate = load_baudrate;
+ serial_setbrg ();
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
+ udelay(50000);
+ for (;;) {
+ if (getc() == '\r')
+@@ -504,9 +517,11 @@ int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ if (load_baudrate != current_baudrate) {
+ printf ("## Switch baudrate to %d bps and press ESC ...\n",
+ current_baudrate);
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
+ udelay (50000);
+ gd->baudrate = current_baudrate;
+ serial_setbrg ();
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
+ udelay (50000);
+ for (;;) {
+ if (getc() == 0x1B) /* ESC */
+@@ -1036,6 +1051,406 @@ static ulong load_serial_ymodem (ulong offset)
+ return offset;
+ }
+
++/**********************************************************************
++ *************** Added by Metrologic *********************************
++ **********************************************************************/
++
++extern flash_info_t flash_info[]; /* info for FLASH chips */
++
++int do_flash (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++#ifdef CFG_NO_FLASH
++ return 0;
++#else
++ ulong addr_first;
++ ulong addr_last;
++ ulong addr = load_addr;
++ ulong dest;
++ ulong count;
++ int rc = 0;
++ char *s;
++
++ if (argc != 2)
++ {
++ goto __DO_FLASH_ERROR;
++ }
++
++ if ((s = getenv("filesize")) != NULL)
++ {
++ count = simple_strtoul(s, NULL, 16);
++ }
++ else
++ {
++ puts ("Unknown filesize! Download file first!\n");
++ return 1;;
++ }
++
++ if (strcmp(argv[1] ,"u-boot") == 0)
++ {
++ int i;
++ flash_info_t *info;
++ int protect_on = 0;
++ int bank;
++ int p = 0;
++
++ puts ("Unprotecting flash sectors... ");
++
++ for (bank=1; bank<=CFG_MAX_FLASH_BANKS; ++bank) {
++ info = &flash_info[bank-1];
++ if (info->flash_id == FLASH_UNKNOWN) {
++ continue;
++ }
++ printf ("%sProtect Flash Bank # %ld\n",
++ p ? "" : "Un-", bank);
++
++ for (i=0; i<info->sector_count; ++i) {
++#if defined(CFG_FLASH_PROTECTION)
++ if (flash_real_protect(info, i, p))
++ rcode = 1;
++ putc ('.');
++#else
++ info->protect[i] = p;
++#endif /* CFG_FLASH_PROTECTION */
++ }
++ }
++
++ puts ("Done\n");
++
++ addr_first = (ulong)U_BOOT_START_ADDR;
++ addr_last = (ulong)CONFIG_START_ADDR - 1;
++
++ dest = U_BOOT_START_ADDR;
++ rc = 1;
++ }
++ else if (strcmp(argv[1] ,"kernel") == 0)
++ {
++ addr_first = (ulong)KERNEL_START_ADDR;
++ addr_last = (ulong)FILSYS_START_ADDR - 1;
++
++ dest = KERNEL_START_ADDR;
++ rc = 2;
++ }
++ else if (strcmp(argv[1] ,"filesystem") == 0)
++ {
++#ifndef CFG_FLASH_SIZE
++ puts ("CFG_FLASH_SIZE must be defined to use this feature!\n");
++ return 1;
++#endif
++
++ addr_first = (ulong)FILSYS_START_ADDR;
++ addr_last = (ulong)FLASH_PARTITION_START + (ulong)CFG_FLASH_SIZE - 1;
++
++ dest = FILSYS_START_ADDR;
++ rc = 3;
++ }
++
++ if (rc >= 1)
++ {
++ if (addr_last <= addr_first)
++ {
++ puts("Invalid CFG_FLASH_SIZE\n");
++ return 1;
++ }
++
++ printf ("Erasing %s\n", argv[1]);
++
++ if (flash_sect_erase(addr_first, addr_last))
++ {
++ printf ("Error erasing region %d - %d\n", addr_first, addr_last);
++ return 1;
++ }
++ puts ("Done\n");
++
++ printf ("Copy %s to Flash... ", argv[1]);
++
++ rc = flash_write ((uchar *)addr, dest, count);
++ if (rc != 0) {
++ flash_perror (rc);
++ return (1);
++ }
++ puts ("done\n");
++ return 0;
++ }
++
++__DO_FLASH_ERROR:
++
++ printf ("Usage:\n%s\n", cmdtp->usage);
++ return 1;
++#endif
++}
++
++int do_eflash ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
++{
++ const char *const fmt =
++ "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
++
++ ulong dev_addr = CFG_DEF_EEPROM_ADDR;
++ ulong addr = load_addr;
++ ulong off;
++ ulong cnt;
++ char *s;
++ int rcode = 0;
++
++ if (argc != 2)
++ {
++ goto __DO_EFLASH_ERROR;
++ }
++
++ if ((s = getenv("filesize")) != NULL)
++ {
++ cnt = simple_strtoul(s, NULL, 16);
++ }
++ else
++ {
++ puts ("Unknown filesize! Download file first!\n");
++ return 1;
++ }
++
++ if (strcmp(argv[1] ,"u-boot") == 0)
++ {
++ off = U_BOOT_START_OFFS;
++ rcode = 1;
++ }
++ else if (strcmp(argv[1] ,"kernel") == 0)
++ {
++ off = KERNEL_START_OFFS;
++ rcode = 2;
++ }
++ else if (strcmp(argv[1] ,"filesystem") == 0)
++ {
++ ulong addr_pad = load_addr - PADDING_BUFF_SIZE;
++ ulong bytes_to_erase = (ulong)CFG_FLASH_SIZE - 1 - FILSYS_START_OFFS;
++ ulong start_offset = FILSYS_START_OFFS;
++ int i;
++
++ if (load_addr < PADDING_BUFF_SIZE)
++ {
++ printf ("load_addr too small, need %d bytes room to erase filesystem\n", PADDING_BUFF_SIZE);
++ return 1;
++ }
++
++ for (i = 0; i < PADDING_BUFF_SIZE; i++)
++ {
++ *((u_char *)addr_pad) = (u_char)PADDING_CHAR;
++ addr_pad += 1;
++ }
++
++ addr_pad = load_addr - PADDING_BUFF_SIZE;
++
++ if (cnt >= 12)
++ {
++ for (i = 0; i < 12; i++)
++ {
++ *((u_char *)addr_pad) = *((u_char*)addr);
++ addr_pad += 1;
++ addr += 1;
++ }
++ }
++
++ addr = load_addr;
++ addr_pad = load_addr - PADDING_BUFF_SIZE;
++
++ puts ("Formatting file system partition... ");
++
++ while (bytes_to_erase > 0)
++ {
++ ulong count;
++
++ if ( bytes_to_erase > PADDING_BUFF_SIZE )
++ {
++ count = PADDING_BUFF_SIZE;
++ }
++ else
++ {
++ for (i = 0; i < 12; i++)
++ {
++ *((u_char *)addr_pad) = (u_char)PADDING_CHAR;
++ addr_pad += 1;
++ }
++ addr_pad = load_addr - PADDING_BUFF_SIZE;
++ count = bytes_to_erase;
++ }
++
++ if (eeprom_write (dev_addr, start_offset, (uchar *) addr_pad, count))
++ {
++ printf("Error erasing %d to %d\n", start_offset, start_offset + count);
++ return 1;
++ }
++ else
++ {
++ puts (".");
++ }
++ start_offset += count;
++ bytes_to_erase -= count;
++ }
++
++ puts ("done\n");
++ off = FILSYS_START_OFFS;
++ rcode = 3;
++ }
++
++ if (rcode >= 1)
++ {
++ printf (fmt, dev_addr, "write", addr, off, cnt);
++ rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);
++ puts ("done\n");
++ return rcode;
++ }
++
++__DO_EFLASH_ERROR:
++
++ printf ("Usage:\n%s\n", cmdtp->usage);
++ return 1;
++
++}
++
++
++int print_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ uint regval1, regval2, regval3, regval4;
++
++#if (defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534) || \
++ defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) )
++
++ regval1 = *pPORTF_FER;
++ regval2 = *pPORTFIO_DIR;
++ regval3 = *pPORTFIO_INEN;
++ regval4 = *pPORTFIO;
++
++ printf ("PortF, FER 0x%04x, DIR 0x%04x, INEN 0x%04x, DATA 0x%04x\r\n",
++ regval1, regval2, regval3, regval4);
++
++ regval1 = *pPORTG_FER;
++ regval2 = *pPORTGIO_DIR;
++ regval3 = *pPORTGIO_INEN;
++ regval4 = *pPORTGIO;
++
++ printf ("PortG, FER 0x%04x, DIR 0x%04x, INEN 0x%04x, DATA 0x%04x\r\n",
++ regval1, regval2, regval3, regval4);
++
++ regval1 = *pPORTH_FER;
++ regval2 = *pPORTHIO_DIR;
++ regval3 = *pPORTHIO_INEN;
++ regval4 = *pPORTHIO;
++
++ printf ("PortH, FER 0x%04x, DIR 0x%04x, INEN 0x%04x, DATA 0x%04x\r\n",
++ regval1, regval2, regval3, regval4);
++
++#elif (defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
++ defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) )
++
++ regval1 = *pFIO_DIR;
++ regval2 = *pFIO_EDGE;
++ regval3 = *pFIO_INEN;
++ regval4 = *pFIO_FLAG_D;
++
++ {
++ uint regval5 = *pFIO_POLAR;
++
++ printf ("PortF, DIR 0x%04x, EDGE 0x%04x, INEN 0x%04x, DATA 0x%04x, POLAR 0x%04x\r\n",
++ regval1, regval2, regval3, regval4, regval5);
++ }
++#else
++#error "Unknown Blackfin platform..."
++#endif
++
++ regval1 = *pVR_CTL;
++ printf("VR_CTL = 0x%04x\r\n", regval1);
++
++ return 0;
++}
++
++extern void Configure_Interface_IO(void);
++extern void DisplayInterfaceBoard(void);
++
++#if defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
++
++extern int Get_Interface_AtoD_Value(void);
++extern void Send_Interface_AtoD_to_kernel(void);
++int program_vrctl(int millivolt);
++
++#endif
++
++int interfaceboard_init (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ Configure_Interface_IO();
++ DisplayInterfaceBoard();
++#if defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
++ if (Get_Interface_AtoD_Value() >= 0)
++ {
++ Send_Interface_AtoD_to_kernel();
++ }
++#endif
++ return 0;
++}
++
++int prog_vrctl (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ unsigned long voltage;
++
++ if (argc != 2)
++ {
++ goto __PROG_VRCTL_ERROR;
++ }
++
++ voltage = simple_strtoul(argv[1], NULL, 10);
++
++ if (voltage < 850 || voltage > 1300)
++ {
++ goto __PROG_VRCTL_ERROR;
++ }
++
++ if (voltage % 50)
++ {
++ goto __PROG_VRCTL_ERROR;
++ }
++
++ program_vrctl(voltage);
++
++ return 0;
++
++__PROG_VRCTL_ERROR:
++ printf ("Usage:\n%s\n", cmdtp->usage);
++ return 1;
++}
++
++int program_vrctl(int millivolt)
++{
++ int vlev = 6;
++ uint mask = 0xFF0F;
++
++#if defined(CONFIG_DISABLE_CLKIN_OUTPUT)
++#if (CONFIG_DISABLE_CLKIN_OUTPUT)
++
++ mask = 0xBF0F;
++
++#endif
++#endif
++
++ vlev = 6 + (millivolt - 850) / 50;
++
++ disable_interrupts();
++
++ if (millivolt < 850 || millivolt > 1300)
++ { /* Preserve the voltage setting but update the clkin-output */
++ *pVR_CTL = *pVR_CTL & (mask | 0x00f0);
++ }
++ else
++ {
++ *pVR_CTL = (*pVR_CTL & mask) | (vlev << 4);
++ }
++
++ asm("idle;");
++
++ enable_interrupts();
++
++ return 0;
++}
++
++/**********************************************************************
++ *************** Metrologic *********************************
++ **********************************************************************/
++
+ #endif /* CFG_CMD_LOADB */
+
+ /* -------------------------------------------------------------------- */
+@@ -1103,6 +1518,47 @@ U_BOOT_CMD(
+ " with offset 'off' and baudrate 'baud'\n"
+ );
+
++
++/**********************************************************************
++ *************** Added by Metrologic *********************************
++ **********************************************************************/
++
++U_BOOT_CMD(
++ flash, 2, 0, do_flash,
++ "flash - save binary file to parallel flash\n",
++ "[ u-boot | kernel | filesystem ]\n"
++ " - save binary file to parallel flash\n"
++);
++
++U_BOOT_CMD(
++ eflash, 2, 0, do_eflash,
++ "eflash - save binary file to EEPROM\n",
++ "[ u-boot | kernel | filesystem ]\n"
++ " - save binary file to EEPROM\n"
++);
++
++U_BOOT_CMD(
++ status, 2, 0, print_status,
++ "status - Prints the status of different registers\n",
++ "\n"
++);
++
++U_BOOT_CMD(
++ ibinit, 2, 0, interfaceboard_init,
++ "ibinit - Detect Interface Board and initialize IO \n",
++ "\n"
++);
++
++U_BOOT_CMD(
++ vrctl, 2, 0, prog_vrctl,
++ "vrctl - Programs new voltage (mV) to Bfin Core [850 .. 1300]\n",
++ "\n"
++);
++
++/**********************************************************************
++ *************** Metrologic *********************************
++ **********************************************************************/
++
+ #endif /* CFG_CMD_LOADB */
+
+ /* -------------------------------------------------------------------- */
+diff --git a/u-boot-1.1.6/common/cmd_mem.c b/u-boot-1.1.6/common/cmd_mem.c
+index 3f1023c..154035e 100644
+--- a/u-boot-1.1.6/common/cmd_mem.c
++++ b/u-boot-1.1.6/common/cmd_mem.c
+@@ -1028,6 +1028,95 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ }
+
+
++/*
++ * Runs memory test from CFG_MEMTEST_END to CFG_MEMTEST_END.
++ */
++
++int FullRamTest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ int testcnt = 0;
++ int test_passed = 1;
++
++ vu_long *addr_to_fail;
++ vu_long *current_addr;
++
++ vu_long *start = (ulong *)CFG_MEMTEST_START;
++ vu_long *end = (ulong *)CFG_MEMTEST_END;
++
++ ulong pattern1 = 0x5a5a5a5a;
++ ulong pattern2 = 0xa5a5a5a5;
++
++ ulong val1, val2;
++
++ if (argc > 2)
++ {
++ printf("Performing Full Ram Test from 0x%08x to 0x%08x:\n", CFG_MEMTEST_START, CFG_MEMTEST_END - 1);
++ }
++
++ if ( argc < 2 )
++ {
++ addr_to_fail = (ulong *)CFG_MEMTEST_END + 0x1000;
++ }
++ else if (argc > 1)
++ {
++ addr_to_fail = (ulong *)simple_strtoul(argv[1], NULL, 16);
++ }
++
++ for(current_addr = CFG_MEMTEST_START; current_addr < CFG_MEMTEST_END; current_addr+=2)
++ {
++ if ( (((long)current_addr & 0x3ffff) == 0) && (argc > 2) )
++ { /* print progress */
++ printf("0x%08x\r", current_addr);
++ }
++
++ test_passed = 0;
++
++ if (current_addr != addr_to_fail)
++ { /* Run memory test here */
++ *current_addr = pattern1;
++ *(current_addr + 1) = pattern2;
++
++ val1 = *current_addr;
++ val2 = *(current_addr + 1);
++
++ if ((val1 == pattern1) && (val2 == pattern2))
++ {
++ test_passed = 1;
++ }
++
++ testcnt += 2;
++ }
++
++ if (test_passed < 1 && argc > 2)
++ {
++ if (val1 != pattern1)
++ {
++ printf("Ram test failed at 0x%08x\n", current_addr);
++ printf("\rExpected 0x%08x but read 0x%08x \r\n", val1, pattern1);
++ }
++ if (val2 != pattern2)
++ {
++ printf("Ram test failed at 0x%08x\n", current_addr + 1);
++ printf("\rExpected 0x%08x but read 0x%08x \r\n", val2, pattern2);
++ }
++ }
++ }
++
++ if (argc > 2)
++ {
++ printf("\nDone testing 0x%08x addresses!\n", testcnt);
++ }
++
++ if (argc == 1)
++ {
++ printf("%d\r\n", test_passed);
++ }
++
++ return test_passed ;
++}
++
++
++
+ /* Modify memory.
+ *
+ * Syntax:
+@@ -1314,6 +1403,13 @@ U_BOOT_CMD(
+ " - simple RAM read/write test\n"
+ );
+
++U_BOOT_CMD(
++ ramtest, 3, 1, FullRamTest,
++ "ramtest - RAM test covering all but the last MB of Memory\n",
++ "[loop]\n"
++ " - RAM read/write test\n"
++);
++
+ #ifdef CONFIG_MX_CYCLIC
+ U_BOOT_CMD(
+ mdc, 4, 1, do_mem_mdc,
+diff --git a/u-boot-1.1.6/common/interface_select.c b/u-boot-1.1.6/common/interface_select.c
+new file mode 100644
+index 0000000..d571105
+--- /dev/null
++++ b/u-boot-1.1.6/common/interface_select.c
+@@ -0,0 +1,526 @@
++#include <common.h>
++#include <watchdog.h>
++#include <config.h>
++#include <asm/blackfin.h>
++#include <i2c.h>
++#include <Metrologic_Hardware.h>
++#include <metro_pf.h>
++
++/* All transfers are described by this data structure */
++struct i2c_msg {
++ u16 addr; /* slave address */
++ u16 flags;
++#define I2C_M_STOP 0x2
++#define I2C_M_RD 0x1
++ u16 len; /* msg length */
++ u8 *buf; /* pointer to msg data */
++};
++
++#define CLR_PIN(x) set_pfx_level(x, 0)
++#define SET_PIN(x) set_pfx_level(x, 1)
++#define GPDRX_OUT(x) set_pfx_dir(x, 1)
++#define GPDRX_IN(x) set_pfx_dir(x, 0)
++
++
++//extern int i2c_transfer(struct i2c_msg *msg);
++extern int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
++extern int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
++
++BOARD_FEATURE board_desc[] = {
++ { KBW_BOARD, 17 , 31 },
++ { LASER_EMULATION_BOARD, 33 , 47 },
++ { IBM_BOARD, 49 , 63 },
++ { OCIA_BOARD, 65 , 79 },
++ { LS_USB_HID_BOARD, 81 , 95 },
++ { LS_USB_POS_BOARD, 97 , 111 },
++ { FS_USB_BOARD, 113, 127 },
++ { BLUETOOTH_BOARD, 129, 143 },
++ { MULTIFUN_IBM_USB_BOARD, 145, 159 },
++ { RS232_BOARD, 241, 255 },
++ { 0, 0 , 0 }
++};
++
++static unsigned char NOVRAM_Array[NOVRAM_SIGNATURE_LEN + NOVRAMSIZE];
++static int Detected_Interface_Board;
++static int AtoD_Value;
++
++/*
++ * Function will return rd_len if successful
++ */
++
++#if defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
++
++int
++Psoc_I2C_Xfer(unsigned char *wr_msg, int wr_len,
++ unsigned char *rd_msg, int rd_len,
++ int wait_uSec,
++ int timeout_uSec)
++{
++ int i2c_clk;
++ int num_polls;
++ int i, j;
++ struct i2c_msg msg;
++
++#if defined(CONFIG_HARD_I2C)
++ i2c_clk = CFG_I2C_SPEED;
++#elif defined(CONFIG_SOFT_I2C)
++ i2c_clk = CFG_I2C_SPEED;
++#else
++ i2c_clk = 50000;
++#endif
++
++ num_polls = timeout_uSec * i2c_clk / (1000000 * rd_len * 10);
++
++ if (num_polls < 1)
++ {
++ num_polls = 1;
++ }
++
++ i2c_init(i2c_clk, PSOC_CHIP_ADDR);
++
++// PRINTD("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x, buf0=0x%x\n", chip, addr, alen, len, buffer[0]);
++
++ /* write out command */
++
++ for (i = 0; i < NUM_RETRIES_ON_XFER; i++)
++ {
++ msg.addr = PSOC_CHIP_ADDR;
++ msg.flags = 0;
++ msg.len = wr_len;
++ msg.buf = wr_msg;
++
++// if (i2c_transfer(&msg)) return -1;
++ if (i2c_write(PSOC_CHIP_ADDR, 0, 0, wr_msg, wr_len))
++ {
++ return -1;
++ }
++
++ /* Wait */
++
++ if (wait_uSec)
++ {
++ udelay(wait_uSec);
++ }
++
++ /* poll */
++ for (j = 0; j < num_polls; j++)
++ {
++ msg.addr = PSOC_CHIP_ADDR;
++ msg.flags = I2C_M_RD;
++ msg.len = rd_len;
++ msg.buf = rd_msg;
++
++// if (i2c_transfer(&msg)) return -1;
++ if (i2c_read(PSOC_CHIP_ADDR, 0, 0, rd_msg, rd_len))
++ {
++ return -1;
++ }
++
++ /* Check for valid data here */
++
++ if (rd_msg[0] == 0x06)
++ { /* Data is valid */
++ return rd_len;
++ }
++
++ udelay(10);
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
++ }
++
++ udelay(10 * 1000);
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
++ }
++
++ /* Timeout */
++
++ return -2;
++}
++
++static int
++ReadAtoD(void)
++{
++ unsigned char wr_msg[1], rd_msg[2];
++
++ wr_msg[0] = 'a';
++
++ if (Psoc_I2C_Xfer(wr_msg, 1, rd_msg, 2, PSOC_COMMAND_DELAY_USEC, PSOC_COMMAND_TIMEOUT_USEC) < 0)
++ {
++#if defined(DEBUG_METRO_IO)
++ printf("Error reading I2C()\r\n");
++#endif
++ return -1;
++ }
++ else
++ {
++#if defined(DEBUG_METRO_IO)
++ printf("I2C read completed()\r\n");
++#endif
++ return (int)rd_msg[1];
++ }
++}
++
++
++static int
++ReadInterfaceType(void)
++{
++ int i;
++
++#if defined(DEBUG_METRO_IO)
++ printf("start ReadAtoD()\r\n");
++#endif
++#if (CONFIG_METROLOGIC_VQ2D_REV)
++ AtoD_Value = Read_VQ_AtoD();
++#else
++ AtoD_Value = ReadAtoD();
++#endif
++#if defined(DEBUG_METRO_IO)
++ printf("returned from ReadAtoD()\r\n");
++#endif
++
++ if (AtoD_Value < 0 || AtoD_Value > 255)
++ {
++ return UNKNOWN_INTERFACE_BOARD;
++ }
++
++ for (i = 0; i < NUM_SUPPORTED_INTERFACE_BOARD; i++)
++ {
++ if ((AtoD_Value <= board_desc[i].AtoD_high) && (AtoD_Value >= board_desc[i].AtoD_low))
++ {
++ return board_desc[i].board_type;
++ }
++ }
++
++ return UNKNOWN_INTERFACE_BOARD;
++
++}
++
++
++//extern int Get_Interface_AtoD_Value(void);
++
++void
++Send_Interface_AtoD_to_kernel(void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++ char buf[256], buf2[32], *start, *end;
++ char *cmdline = getenv ("bootargs");
++
++ if (cmdline)
++ {
++ if ((start = strstr (cmdline, "intsel=")) == NULL)
++ {
++ strcpy (buf, cmdline);
++ sprintf(buf2, " intsel=%d", Get_Interface_AtoD_Value());
++ strcat (buf, buf2);
++ }
++ }
++
++ setenv ("bootargs", buf);
++}
++
++#endif /* CONFIG_METROLOGIC_INTERFACE_DETECTION */
++
++static int
++GetNovram(void)
++{
++ ulong dev_addr = CFG_DEF_EEPROM_ADDR;
++ ulong addr = (ulong)NOVRAM_Array;
++ ulong off = CONFIG_START_OFFS;
++ ulong cnt = NOVRAM_SIGNATURE_LEN + NOVRAMSIZE;
++ int i;
++
++ if (eeprom_read (dev_addr, off, (uchar *) addr, cnt))
++ {
++ return -1;
++ }
++
++ for (i = 0; i < NOVRAM_SIGNATURE_LEN; i++)
++ {
++ if (NOVRAM_Array[i] != NOVRAM_SIGNATURE[i])
++ {
++ return -1;
++ }
++ }
++
++ return 1;
++}
++
++static uchar
++get_NOVRAM_Data(int addr)
++{
++ if (addr < 0 || addr > NOVRAMSIZE)
++ {
++ return 0;
++ }
++ return NOVRAM_Array[addr + NOVRAM_SIGNATURE_LEN];
++}
++
++void
++Configure_RTS_Pin(void)
++{
++#if defined(RTS_PIN)
++#if defined(CONFIG_RTS_DEFAULT_ASSERTED)
++ if ( !(get_NOVRAM_Data(158) & (1 << 6)) )
++ { /* Not support for Metrologic RTS / CTS */
++ CLR_PIN(RTS_PIN);
++ }
++ else
++ {
++ if (get_NOVRAM_Data(245) & 1)
++ { /* RTS level inverted, asserts high */
++ SET_PIN(RTS_PIN);
++ }
++ else
++ { /* RTS level normal, asserts low */
++ CLR_PIN(RTS_PIN);
++ }
++ }
++#else
++ if (get_NOVRAM_Data(245) & 1)
++ { /* RTS level inverted, idles low */
++ CLR_PIN(RTS_PIN);
++ }
++ else
++ { /* RTS level normal, idles high */
++ SET_PIN(RTS_PIN);
++ }
++#endif
++ GPDRX_OUT(RTS_PIN);
++#endif
++}
++
++void
++Configure_Interface_IO(void)
++{
++ if (GetNovram() < 0)
++ { /* Error reading NOVRAM */
++ int i;
++
++ for (i = 0; i < NOVRAM_SIGNATURE_LEN + NOVRAMSIZE; i++)
++ {
++ NOVRAM_Array[i] = 0;
++ }
++ }
++
++#if (CONFIG_METROLOGIC_VQ2D_REV)
++ int interface_board;
++
++ interface_board = Detected_Interface_Board = ReadInterfaceType();
++
++ Configure_VQ2D_Interface_IO(interface_board);
++
++ if (interface_board == RS232_BOARD)
++ {
++ Configure_RTS_Pin();
++ }
++
++#elif defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
++ int interface_board;
++
++ interface_board = Detected_Interface_Board = ReadInterfaceType();
++
++#if defined(DEBUG_METRO_IO)
++ printf("returned from ReadInterfaceType()\r\n");
++#endif
++
++ if (interface_board == KBW_BOARD)
++ {
++#ifdef CONFIG_SUPPORT_KBW
++ /* configure RTS as KBClock (output low, but inverted to high
++ * at the interface board) for the KBW. If in stand-alone mode, kb
++ * would still be funcitonal and responsible for handshaking until
++ * kbw driver is loaded */
++ CLR_PIN(KBCLOCK_PIN);
++ GPDRX_OUT(KBCLOCK_PIN);
++
++ CLR_PIN(KBW_GATE_PIN); /* enable feed thru */
++#endif
++#if defined(DEBUG_METRO_IO)
++ printf("configured KBW\r\n");
++#endif
++ }
++ else if (interface_board == RS232_BOARD || interface_board == LS_USB_HID_BOARD ||
++ interface_board == LS_USB_POS_BOARD || interface_board == FS_USB_BOARD ||
++ interface_board == IBM_BOARD )
++ { /* read the novram and set up the RTS level */
++#if defined(RTS_PIN)
++#if defined(CONFIG_RTS_DEFAULT_ASSERTED)
++ if ( !(get_NOVRAM_Data(158) & (1 << 6)) )
++ { /* Not support for Metrologic RTS / CTS */
++ CLR_PIN(RTS_PIN);
++ }
++ else
++ {
++ if (get_NOVRAM_Data(245) & 1)
++ { /* RTS level inverted, asserts high */
++ SET_PIN(RTS_PIN);
++ }
++ else
++ { /* RTS level normal, asserts low */
++ CLR_PIN(RTS_PIN);
++ }
++ }
++#else
++ if (get_NOVRAM_Data(245) & 1)
++ { /* RTS level inverted, idles low */
++ CLR_PIN(RTS_PIN);
++ }
++ else
++ { /* RTS level normal, idles high */
++ SET_PIN(RTS_PIN);
++ }
++#endif
++
++ GPDRX_OUT(RTS_PIN);
++#endif /* RTS_PIN */
++
++#ifdef CONFIG_SUPPORT_IBM
++ if (interface_board == IBM_BOARD)
++ {
++ CLR_PIN(IBM_RS4680_RESET_PIN);
++#if defined(DEBUG_METRO_IO)
++ printf("configured IBM\r\n");
++#endif
++ }
++#endif
++ }
++ else if (interface_board == MULTIFUN_IBM_USB_BOARD)
++ {
++#ifdef CONFIG_SUPPORT_MULTIFUNC
++ /* set up the I/O for MULTIFUN_IBM_USB_BOARD */
++ CLR_PIN(IBM_RS4680_RESET_PIN);
++ /* RTS line is used as CTS to Interface signal, for now, signal that Focus is
++ * ready to receive data so that nothing is lock up.
++ * CAUTION!!! Must confirm this is the right handshaking protocol */
++ CLR_PIN(RTS_PIN);
++ GPDRX_OUT(RTS_PIN);
++#endif
++ }
++ else if (interface_board == BLUETOOTH_BOARD)
++ {
++#ifdef CONFIG_SUPPORT_BLUETOOTH
++ // configure IO pins
++ GPDRX_OUT(BT_LDO_PIN);
++ GPDRX_OUT(BT_RESET_PIN);
++ GPDRX_OUT(BT_SWITCH_PIN);
++ GPDRX_OUT(BLUE_LED_PIN);
++ GPDRX_OUT(WHITE_LED_PIN);
++ GPDRX_OUT(YELLOW_LED_PIN);
++
++ GPDRX_IN(BT_CONN_PIN);
++ GPDRX_IN(BT_RDY_PIN);
++ GPDRX_IN(BT_DSR_PIN);
++ GPDRX_IN(TRIG_PIN);
++
++ SET_PIN(BT_LDO_PIN);
++ SET_PIN(BT_RESET_PIN);
++ SET_PIN(BT_SWITCH_PIN);
++
++ CLR_PIN(FOCUS_KBWEN_PIN);
++ GPDRX_OUT(FOCUS_KBWEN_PIN);
++#endif
++ }
++
++ /* Now enable the KB_GATE, BTRTS, PC_CLK, PC_DATA signals */
++#ifdef FOCUS_KBWEN_PIN
++ if (FOCUS_KBWEN_PIN >= 0 && FOCUS_KBWEN_PIN < 48)
++ {
++ CLR_PIN(FOCUS_KBWEN_PIN); /* Active low signal */
++ GPDRX_OUT(FOCUS_KBWEN_PIN);
++ }
++#endif
++
++#else /* CONFIG_METROLOGIC_INTERFACE_DETECTION */
++
++#if defined(RTS_PIN)
++ if (get_NOVRAM_Data(245) & 1)
++ { /* RTS level inverted, idles low */
++ CLR_PIN(RTS_PIN);
++ }
++ else
++ { /* RTS level normal, idles high */
++ SET_PIN(RTS_PIN);
++ }
++
++ GPDRX_OUT(RTS_PIN);
++
++#endif /* RTS_PIN */
++
++#endif /* CONFIG_METROLOGIC_INTERFACE_DETECTION */
++
++ __builtin_bfin_ssync();
++
++}
++
++void
++DisplayInterfaceBoard(void)
++{
++ printf(INTERFACE_TYPE_TITLE);
++ printf(" ");
++
++ switch(Detected_Interface_Board)
++ {
++ case RS232_BOARD:
++ printf(INTERFACE_RS232_TEXT);
++ break;
++
++ case KBW_BOARD:
++ printf(INTERFACE_KBW_TEXT);
++ break;
++
++ case LASER_EMULATION_BOARD:
++ printf(INTERFACE_UNKNOWN_TEXT);
++ break;
++
++ case IBM_BOARD:
++ printf(INTERFACE_IBM_TEXT);
++ break;
++
++ case OCIA_BOARD:
++ printf(INTERFACE_OCIA_TEXT);
++ break;
++
++ case LS_USB_HID_BOARD:
++ printf(INTERFACE_LSUSBHID_TEXT);
++ break;
++
++ case LS_USB_POS_BOARD:
++ printf(INTERFACE_LSUSBPOS_TEXT);
++ break;
++
++ case FS_USB_BOARD:
++ printf(INTERFACE_FSUSB_TEXT);
++ break;
++
++ case BLUETOOTH_BOARD:
++ printf(INTERFACE_BLUETOOTH_TEXT);
++ break;
++
++ case MULTIFUN_IBM_USB_BOARD:
++ printf(INTERFACE_MULTIFUN_USB_IBM_TEXT);
++ break;
++
++ default:
++ printf(INTERFACE_UNKNOWN_TEXT);
++ break;
++
++ }
++
++ printf("\n");
++
++ printf("IntSel A/D = %d\r\n", AtoD_Value);
++
++ printf("Novram[155] = 0x%02x\r\n", get_NOVRAM_Data(155));
++}
++
++
++int Get_Interface_Board_Type(void)
++{
++ return Detected_Interface_Board;
++}
++
++
++int Get_Interface_AtoD_Value(void)
++{
++ return AtoD_Value;
++}
++
+diff --git a/u-boot-1.1.6/common/main.c b/u-boot-1.1.6/common/main.c
+index 0659c5b..6acc222 100644
+--- a/u-boot-1.1.6/common/main.c
++++ b/u-boot-1.1.6/common/main.c
+@@ -28,11 +28,14 @@
+ /* #define DEBUG */
+
+ #include <common.h>
++#include <config.h>
+ #include <watchdog.h>
+ #include <command.h>
+ #ifdef CONFIG_MODEM_SUPPORT
+ #include <malloc.h> /* for free() prototype */
+ #endif
++#include <Metrologic_Hardware.h>
++#include <metro_pf.h>
+
+ #ifdef CFG_HUSH_PARSER
+ #include <hush.h>
+@@ -49,6 +52,14 @@ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* fo
+ #endif
+
+ extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
++extern int Get_Interface_Board_Type(void);
++extern int get_pfx_level(int pf_num);
++extern int set_pfx_level(int pf_num, int level);
++extern void set_cmdline_active(int active);
++
++#define SET_PIN(gpio_pin) { set_pfx_level(gpio_pin, 1); }
++#define CLR_PIN(gpio_pin) { set_pfx_level(gpio_pin, 0); }
++#define GET_PIN_LEVEL(gpio_pin) ( get_pfx_level(gpio_pin) )
+
+
+ #define MAX_DELAY_STOP_STR 32
+@@ -84,16 +95,66 @@ int do_mdm_init = 0;
+ extern void mdm_init(void); /* defined in board.c */
+ #endif
+
++#ifdef CONFIG_SUPPORT_BLUETOOTH
++static __inline__ int bluetooth_abortboot(void)
++{
++ int abort = 0;
++
++ if(Get_Interface_Board_Type() == BLUETOOTH_BOARD)
++ {
++ int ct, prev_state, curr_state;
++ int lh_trans = 0; // number of low-to-high transitions on trigger pin
++ int hl_trans = 0; // number of high-to-low transitions on trigger pin
++
++ prev_state = GET_PIN_LEVEL(TRIG_PIN);
++
++ if (prev_state == 0) // enter this loop only if trigger is initially activated
++ // (trigger is active-low)
++ {
++ SET_PIN(YELLOW_LED_PIN);
++ CLR_PIN(WHITE_LED_PIN);
++ CLR_PIN(BLUE_LED_PIN);
++
++ // Sit in a loop for 2 seconds and check trigger pin every 5 ms
++ for(ct=0; ct<400; ct++)
++ {
++ udelay(5000);
++ curr_state = GET_PIN_LEVEL(TRIG_PIN);
++ if (curr_state == 1 && prev_state == 0)
++ {
++ lh_trans++;
++ }
++ else if (curr_state == 0 && prev_state == 1)
++ {
++ hl_trans++;
++ }
++ prev_state = curr_state;
++
++ if(lh_trans > 1 && hl_trans > 1) // double-click detected
++ {
++ abort = 1;
++ break;
++ }
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
++ }
++ }
++ }
++ return abort;
++}
++#endif
++
+ /***************************************************************************
+ * Watch for 'delay' seconds for autoboot stop or autoboot delay string.
+ * returns: 0 - no key string, allow autoboot
+ * 1 - got key string, abort
+ */
++
+ #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
+ # if defined(CONFIG_AUTOBOOT_KEYED)
+ static __inline__ int abortboot(int bootdelay)
+ {
+ int abort = 0;
++ int try_once = 0;
+ uint64_t etime = endtick(bootdelay);
+ struct {
+ char* str;
+@@ -150,6 +211,13 @@ static __inline__ int abortboot(int bootdelay)
+ presskey_max = presskey_max > delaykey[i].len ?
+ presskey_max : delaykey[i].len;
+
++#if defined CONFIG_ZERO_BOOTDELAY_CHECK
++ if (bootdelay == 0 && delaykey[i].len == 1)
++ {
++ try_once = 1;
++ }
++#endif
++
+ # if DEBUG_BOOTKEYS
+ printf("%s key:<%s>\n",
+ delaykey[i].retry ? "delay" : "stop",
+@@ -157,10 +225,23 @@ static __inline__ int abortboot(int bootdelay)
+ # endif
+ }
+
++#if defined CONFIG_ZERO_BOOTDELAY_CHECK
++ if (try_once)
++ {
++ udelay(10000);
++
++ if (tstc())
++ {
++ presskey [presskey_len ++] = getc();
++ }
++ }
++#endif
++
+ /* In order to keep up with incoming data, check timeout only
+ * when catch up.
+ */
+- while (!abort && get_ticks() <= etime) {
++ while (try_once > 0 || (!abort && get_ticks() <= etime)) {
++ try_once = 0;
+ for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) {
+ if (delaykey[i].len > 0 &&
+ presskey_len >= delaykey[i].len &&
+@@ -198,6 +279,13 @@ static __inline__ int abortboot(int bootdelay)
+ puts ("key timeout\n");
+ # endif
+
++#ifdef CONFIG_SUPPORT_BLUETOOTH
++ if (!abort)
++ {
++ abort = bluetooth_abortboot();
++ }
++#endif
++
+ #ifdef CONFIG_SILENT_CONSOLE
+ if (abort) {
+ /* permanently enable normal console output */
+@@ -274,6 +362,13 @@ static __inline__ int abortboot(int bootdelay)
+
+ putc ('\n');
+
++#ifdef CONFIG_SUPPORT_BLUETOOTH
++ if (!abort)
++ {
++ abort = bluetooth_abortboot();
++ }
++#endif
++
+ #ifdef CONFIG_SILENT_CONSOLE
+ if (abort) {
+ /* permanently enable normal console output */
+@@ -443,7 +538,31 @@ void main_loop (void)
+ }
+ #endif
+
+- /*
++#ifdef CONFIG_SUPPORT_BLUETOOTH
++ if(Get_Interface_Board_Type() == BLUETOOTH_BOARD)
++ {
++ CLR_PIN(YELLOW_LED_PIN);
++ SET_PIN(WHITE_LED_PIN); // indicates to user that we have entered the bootloader
++
++ CLR_PIN(BT_RESET_PIN); // reset Bluetooth chip
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
++ udelay(5000);
++ SET_PIN(BT_RESET_PIN);
++
++ if (gd->baudrate != 115200)
++ {
++ // Reinitialize serial to 115200 bps
++ gd->baudrate = 115200;
++ serial_setbrg();
++
++ udelay(50000);
++ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
++ }
++ set_cmdline_active(1);
++ }
++#endif
++
++ /*
+ * Main Loop for Monitor Command Processing
+ */
+ #ifdef CFG_HUSH_PARSER
+diff --git a/u-boot-1.1.6/common/metro_pf.c b/u-boot-1.1.6/common/metro_pf.c
+new file mode 100644
+index 0000000..de6421b
+--- /dev/null
++++ b/u-boot-1.1.6/common/metro_pf.c
+@@ -0,0 +1,318 @@
++#include <common.h>
++#include <config.h>
++#include <asm/blackfin.h>
++#include <metro_pf.h>
++
++#ifndef PF_bit
++#define PF_bit(pfx) ( 1 << (pfx & 0x0f) )
++#endif
++
++//#ifndef CSYNC
++//#define CSYNC asm("csync;")
++//#endif
++
++//#ifndef SSYNC
++//#define SSYNC asm("ssync;")
++//#endif
++
++int Metro_set_pfx_dir(int pf_num, int dir, int initial_val);
++int Metro_get_pfx_dir(int pf_num);
++
++#if (defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) || \
++ defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) )
++
++
++static void
++Metro_set_portF_pfx_dir(int pf_num, int dir, int initial_val)
++{
++ unsigned short mask = PF_bit(pf_num);
++
++ *pPORTFIO_MASKA_CLEAR = mask;
++ *pPORTFIO_MASKB_CLEAR = mask;
++ *pPORTF_FER &= ~mask;
++ SSYNC();
++ if (dir)
++ {
++ *pPORTFIO_INEN &= ~mask;
++ if (initial_val > 0)
++ *pPORTFIO_SET = mask;
++ else if (initial_val == 0)
++ *pPORTFIO_CLEAR = mask;
++ *pPORTFIO_DIR |= mask;
++ *pPORTFIO_POLAR &= ~mask;
++ *pPORTFIO_EDGE &= ~mask;
++ *pPORTFIO_BOTH &= ~mask;
++ }
++ else
++ {
++ *pPORTFIO_DIR &= ~mask;
++ *pPORTFIO_POLAR &= ~mask;
++ *pPORTFIO_EDGE &= ~mask;
++ *pPORTFIO_BOTH &= ~mask;
++ *pPORTFIO_INEN |= mask;
++ }
++ SSYNC();
++}
++
++static void
++Metro_set_portG_pfx_dir(int pf_num, int dir, int initial_val)
++{
++ unsigned short mask = PF_bit(pf_num);
++
++ *pPORTGIO_MASKA_CLEAR = mask;
++ *pPORTGIO_MASKB_CLEAR = mask;
++ *pPORTG_FER &= ~mask;
++ SSYNC();
++ if (dir)
++ {
++ *pPORTGIO_INEN &= ~mask;
++ if (initial_val > 0)
++ *pPORTGIO_SET = mask;
++ else if (initial_val == 0)
++ *pPORTGIO_CLEAR = mask;
++ *pPORTGIO_DIR |= mask;
++ *pPORTGIO_POLAR &= ~mask;
++ *pPORTGIO_EDGE &= ~mask;
++ *pPORTGIO_BOTH &= ~mask;
++ }
++ else
++ {
++ *pPORTGIO_DIR &= ~mask;
++ *pPORTGIO_POLAR &= ~mask;
++ *pPORTGIO_EDGE &= ~mask;
++ *pPORTGIO_BOTH &= ~mask;
++ *pPORTGIO_INEN |= mask;
++ }
++ SSYNC();
++}
++
++static void
++Metro_set_portH_pfx_dir(int pf_num, int dir, int initial_val)
++{
++ unsigned short mask = PF_bit(pf_num);
++
++ *pPORTHIO_MASKA_CLEAR = mask;
++ *pPORTHIO_MASKB_CLEAR = mask;
++ *pPORTH_FER &= ~mask;
++ SSYNC();
++ if (dir)
++ {
++ *pPORTHIO_INEN &= ~mask;
++ if (initial_val > 0)
++ *pPORTHIO_SET = mask;
++ else if (initial_val == 0)
++ *pPORTHIO_CLEAR = mask;
++ *pPORTHIO_DIR |= mask;
++ *pPORTHIO_POLAR &= ~mask;
++ *pPORTHIO_EDGE &= ~mask;
++ *pPORTHIO_BOTH &= ~mask;
++ }
++ else
++ {
++ *pPORTHIO_DIR &= ~mask;
++ *pPORTHIO_POLAR &= ~mask;
++ *pPORTHIO_EDGE &= ~mask;
++ *pPORTHIO_BOTH &= ~mask;
++ *pPORTHIO_INEN |= mask;
++ }
++ SSYNC();
++}
++
++int
++Metro_set_pfx_dir(int pf_num, int dir, int initial_val)
++{
++ unsigned long flags;
++
++ if (pf_num < 0 || pf_num >= 48 || dir < 0 || dir > 1)
++ {
++ return -1;
++ }
++
++ local_irq_save(flags);
++ if (pf_num < 16)
++ {
++ Metro_set_portF_pfx_dir(pf_num, dir, initial_val);
++ }
++ else if (pf_num < 32)
++ {
++ Metro_set_portG_pfx_dir(pf_num, dir, initial_val);
++ }
++ else
++ {
++ Metro_set_portH_pfx_dir(pf_num, dir, initial_val);
++ }
++ local_irq_restore(flags);
++
++ return 0;
++}
++
++#elif (defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) || \
++ defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) )
++
++int
++Metro_set_pfx_dir(int pf_num, int dir, int initial_val)
++{
++ unsigned long flags;
++ unsigned short mask;
++
++ if (pf_num < 0 || pf_num >= 16 || dir < 0 || dir > 1)
++ {
++ return -1;
++ }
++
++ mask = PF_bit(pf_num);
++ local_irq_save(flags);
++
++ *pFIO_MASKA_C = mask;
++ *pFIO_MASKB_C = mask;
++
++ if (dir)
++ { /* Output */
++ *pFIO_INEN &= ~mask;
++ if (initial_val > 0)
++ *pFIO_FLAG_S = mask;
++ else if (initial_val == 0)
++ *pFIO_FLAG_C = mask;
++ *pFIO_DIR |= mask;
++ *pFIO_POLAR &= ~mask;
++ *pFIO_EDGE &= ~mask;
++ *pFIO_BOTH &= ~mask;
++ }
++ else
++ { /* Input */
++ *pFIO_DIR &= ~mask;
++ *pFIO_POLAR &= ~mask;
++ *pFIO_EDGE &= ~mask;
++ *pFIO_BOTH &= ~mask;
++ *pFIO_INEN |= mask;
++ }
++
++ SSYNC();
++ local_irq_restore(flags);
++ return 0;
++}
++
++#else
++#error "undefined platform!!!"
++#endif
++
++
++#if (defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) || \
++ defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) )
++
++/*
++ * Return value:
++ * <0: error
++ * 0: input
++ * 1: output
++ */
++int
++Metro_get_pfx_dir(int pf_num)
++{
++ unsigned short mask = PF_bit(pf_num);
++
++ if (pf_num < 0 || pf_num >= 48)
++ {
++ return -1;
++ }
++
++ if (pf_num < 16)
++ {
++ if (*pPORTF_FER & mask)
++ return -1;
++
++ return (*pPORTFIO_DIR & mask ? 1 : 0);
++ }
++ else if (pf_num < 32)
++ {
++ if (*pPORTG_FER & mask)
++ return -1;
++
++ return (*pPORTGIO_DIR & mask ? 1 : 0);
++ }
++ else
++ {
++ if (*pPORTH_FER & mask)
++ return -1;
++
++ return (*pPORTHIO_DIR & mask ? 1 : 0);
++ }
++}
++
++#elif (defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) || \
++ defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) )
++
++
++/*
++ * Return value:
++ * <0: error
++ * 0: input
++ * 1: output
++ */
++int
++Metro_get_pfx_dir(int pf_num)
++{
++ if (pf_num < 0 || pf_num >= 16)
++ {
++ return -1;
++ }
++ return (*pFIO_DIR & PF_bit(pf_num) ? 1 : 0);
++}
++
++#endif
++
++int
++set_pfx_dir(int pf_num, int dir)
++{
++ return Metro_set_pfx_dir(pf_num, dir, -1);
++}
++
++int
++get_pfx_dir(int pf_num)
++{
++ return Metro_get_pfx_dir(pf_num);
++}
++
++int
++get_pfx_level(int pf_num)
++{
++#if (defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) || \
++ defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) )
++ if (pf_num < 0 || pf_num >= 48)
++ {
++ return -1;
++ }
++#elif (defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) || \
++ defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) )
++
++ if (pf_num < 0 || pf_num >= 16)
++ {
++ return -1;
++ }
++#endif
++
++ return Metro_get_pfx_level(pf_num);
++}
++
++int
++set_pfx_level(int pf_num, int level)
++{
++#if (defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) || \
++ defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) )
++
++ if (pf_num < 0 || pf_num >= 48 || level < 0 || level > 1)
++ {
++ return -1;
++ }
++#elif (defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) || \
++ defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) )
++
++ if (pf_num < 0 || pf_num >= 16 || level < 0 || level > 1)
++ {
++ return -1;
++ }
++#endif
++
++ Metro_set_pfx_level(pf_num, level);
++ return 0;
++}
+diff --git a/u-boot-1.1.6/cpu/blackfin/i2c.c b/u-boot-1.1.6/cpu/blackfin/i2c.c
+index 0524680..8eaf509 100644
+--- a/u-boot-1.1.6/cpu/blackfin/i2c.c
++++ b/u-boot-1.1.6/cpu/blackfin/i2c.c
+@@ -14,6 +14,7 @@
+
+ #include <asm/blackfin.h>
+ #include <asm/mach-common/bits/twi.h>
++#if defined DEBUG_I2C
+
+ #define debugi(fmt, args...) \
+ debug( \
+@@ -22,6 +23,10 @@
+ bfin_read_TWI_MASTER_STAT(), bfin_read_TWI_FIFO_STAT(), bfin_read_TWI_INT_STAT(), \
+ __func__, __LINE__, ## args)
+
++#else
++#define debugi(fmt, args...)
++#endif
++
+ #ifdef TWI0_CLKDIV
+ #define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val)
+ #define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val)
+@@ -126,14 +131,18 @@ static int wait_for_completion(struct i2c_msg *msg)
+ *
+ * @return: 0 if things worked, non-0 if things failed
+ */
+-static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags)
++int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags)
+ {
++#if (0)
+ uchar addr_buffer[] = {
+ (addr >> 0),
+ (addr >> 8),
+ (addr >> 16),
+ };
+- struct i2c_msg msg = {
++#else
++ uchar addr_buffer[3 + 256];
++#endif
++ struct i2c_msg msg = {
+ .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
+ .buf = buffer,
+ .len = len,
+@@ -141,8 +150,29 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len,
+ .alen = alen,
+ };
+ int ret;
+-
+- memset(buffer, 0xff, len);
++ int i;
++
++ addr_buffer[0] = (addr >> 0);
++ addr_buffer[0] = (addr >> 8);
++ addr_buffer[0] = (addr >> 16);
++
++ if (flags == 0) /* write operation */
++ {
++ if (len > 255)
++ {
++ len = 255;
++ }
++
++ msg.alen = alen + len;
++ msg.len = 0;
++
++ for (i = 0; i < len; i++)
++ {
++ addr_buffer[alen + i] = buffer[i];
++ }
++ }
++
++//??? memset(buffer, 0xff, len);
+ debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ",
+ chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr"));
+
+diff --git a/u-boot-1.1.6/cpu/blackfin/serial.c b/u-boot-1.1.6/cpu/blackfin/serial.c
+index f7b935d..1e5ebda 100644
+--- a/u-boot-1.1.6/cpu/blackfin/serial.c
++++ b/u-boot-1.1.6/cpu/blackfin/serial.c
+@@ -41,6 +41,7 @@
+ */
+
+ #include <common.h>
++#include <config.h>
+ #include <watchdog.h>
+ #include <asm/blackfin.h>
+ #include <asm/mach-common/bits/uart.h>
+@@ -51,6 +52,28 @@
+
+ #include "serial.h"
+
++
++#include <Metrologic_Hardware.h>
++#include <metro_pf.h>
++
++extern int Get_Interface_Board_Type(void);
++extern int get_pfx_level(int pf_num);
++extern int set_pfx_level(int pf_num, int level);
++
++#define SET_PIN(gpio_pin) { set_pfx_level(gpio_pin, 1); }
++#define CLR_PIN(gpio_pin) { set_pfx_level(gpio_pin, 0); }
++#define GET_PIN_LEVEL(gpio_pin) ( get_pfx_level(gpio_pin) )
++
++#ifdef CONFIG_SUPPORT_BLUETOOTH
++static int bt_state = 0;
++#endif
++static int cmdline_active = 0;
++
++void set_cmdline_active(int active)
++{
++ cmdline_active = active;
++}
++
+ #ifdef CONFIG_DEBUG_SERIAL
+ uint16_t cached_lsr[256];
+ uint16_t cached_rbr[256];
+@@ -114,6 +137,14 @@ int serial_init(void)
+
+ void serial_putc(const char c)
+ {
++#ifdef CONFIG_SUPPORT_BLUETOOTH
++ if (Get_Interface_Board_Type() == BLUETOOTH_BOARD && bt_state == 0)
++ {
++ WATCHDOG_RESET();
++ return;
++ }
++#endif
++
+ /* send a \r for compatibility */
+ if (c == '\n')
+ serial_putc('\r');
+@@ -138,16 +169,67 @@ void serial_putc(const char c)
+ int serial_tstc(void)
+ {
+ WATCHDOG_RESET();
++#ifdef CONFIG_SUPPORT_BLUETOOTH
++ {
++ int bt_pin_level;
++ int board_type = Get_Interface_Board_Type();
++
++ if(board_type == BLUETOOTH_BOARD && cmdline_active == 1)
++ {
++ bt_pin_level = GET_PIN_LEVEL(BT_CONN_PIN);
++ if (bt_state == 0 && bt_pin_level == 1)
++ {
++ bt_state = 1;
++ SET_PIN(BLUE_LED_PIN);
++ udelay(500000);
++ WATCHDOG_RESET();
++ }
++ if (bt_state == 1 && bt_pin_level == 0)
++ {
++ bt_state = 0;
++ CLR_PIN(BLUE_LED_PIN);
++ udelay(500000);
++ WATCHDOG_RESET();
++ }
++ }
++ }
++#endif
++
+ return (uart_lsr_read() & DR) ? 1 : 0;
+ }
+
+ int serial_getc(void)
+ {
+ uint16_t uart_rbr_val;
++#ifdef CONFIG_SUPPORT_BLUETOOTH
++ int board_type = Get_Interface_Board_Type();
++ int bt_pin_level;
++#endif
++
+
+ /* wait for data ! */
+ while (!serial_tstc())
++ {
++#ifdef CONFIG_SUPPORT_BLUETOOTH
++ if(board_type == BLUETOOTH_BOARD && cmdline_active == 1)
++ {
++ bt_pin_level = GET_PIN_LEVEL(BT_CONN_PIN);
++ if (bt_state == 0 && bt_pin_level == 1)
++ {
++ bt_state = 1;
++ SET_PIN(BLUE_LED_PIN);
++ udelay(500000);
++ }
++ if (bt_state == 1 && bt_pin_level == 0)
++ {
++ bt_state = 0;
++ CLR_PIN(BLUE_LED_PIN);
++ udelay(500000);
++ }
++ }
++#endif
+ continue;
++ }
+
+ /* grab the new byte */
+ uart_rbr_val = *pUART_RBR;
+diff --git a/u-boot-1.1.6/examples/Makefile b/u-boot-1.1.6/examples/Makefile
+index 75753a2..85df974 100644
+--- a/u-boot-1.1.6/examples/Makefile
++++ b/u-boot-1.1.6/examples/Makefile
+@@ -89,9 +89,23 @@ BIN += sched.bin
+ endif
+
+ ifeq ($(ARCH),blackfin)
++
++ifneq ($(BOARD),bf537-stamp)
++ifneq ($(BOARD),bf533-stamp)
++ifneq ($(BOARD),Focus)
++ifneq ($(BOARD),Orbit3)
++ifneq ($(BOARD),VuQuest2D)
++
+ ELF += smc91111_eeprom smsc9118_eeprom
+ SREC += smc91111_eeprom.srec smsc9118_eeprom.srec
+ BIN += smc91111_eeprom.bin smsc9118_eeprom.bin
++
++endif # VuQuest2D
++endif # Orbit3
++endif # Focus
++endif # bf533-stamp
++endif # bf537-stamp
++
+ endif
+
+ # The following example is pretty 8xx specific...
+diff --git a/u-boot-1.1.6/include/Metrologic_Hardware.h b/u-boot-1.1.6/include/Metrologic_Hardware.h
+new file mode 100644
+index 0000000..19506af
+--- /dev/null
++++ b/u-boot-1.1.6/include/Metrologic_Hardware.h
+@@ -0,0 +1,69 @@
++#ifndef METROLOGIC_HARDWARE_H
++#define METROLOGIC_HARDWARE_H
++
++#define PADDING_CHAR 0xff
++#define SPI_SECTOR_SIZE 0x10000
++#define PADDING_BUFF_SIZE SPI_SECTOR_SIZE
++
++#define U_BOOT_START_OFFS 0x000000
++#define CONFIG_START_OFFS 0x040000
++#define KERNEL_START_OFFS 0x060000
++#define FILSYS_START_OFFS 0x100000
++
++#define FLASH_PARTITION_START 0x20000000
++
++#define U_BOOT_START_ADDR ( U_BOOT_START_OFFS + FLASH_PARTITION_START)
++#define CONFIG_START_ADDR ( CONFIG_START_OFFS + FLASH_PARTITION_START)
++#define KERNEL_START_ADDR ( KERNEL_START_OFFS + FLASH_PARTITION_START)
++#define FILSYS_START_ADDR ( FILSYS_START_OFFS + FLASH_PARTITION_START)
++
++#define NOVRAM_SIGNATURE "MTLG FOCUS TK 04"
++#define NOVRAM_SIGNATURE_LEN 16
++#define NOVRAMSIZE 512
++
++
++#define NUM_RETRIES_ON_XFER 3
++#define PSOC_COMMAND_DELAY_USEC 100
++#define PSOC_COMMAND_TIMEOUT_USEC 1000
++
++#define PSOC_CHIP_ADDR 0x71
++
++
++#define INTERFACE_TYPE_TITLE "Interface Board:"
++#define INTERFACE_RS232_TEXT "RS232"
++#define INTERFACE_KBW_TEXT "Keyboard Wedge"
++#define INTERFACE_IBM_TEXT "IBM"
++#define INTERFACE_OCIA_TEXT "OCIA"
++#define INTERFACE_LSUSBHID_TEXT "USB-HID"
++#define INTERFACE_LSUSBPOS_TEXT "USB-POS"
++#define INTERFACE_FSUSB_TEXT "FS-USB"
++#define INTERFACE_BLUETOOTH_TEXT "BlueTooth"
++#define INTERFACE_MULTIFUN_USB_IBM_TEXT "MultiFunction"
++#define INTERFACE_UNKNOWN_TEXT "Unknown"
++
++#define UNKNOWN_INTERFACE_BOARD 999
++
++enum {
++ RS232_BOARD = 0,
++ KBW_BOARD,
++ LASER_EMULATION_BOARD,
++ IBM_BOARD,
++ OCIA_BOARD,
++ LS_USB_HID_BOARD,
++ LS_USB_POS_BOARD,
++ FS_USB_BOARD,
++ BLUETOOTH_BOARD,
++ MULTIFUN_IBM_USB_BOARD,
++ NUM_SUPPORTED_INTERFACE_BOARD
++};
++
++typedef struct {
++ int board_type;
++ int AtoD_low;
++ int AtoD_high;
++} BOARD_FEATURE;
++
++extern BOARD_FEATURE board_desc[];
++
++
++#endif /* METROLOGIC_HARDWARE_H */
+diff --git a/u-boot-1.1.6/include/asm-blackfin/blackfin-config-post.h b/u-boot-1.1.6/include/asm-blackfin/blackfin-config-post.h
+index 0ad4715..ec5bc5d 100644
+--- a/u-boot-1.1.6/include/asm-blackfin/blackfin-config-post.h
++++ b/u-boot-1.1.6/include/asm-blackfin/blackfin-config-post.h
+@@ -9,55 +9,7 @@
+ #ifndef __ASM_BLACKFIN_CONFIG_POST_H__
+ #define __ASM_BLACKFIN_CONFIG_POST_H__
+
+-/* Sanity check CONFIG_BFIN_CPU */
+-#ifndef CONFIG_BFIN_CPU
+-# error CONFIG_BFIN_CPU: your board config needs to define this
+-#endif
+-
+-/* Make sure the structure is properly aligned */
+-#if ((CFG_GBL_DATA_ADDR & -4) != CFG_GBL_DATA_ADDR)
+-# error CFG_GBL_DATA_ADDR: must be 4 byte aligned
+-#endif
+-
+-/* Set default CONFIG_VCO_HZ if need be */
+-#if !defined(CONFIG_VCO_HZ)
+-# if (CONFIG_CLKIN_HALF == 0)
+-# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
+-# else
+-# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2)
+-# endif
+-#endif
+-
+-/* Set default CONFIG_CCLK_HZ if need be */
+-#if !defined(CONFIG_CCLK_HZ)
+-# if (CONFIG_PLL_BYPASS == 0)
+-# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV)
+-# else
+-# define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
+-# endif
+-#endif
+-
+-/* Set default CONFIG_SCLK_HZ if need be */
+-#if !defined(CONFIG_SCLK_HZ)
+-# if (CONFIG_PLL_BYPASS == 0)
+-# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV)
+-# else
+-# define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
+-# endif
+-#endif
+-
+-/* Since we use these to program PLL registers directly,
+- * make sure the values are sane and won't screw us up.
+- */
+-#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT
+-# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63)
+-#endif
+-#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF
+-# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1
+-#endif
+-#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS
+-# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1
+-#endif
++#include <asm/blackfin_clocks.h>
+
+ /* Using L1 scratch pad makes sense for everyone by default. */
+ #ifndef CMD_LINE_ADDR
+diff --git a/u-boot-1.1.6/include/asm-blackfin/blackfin_clocks.h b/u-boot-1.1.6/include/asm-blackfin/blackfin_clocks.h
+new file mode 100644
+index 0000000..67c7709
+--- /dev/null
++++ b/u-boot-1.1.6/include/asm-blackfin/blackfin_clocks.h
+@@ -0,0 +1,56 @@
++#ifndef __ASM_BLACKFIN_CLOCKS_H__
++#define __ASM_BLACKFIN_CLOCKS_H__
++
++/* Sanity check CONFIG_BFIN_CPU */
++#ifndef CONFIG_BFIN_CPU
++# error CONFIG_BFIN_CPU: your board config needs to define this
++#endif
++
++/* Set default CONFIG_CCLK_HZ if need be */
++#if !defined(CONFIG_CCLK_HZ)
++# if (CONFIG_PLL_BYPASS == 0)
++# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV)
++# else
++# define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
++# endif
++#endif
++
++/* Set default CONFIG_SCLK_HZ if need be */
++#if !defined(CONFIG_SCLK_HZ)
++# if (CONFIG_PLL_BYPASS == 0)
++# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV)
++# else
++# define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
++# endif
++#endif
++
++/* Since we use these to program PLL registers directly,
++ * make sure the values are sane and won't screw us up.
++ */
++#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT
++# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63)
++#endif
++#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF
++# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1
++#endif
++#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS
++# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1
++#endif
++
++/* Make sure the structure is properly aligned */
++#if ((CFG_GBL_DATA_ADDR & -4) != CFG_GBL_DATA_ADDR)
++# error CFG_GBL_DATA_ADDR: must be 4 byte aligned
++#endif
++
++/* Set default CONFIG_VCO_HZ if need be */
++#if !defined(CONFIG_VCO_HZ)
++# if (CONFIG_CLKIN_HALF == 0)
++# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
++# else
++# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2)
++# endif
++#endif
++
++#endif /* __ASM_BLACKFIN_CLOCKS_H__ */
++
++
+diff --git a/u-boot-1.1.6/include/asm-blackfin/mem_init.h b/u-boot-1.1.6/include/asm-blackfin/mem_init.h
+new file mode 100644
+index 0000000..e413aae
+--- /dev/null
++++ b/u-boot-1.1.6/include/asm-blackfin/mem_init.h
+@@ -0,0 +1,338 @@
++#ifndef __ASM_MEM_INIT_H__
++#define __ASM_MEM_INIT_H__
++/*
++ * U-boot - mem_init.h Header file for memory initialization
++ *
++ * Copyright (c) 2005 blackfin.uclinux.org
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <asm/blackfin_clocks.h>
++
++#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \
++ CONFIG_MEM_MT48LC64M4A2FB_7E || \
++ CONFIG_MEM_MT48LC16M8A2TG_75 || \
++ CONFIG_MEM_MT48LC8M16A2TG_7E || \
++ CONFIG_MEM_MT48LC8M32B2B5_7 || \
++ CONFIG_MEM_MT48LC32M8A2_75 || \
++ CONFIG_MEM_IS42S16160B_7 \
++ )
++
++ #if ( CONFIG_SCLK_HZ > 119402985 )
++ #define SDRAM_tRP TRP_2
++ #define SDRAM_tRP_num 2
++ #define SDRAM_tRAS TRAS_7
++ #define SDRAM_tRAS_num 7
++ #define SDRAM_tRCD TRCD_2
++ #define SDRAM_tWR TWR_2
++ #endif
++ #if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 )
++ #define SDRAM_tRP TRP_2
++ #define SDRAM_tRP_num 2
++ #define SDRAM_tRAS TRAS_6
++ #define SDRAM_tRAS_num 6
++ #define SDRAM_tRCD TRCD_2
++ #define SDRAM_tWR TWR_2
++ #endif
++ #if ( CONFIG_SCLK_HZ > 89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 )
++ #define SDRAM_tRP TRP_2
++ #define SDRAM_tRP_num 2
++ #define SDRAM_tRAS TRAS_5
++ #define SDRAM_tRAS_num 5
++ #define SDRAM_tRCD TRCD_2
++ #define SDRAM_tWR TWR_2
++ #endif
++ #if ( CONFIG_SCLK_HZ > 74626866 ) && ( CONFIG_SCLK_HZ <= 89552239 )
++ #define SDRAM_tRP TRP_2
++ #define SDRAM_tRP_num 2
++ #define SDRAM_tRAS TRAS_4
++ #define SDRAM_tRAS_num 4
++ #define SDRAM_tRCD TRCD_2
++ #define SDRAM_tWR TWR_2
++ #endif
++ #if ( CONFIG_SCLK_HZ > 66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 )
++ #define SDRAM_tRP TRP_2
++ #define SDRAM_tRP_num 2
++ #define SDRAM_tRAS TRAS_3
++ #define SDRAM_tRAS_num 3
++ #define SDRAM_tRCD TRCD_2
++ #define SDRAM_tWR TWR_2
++ #endif
++ #if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
++ #define SDRAM_tRP TRP_1
++ #define SDRAM_tRP_num 1
++ #define SDRAM_tRAS TRAS_3
++ #define SDRAM_tRAS_num 3
++ #define SDRAM_tRCD TRCD_1
++ #define SDRAM_tWR TWR_2
++ #endif
++ #if ( CONFIG_SCLK_HZ > 44776119 ) && ( CONFIG_SCLK_HZ <= 59701493 )
++ #define SDRAM_tRP TRP_1
++ #define SDRAM_tRP_num 1
++ #define SDRAM_tRAS TRAS_3
++ #define SDRAM_tRAS_num 3
++ #define SDRAM_tRCD TRCD_1
++ #define SDRAM_tWR TWR_2
++ #endif
++ #if ( CONFIG_SCLK_HZ > 29850746 ) && ( CONFIG_SCLK_HZ <= 44776119 )
++ #define SDRAM_tRP TRP_1
++ #define SDRAM_tRP_num 1
++ #define SDRAM_tRAS TRAS_2
++ #define SDRAM_tRAS_num 2
++ #define SDRAM_tRCD TRCD_1
++ #define SDRAM_tWR TWR_2
++ #endif
++ #if ( CONFIG_SCLK_HZ <= 29850746 )
++ #define SDRAM_tRP TRP_1
++ #define SDRAM_tRP_num 1
++ #define SDRAM_tRAS TRAS_1
++ #define SDRAM_tRAS_num 1
++ #define SDRAM_tRCD TRCD_1
++ #define SDRAM_tWR TWR_2
++ #endif
++#endif
++
++#if (CONFIG_MEM_IS42S16160B_7)
++ /*SDRAM INFORMATION: */
++ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
++ #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
++ #define SDRAM_CL CL_2
++#endif
++
++#if (CONFIG_MEM_MT48LC16M16A2TG_75)
++ /*SDRAM INFORMATION: */
++ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
++ #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
++ #define SDRAM_CL CL_3
++#endif
++
++#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
++ /*SDRAM INFORMATION: */
++ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
++ #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
++ #define SDRAM_CL CL_2
++#endif
++
++#if (CONFIG_MEM_MT48LC16M8A2TG_75)
++ /*SDRAM INFORMATION: */
++ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
++ #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
++ #define SDRAM_CL CL_3
++#endif
++
++#if (CONFIG_MEM_MT48LC32M8A2_75)
++ /*SDRAM INFORMATION: */
++#define SDRAM_Tref 64 /* Refresh period in milliseconds */
++#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
++#define SDRAM_CL CL_3
++#endif
++
++#if (CONFIG_MEM_MT48LC8M16A2TG_7E)
++ /*SDRAM INFORMATION: */
++ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
++ #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
++ #define SDRAM_CL CL_2
++#endif
++
++#if (CONFIG_MEM_MT48LC8M32B2B5_7)
++ /*SDRAM INFORMATION: */
++ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
++ #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
++ #define SDRAM_CL CL_3
++#endif
++
++#if ( CONFIG_MEM_SIZE == 128 )
++ #define SDRAM_SIZE EBSZ_128
++#endif
++#if ( CONFIG_MEM_SIZE == 64 )
++ #define SDRAM_SIZE EBSZ_64
++#endif
++#if ( CONFIG_MEM_SIZE == 32 )
++ #define SDRAM_SIZE EBSZ_32
++#endif
++#if ( CONFIG_MEM_SIZE == 16 )
++ #define SDRAM_SIZE EBSZ_16
++#endif
++#if ( CONFIG_MEM_ADD_WDTH == 11 )
++ #define SDRAM_WIDTH EBCAW_11
++#endif
++#if ( CONFIG_MEM_ADD_WDTH == 10 )
++ #define SDRAM_WIDTH EBCAW_10
++#endif
++#if ( CONFIG_MEM_ADD_WDTH == 9 )
++ #define SDRAM_WIDTH EBCAW_9
++#endif
++#if ( CONFIG_MEM_ADD_WDTH == 8 )
++ #define SDRAM_WIDTH EBCAW_8
++#endif
++
++#define mem_SDBCTL SDRAM_WIDTH | SDRAM_SIZE | EBE
++
++/* Equation from section 17 (p17-46) of BF533 HRM */
++#define mem_SDRRC ((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
++
++/* Enable SCLK Out */
++#define mem_SDGCTL ( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS )
++
++#define flash_EBIU_AMBCTL_WAT ( ( CONFIG_FLASH_SPEED_BWAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
++#define flash_EBIU_AMBCTL_RAT ( ( CONFIG_FLASH_SPEED_BRAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
++#define flash_EBIU_AMBCTL_HT ( ( CONFIG_FLASH_SPEED_BHT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) )
++#define flash_EBIU_AMBCTL_ST ( ( CONFIG_FLASH_SPEED_BST * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
++#define flash_EBIU_AMBCTL_TT ( ( CONFIG_FLASH_SPEED_BTT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
++
++#if (flash_EBIU_AMBCTL_TT > 3 )
++ #define flash_EBIU_AMBCTL0_TT B0TT_4
++#endif
++#if (flash_EBIU_AMBCTL_TT == 3 )
++ #define flash_EBIU_AMBCTL0_TT B0TT_3
++#endif
++#if (flash_EBIU_AMBCTL_TT == 2 )
++ #define flash_EBIU_AMBCTL0_TT B0TT_2
++#endif
++#if (flash_EBIU_AMBCTL_TT < 2 )
++ #define flash_EBIU_AMBCTL0_TT B0TT_1
++#endif
++
++#if (flash_EBIU_AMBCTL_ST > 3 )
++ #define flash_EBIU_AMBCTL0_ST B0ST_4
++#endif
++#if (flash_EBIU_AMBCTL_ST == 3 )
++ #define flash_EBIU_AMBCTL0_ST B0ST_3
++#endif
++#if (flash_EBIU_AMBCTL_ST == 2 )
++ #define flash_EBIU_AMBCTL0_ST B0ST_2
++#endif
++#if (flash_EBIU_AMBCTL_ST < 2 )
++ #define flash_EBIU_AMBCTL0_ST B0ST_1
++#endif
++
++#if (flash_EBIU_AMBCTL_HT > 2 )
++ #define flash_EBIU_AMBCTL0_HT B0HT_3
++#endif
++#if (flash_EBIU_AMBCTL_HT == 2 )
++ #define flash_EBIU_AMBCTL0_HT B0HT_2
++#endif
++#if (flash_EBIU_AMBCTL_HT == 1 )
++ #define flash_EBIU_AMBCTL0_HT B0HT_1
++#endif
++#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
++ #define flash_EBIU_AMBCTL0_HT B0HT_0
++#endif
++#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
++ #define flash_EBIU_AMBCTL0_HT B0HT_1
++#endif
++
++#if (flash_EBIU_AMBCTL_WAT > 14)
++ #define flash_EBIU_AMBCTL0_WAT B0WAT_15
++#endif
++#if (flash_EBIU_AMBCTL_WAT == 14)
++ #define flash_EBIU_AMBCTL0_WAT B0WAT_14
++#endif
++#if (flash_EBIU_AMBCTL_WAT == 13)
++ #define flash_EBIU_AMBCTL0_WAT B0WAT_13
++#endif
++#if (flash_EBIU_AMBCTL_WAT == 12)
++ #define flash_EBIU_AMBCTL0_WAT B0WAT_12
++#endif
++#if (flash_EBIU_AMBCTL_WAT == 11)
++ #define flash_EBIU_AMBCTL0_WAT B0WAT_11
++#endif
++#if (flash_EBIU_AMBCTL_WAT == 10)
++ #define flash_EBIU_AMBCTL0_WAT B0WAT_10
++#endif
++#if (flash_EBIU_AMBCTL_WAT == 9)
++ #define flash_EBIU_AMBCTL0_WAT B0WAT_9
++#endif
++#if (flash_EBIU_AMBCTL_WAT == 8)
++ #define flash_EBIU_AMBCTL0_WAT B0WAT_8
++#endif
++#if (flash_EBIU_AMBCTL_WAT == 7)
++ #define flash_EBIU_AMBCTL0_WAT B0WAT_7
++#endif
++#if (flash_EBIU_AMBCTL_WAT == 6)
++ #define flash_EBIU_AMBCTL0_WAT B0WAT_6
++#endif
++#if (flash_EBIU_AMBCTL_WAT == 5)
++ #define flash_EBIU_AMBCTL0_WAT B0WAT_5
++#endif
++#if (flash_EBIU_AMBCTL_WAT == 4)
++ #define flash_EBIU_AMBCTL0_WAT B0WAT_4
++#endif
++#if (flash_EBIU_AMBCTL_WAT == 3)
++ #define flash_EBIU_AMBCTL0_WAT B0WAT_3
++#endif
++#if (flash_EBIU_AMBCTL_WAT == 2)
++ #define flash_EBIU_AMBCTL0_WAT B0WAT_2
++#endif
++#if (flash_EBIU_AMBCTL_WAT == 1)
++ #define flash_EBIU_AMBCTL0_WAT B0WAT_1
++#endif
++
++#if (flash_EBIU_AMBCTL_RAT > 14)
++ #define flash_EBIU_AMBCTL0_RAT B0RAT_15
++#endif
++#if (flash_EBIU_AMBCTL_RAT == 14)
++ #define flash_EBIU_AMBCTL0_RAT B0RAT_14
++#endif
++#if (flash_EBIU_AMBCTL_RAT == 13)
++ #define flash_EBIU_AMBCTL0_RAT B0RAT_13
++#endif
++#if (flash_EBIU_AMBCTL_RAT == 12)
++ #define flash_EBIU_AMBCTL0_RAT B0RAT_12
++#endif
++#if (flash_EBIU_AMBCTL_RAT == 11)
++ #define flash_EBIU_AMBCTL0_RAT B0RAT_11
++#endif
++#if (flash_EBIU_AMBCTL_RAT == 10)
++ #define flash_EBIU_AMBCTL0_RAT B0RAT_10
++#endif
++#if (flash_EBIU_AMBCTL_RAT == 9)
++ #define flash_EBIU_AMBCTL0_RAT B0RAT_9
++#endif
++#if (flash_EBIU_AMBCTL_RAT == 8)
++ #define flash_EBIU_AMBCTL0_RAT B0RAT_8
++#endif
++#if (flash_EBIU_AMBCTL_RAT == 7)
++ #define flash_EBIU_AMBCTL0_RAT B0RAT_7
++#endif
++#if (flash_EBIU_AMBCTL_RAT == 6)
++ #define flash_EBIU_AMBCTL0_RAT B0RAT_6
++#endif
++#if (flash_EBIU_AMBCTL_RAT == 5)
++ #define flash_EBIU_AMBCTL0_RAT B0RAT_5
++#endif
++#if (flash_EBIU_AMBCTL_RAT == 4)
++ #define flash_EBIU_AMBCTL0_RAT B0RAT_4
++#endif
++#if (flash_EBIU_AMBCTL_RAT == 3)
++ #define flash_EBIU_AMBCTL0_RAT B0RAT_3
++#endif
++#if (flash_EBIU_AMBCTL_RAT == 2)
++ #define flash_EBIU_AMBCTL0_RAT B0RAT_2
++#endif
++#if (flash_EBIU_AMBCTL_RAT == 1)
++ #define flash_EBIU_AMBCTL0_RAT B0RAT_1
++#endif
++
++
++//#define flash_EBIU_AMBCTL0 flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN
++#define CONFIG_FLASH_SPEED_RDYEN 0
++#define flash_EBIU_AMBCTL0 flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN
++
++#endif
+diff --git a/u-boot-1.1.6/include/configs/Focus.h b/u-boot-1.1.6/include/configs/Focus.h
+new file mode 100644
+index 0000000..e56c362
+--- /dev/null
++++ b/u-boot-1.1.6/include/configs/Focus.h
+@@ -0,0 +1,381 @@
++/*
++ * U-boot - Configuration file for BF537 STAMP board
++ */
++
++#ifndef __CONFIG_FOCUS_H__
++#define __CONFIG_FOCUS_H__
++
++#include <asm/blackfin-config-pre.h>
++
++
++#ifndef __ADSPBF534__
++#define __ADSPBF534__
++#endif
++#define METROLOGIC_PLATFORM "Focus"
++#define SUPPORT_NETWORKING 0
++#define CONFIG_SILENT_CONSOLE 1
++#define CONFIG_BAUDRATE 115200
++#define CONFIG_LOADADDR 0x800000
++
++//#define METROLOGIC_FLASH_BOOT_ENV_PARAM "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
++
++#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
++ "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
++
++#define CFG_PROMPT "bootldr> "
++#define CONFIG_ZERO_BOOTDELAY_CHECK
++#define CONFIG_AUTOBOOT_KEYED 1
++#define CONFIG_AUTOBOOT_STOP_STR "\033"
++#define CONFIG_MEM_MT48LC16M16A2TG_75 1
++//#define CONFIG_MEM_IS42S16160B_7 1
++
++//#define CONFIG_DEBUG_EARLY_SERIAL 1
++//#define DEBUG_BOOTKEYS 1
++//#define DEBUG 1
++//#define DEBUG_METRO_IO 1
++//#define DEBUG_I2C 1
++
++// We don't have a parallel flash chip there
++#define CFG_NO_FLASH
++
++
++ /*
++ * Processor Settings
++ */
++#define CONFIG_BFIN_CPU bf534-0.2
++#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
++
++
++/*
++ * Clock Settings
++ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
++ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
++ */
++/* CONFIG_CLKIN_HZ is any value in Hz */
++#define CONFIG_CLKIN_HZ 25000000
++/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
++/* 1 = CLKIN / 2 */
++#define CONFIG_CLKIN_HALF 0
++/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
++/* 1 = bypass PLL */
++#define CONFIG_PLL_BYPASS 0
++/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
++/* Values can range from 0-63 (where 0 means 64) */
++#define CONFIG_VCO_MULT 20
++/* CCLK_DIV controls the core clock divider */
++/* Values can be 1, 2, 4, or 8 ONLY */
++#define CONFIG_CCLK_DIV 1
++/* SCLK_DIV controls the system clock divider */
++/* Values can range from 1-15 */
++#define CONFIG_SCLK_DIV 4
++
++
++/*
++ * Memory Settings
++ */
++#define CONFIG_MEM_ADD_WDTH 9
++#define CONFIG_MEM_SIZE 32
++
++//#define CONFIG_EBIU_SDRRC_VAL 0x306
++//#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
++//#define CONFIG_EBIU_SDBCTL_VAL (EBSZ_64 | EBCAW_10 | EBE)
++
++#define CONFIG_EBIU_AMGCTL_VAL 0xFF
++//#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
++#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
++
++#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for monitor */
++#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 384 kB for malloc() (video/spi are big) */
++#define CFG_GBL_DATA_SIZE 0x4000
++
++
++/*
++ * Network Settings
++ */
++#if SUPPORT_NETWORKING
++#ifndef __ADSPBF534__
++#define ADI_CMDS_NETWORK 1
++#define CONFIG_BFIN_MAC
++#define CONFIG_NETCONSOLE 1
++#define CONFIG_NET_MULTI 1
++#else
++#define ADI_CMDS_NETWORK 0
++#endif
++#endif
++#define CONFIG_HOSTNAME bf537-stamp
++/* Uncomment next line to use fixed MAC address */
++/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
++
++
++/*
++ * Flash Settings
++ */
++#define CFG_FLASH_BASE 0x20000000
++#define CFG_FLASH_CFI /* The flash is CFI compatible */
++//#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
++//#define CFG_FLASH_PROTECTION
++#define CFG_MAX_FLASH_BANKS 1
++#define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
++#define FLASH_SIZE 0x800000
++#define CFG_FLASH_SIZE 0x800000
++
++
++#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
++#define CFG_ENV_IS_IN_EEPROM 1
++#define CFG_ENV_OFFSET 0x4000
++#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
++#else
++#define CFG_ENV_IS_IN_FLASH 1
++#define CFG_ENV_ADDR 0x20004000
++#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
++#endif
++#define CFG_ENV_SIZE 0x2000
++#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
++#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
++#define ENV_IS_EMBEDDED
++#else
++#define ENV_IS_EMBEDDED_CUSTOM
++#endif
++
++/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
++/* Values can range from 2-65535 */
++/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
++#define CONFIG_SPI
++#define CONFIG_SPI_BAUD 2
++#define CONFIG_SPI_BAUD_INITBLOCK 3
++
++
++/*
++ * I2C Settings
++ */
++#define CONFIG_HARD_I2C 1 /* I2C TWI */
++#define CFG_I2C_SPEED 50000
++#define CFG_I2C_SLAVE 0
++
++
++/*
++ * NAND Settings
++ */
++/* #define CONFIG_BF537_NAND */
++#ifdef CONFIG_BF537_NAND
++# define ADD_NAND_CMD CFG_CMD_NAND
++#else
++# define ADD_NAND_CMD 0
++#endif
++
++#define CFG_NAND_ADDR 0x20212000
++#define CFG_NAND_BASE CFG_NAND_ADDR
++#define CFG_MAX_NAND_DEVICE 1
++#define SECTORSIZE 512
++#define ADDR_COLUMN 1
++#define ADDR_PAGE 2
++#define ADDR_COLUMN_PAGE 3
++#define NAND_ChipID_UNKNOWN 0x00
++#define NAND_MAX_FLOORS 1
++#define NAND_MAX_CHIPS 1
++#define BFIN_NAND_READY PF3
++
++#define NAND_WAIT_READY(nand) \
++ do { \
++ int timeout = 0; \
++ while(!(*pPORTFIO & PF3)) \
++ if (timeout++ > 100000) \
++ break; \
++ } while (0)
++
++#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
++#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
++
++#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
++#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
++#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
++#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
++
++
++/*
++ * CF-CARD IDE-HDD Support
++ */
++/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
++/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
++/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
++
++#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
++# define CONFIG_BFIN_IDE 1
++# define ADD_IDE_CMD CFG_CMD_IDE
++#else
++# define ADD_IDE_CMD 0
++#endif
++
++#if defined(CONFIG_BFIN_IDE)
++
++#define CONFIG_DOS_PARTITION 1
++/*
++ * IDE/ATA stuff
++ */
++#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
++#undef CONFIG_IDE_LED /* no led for ide supported */
++#undef CONFIG_IDE_RESET /* no reset for ide supported */
++
++#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
++#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
++
++#undef CONFIG_EBIU_AMBCTL1_VAL
++#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
++
++#define CONFIG_CF_ATASEL_DIS 0x20311800
++#define CONFIG_CF_ATASEL_ENA 0x20311802
++
++#if defined(CONFIG_BFIN_TRUE_IDE)
++/*
++ * Note that these settings aren't for the most part used in include/ata.h
++ * when all of the ATA registers are setup
++ */
++#define CFG_ATA_BASE_ADDR 0x2031C000
++#define CFG_ATA_IDE0_OFFSET 0x0000
++#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
++#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
++#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
++#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
++#endif /* CONFIG_BFIN_TRUE_IDE */
++
++#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
++#define CFG_ATA_BASE_ADDR 0x20211800
++#define CFG_ATA_IDE0_OFFSET 0x0000
++#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
++#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
++#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
++#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
++#endif /* CONFIG_BFIN_CF_IDE */
++
++#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
++#define CFG_ATA_BASE_ADDR 0x20314000
++#define CFG_ATA_IDE0_OFFSET 0x0000
++#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
++#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
++#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
++#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
++
++#undef CONFIG_SCLK_DIV
++#define CONFIG_SCLK_DIV 8
++#endif /* CONFIG_BFIN_HDD_IDE */
++
++#endif /*CONFIG_BFIN_IDE */
++
++
++/*
++ * Misc Settings
++ */
++#define CONFIG_MISC_INIT_R
++//#define CONFIG_RTC_BFIN
++
++/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
++
++//#define ADI_CMDS_EXTRA (ADD_IDE_CMD | ADD_NAND_CMD)
++
++#define CONFIG_BFIN_COMMANDS \
++ ( CFG_BFIN_CMD_BOOTLDR | \
++ CFG_BFIN_CMD_CPLBINFO )
++
++/* Define if want to do post memory test */
++#undef CONFIG_POST
++#ifdef CONFIG_POST
++#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
++#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
++#endif
++
++/*
++ * Pull in common ADI header for remaining command/environment setup
++ */
++#include <configs/bfin_adi_common.h>
++
++#include <asm/blackfin-config-post.h>
++
++#include <asm/mem_init.h>
++
++
++/* Overrides common ADI header's command/environment setup */
++
++#ifdef CONFIG_BOOTDELAY
++#undef CONFIG_BOOTDELAY
++#endif
++#define CONFIG_BOOTDELAY 10
++
++#ifdef CONFIG_BOOTCOMMAND
++#undef CONFIG_BOOTCOMMAND
++#endif
++#define CONFIG_BOOTCOMMAND "run flashboot"
++
++#ifdef CONFIG_BOOTARGS
++#undef CONFIG_BOOTARGS
++#endif
++#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m lpj=496640"
++
++#ifdef CONFIG_EBIU_SDRRC_VAL
++#undef CONFIG_EBIU_SDRRC_VAL
++#endif
++#define CONFIG_EBIU_SDRRC_VAL mem_SDRRC
++
++#ifdef CONFIG_EBIU_SDGCTL_VAL
++#undef CONFIG_EBIU_SDGCTL_VAL
++#endif
++#define CONFIG_EBIU_SDGCTL_VAL mem_SDGCTL
++
++#ifdef CONFIG_EBIU_SDBCTL_VAL
++#undef CONFIG_EBIU_SDBCTL_VAL
++#endif
++#define CONFIG_EBIU_SDBCTL_VAL mem_SDBCTL
++
++#ifdef CONFIG_EBIU_AMBCTL0_VAL
++#undef CONFIG_EBIU_AMBCTL0_VAL
++#endif
++#define CONFIG_EBIU_AMBCTL0_VAL flash_EBIU_AMBCTL0
++
++#ifdef CFG_AUTOLOAD
++#undef CFG_AUTOLOAD
++#endif
++#define CFG_AUTOLOAD ""
++
++ /* CONFIG_SERIAL_BF537 no longer used*/
++//#define CONFIG_SERIAL_BF537 1
++
++#ifdef CONFIG_POST_TEST
++#undef CONFIG_POST_TEST
++#endif
++
++#define CONFIG_METROLOGIC_IO_INIT 1
++
++#define CONFIG_CORE_VOLTAGE_MILLIVOLT 1250
++#define CONFIG_DISABLE_CLKIN_OUTPUT 1
++
++#define CONFIG_METROLOGIC_INTERFACE_DETECTION 1
++#define CONFIG_SUPPORT_KBW 1
++#define CONFIG_SUPPORT_IBM 1
++#define CONFIG_SUPPORT_MULTIFUNC 1
++#define CONFIG_SUPPORT_BLUETOOTH 1
++//#define CONFIG_RTS_DEFAULT_ASSERTED 1
++
++#define KBCLOCK_PIN 25
++#define RTS_PIN 25
++#define KBW_GATE_PIN 27
++#define IBM_RS4680_RESET_PIN 27
++#define FOCUS_KBWEN_PIN 24
++
++#define BT_LDO_PIN 27
++#define BT_RESET_PIN 26
++#define BT_RDY_PIN 37
++#define BT_CONN_PIN 35
++#define BT_DSR_PIN 34
++#define BT_SWITCH_PIN 2
++#define TRIG_PIN 41
++#define BLUE_LED_PIN 31
++#define WHITE_LED_PIN 30
++#define YELLOW_LED_PIN 29
++
++
++#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
++//#define CFG_AUTOLOAD "no"
++
++
++/****************************************************************/
++
++#endif
+diff --git a/u-boot-1.1.6/include/configs/IS4980.h b/u-boot-1.1.6/include/configs/IS4980.h
+new file mode 100644
+index 0000000..3861d38
+--- /dev/null
++++ b/u-boot-1.1.6/include/configs/IS4980.h
+@@ -0,0 +1,378 @@
++/*
++ * U-boot - Configuration file for BF537 STAMP board
++ */
++
++#ifndef __CONFIG_IS4980_H__
++#define __CONFIG_IS4980_H__
++
++#include <asm/blackfin-config-pre.h>
++
++
++#ifndef __ADSPBF534__
++#define __ADSPBF534__
++#endif
++#define METROLOGIC_PLATFORM "IS4980"
++#define SUPPORT_NETWORKING 0
++#define CONFIG_SILENT_CONSOLE 1
++#define CONFIG_BAUDRATE 115200
++#define CONFIG_LOADADDR 0x800000
++
++#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
++ "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
++
++#define CFG_PROMPT "bootldr> "
++#define CONFIG_ZERO_BOOTDELAY_CHECK
++#define CONFIG_AUTOBOOT_KEYED 1
++#define CONFIG_AUTOBOOT_STOP_STR "\033"
++#define CONFIG_MEM_MT48LC16M16A2TG_75 1
++//#define CONFIG_MEM_IS42S16160B_7 1
++
++//#define CONFIG_DEBUG_EARLY_SERIAL 1
++//#define DEBUG_BOOTKEYS 1
++//#define DEBUG 1
++//#define DEBUG_METRO_IO 1
++//#define DEBUG_I2C 1
++
++// We don't have a parallel flash chip there
++#define CFG_NO_FLASH
++
++
++ /*
++ * Processor Settings
++ */
++#define CONFIG_BFIN_CPU bf534-0.2
++#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
++
++
++/*
++ * Clock Settings
++ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
++ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
++ */
++/* CONFIG_CLKIN_HZ is any value in Hz */
++#define CONFIG_CLKIN_HZ 25000000
++/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
++/* 1 = CLKIN / 2 */
++#define CONFIG_CLKIN_HALF 0
++/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
++/* 1 = bypass PLL */
++#define CONFIG_PLL_BYPASS 0
++/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
++/* Values can range from 0-63 (where 0 means 64) */
++#define CONFIG_VCO_MULT 20
++/* CCLK_DIV controls the core clock divider */
++/* Values can be 1, 2, 4, or 8 ONLY */
++#define CONFIG_CCLK_DIV 1
++/* SCLK_DIV controls the system clock divider */
++/* Values can range from 1-15 */
++#define CONFIG_SCLK_DIV 4
++
++
++/*
++ * Memory Settings
++ */
++#define CONFIG_MEM_ADD_WDTH 9
++#define CONFIG_MEM_SIZE 32
++
++//#define CONFIG_EBIU_SDRRC_VAL 0x306
++//#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
++//#define CONFIG_EBIU_SDBCTL_VAL (EBSZ_64 | EBCAW_10 | EBE)
++
++#define CONFIG_EBIU_AMGCTL_VAL 0xFF
++//#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
++#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
++
++#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for monitor */
++#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 384 kB for malloc() (video/spi are big) */
++#define CFG_GBL_DATA_SIZE 0x4000
++
++
++/*
++ * Network Settings
++ */
++#if SUPPORT_NETWORKING
++#ifndef __ADSPBF534__
++#define ADI_CMDS_NETWORK 1
++#define CONFIG_BFIN_MAC
++#define CONFIG_NETCONSOLE 1
++#define CONFIG_NET_MULTI 1
++#else
++#define ADI_CMDS_NETWORK 0
++#endif
++#endif
++//#define CONFIG_HOSTNAME bf537-stamp
++/* Uncomment next line to use fixed MAC address */
++/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
++
++
++/*
++ * Flash Settings
++ */
++#define CFG_FLASH_BASE 0x20000000
++#define CFG_FLASH_CFI /* The flash is CFI compatible */
++//#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
++//#define CFG_FLASH_PROTECTION
++#define CFG_MAX_FLASH_BANKS 1
++#define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
++#define FLASH_SIZE 0x800000
++#define CFG_FLASH_SIZE 0x800000
++
++#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
++#define CFG_ENV_IS_IN_EEPROM 1
++#define CFG_ENV_OFFSET 0x4000
++#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
++#else
++#define CFG_ENV_IS_IN_FLASH 1
++#define CFG_ENV_ADDR 0x20004000
++#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
++#endif
++#define CFG_ENV_SIZE 0x2000
++#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
++#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
++#define ENV_IS_EMBEDDED
++#else
++#define ENV_IS_EMBEDDED_CUSTOM
++#endif
++
++/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
++/* Values can range from 2-65535 */
++/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
++#define CONFIG_SPI
++#define CONFIG_SPI_BAUD 2
++#define CONFIG_SPI_BAUD_INITBLOCK 3
++
++
++/*
++ * I2C Settings
++ */
++#define CONFIG_HARD_I2C 1 /* I2C TWI */
++#define CFG_I2C_SPEED 50000
++#define CFG_I2C_SLAVE 0
++
++
++/*
++ * NAND Settings
++ */
++/* #define CONFIG_BF537_NAND */
++#ifdef CONFIG_BF537_NAND
++# define ADD_NAND_CMD CFG_CMD_NAND
++#else
++# define ADD_NAND_CMD 0
++#endif
++
++#define CFG_NAND_ADDR 0x20212000
++#define CFG_NAND_BASE CFG_NAND_ADDR
++#define CFG_MAX_NAND_DEVICE 1
++#define SECTORSIZE 512
++#define ADDR_COLUMN 1
++#define ADDR_PAGE 2
++#define ADDR_COLUMN_PAGE 3
++#define NAND_ChipID_UNKNOWN 0x00
++#define NAND_MAX_FLOORS 1
++#define NAND_MAX_CHIPS 1
++#define BFIN_NAND_READY PF3
++
++#define NAND_WAIT_READY(nand) \
++ do { \
++ int timeout = 0; \
++ while(!(*pPORTFIO & PF3)) \
++ if (timeout++ > 100000) \
++ break; \
++ } while (0)
++
++#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
++#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
++
++#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
++#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
++#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
++#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
++
++
++/*
++ * CF-CARD IDE-HDD Support
++ */
++/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
++/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
++/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
++
++#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
++# define CONFIG_BFIN_IDE 1
++# define ADD_IDE_CMD CFG_CMD_IDE
++#else
++# define ADD_IDE_CMD 0
++#endif
++
++#if defined(CONFIG_BFIN_IDE)
++
++#define CONFIG_DOS_PARTITION 1
++/*
++ * IDE/ATA stuff
++ */
++#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
++#undef CONFIG_IDE_LED /* no led for ide supported */
++#undef CONFIG_IDE_RESET /* no reset for ide supported */
++
++#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
++#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
++
++#undef CONFIG_EBIU_AMBCTL1_VAL
++#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
++
++#define CONFIG_CF_ATASEL_DIS 0x20311800
++#define CONFIG_CF_ATASEL_ENA 0x20311802
++
++#if defined(CONFIG_BFIN_TRUE_IDE)
++/*
++ * Note that these settings aren't for the most part used in include/ata.h
++ * when all of the ATA registers are setup
++ */
++#define CFG_ATA_BASE_ADDR 0x2031C000
++#define CFG_ATA_IDE0_OFFSET 0x0000
++#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
++#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
++#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
++#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
++#endif /* CONFIG_BFIN_TRUE_IDE */
++
++#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
++#define CFG_ATA_BASE_ADDR 0x20211800
++#define CFG_ATA_IDE0_OFFSET 0x0000
++#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
++#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
++#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
++#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
++#endif /* CONFIG_BFIN_CF_IDE */
++
++#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
++#define CFG_ATA_BASE_ADDR 0x20314000
++#define CFG_ATA_IDE0_OFFSET 0x0000
++#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
++#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
++#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
++#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
++
++#undef CONFIG_SCLK_DIV
++#define CONFIG_SCLK_DIV 8
++#endif /* CONFIG_BFIN_HDD_IDE */
++
++#endif /*CONFIG_BFIN_IDE */
++
++
++/*
++ * Misc Settings
++ */
++#define CONFIG_MISC_INIT_R
++//#define CONFIG_RTC_BFIN
++
++/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
++
++//#define ADI_CMDS_EXTRA (ADD_IDE_CMD | ADD_NAND_CMD)
++#define CONFIG_BFIN_COMMANDS \
++ ( CFG_BFIN_CMD_BOOTLDR | \
++ CFG_BFIN_CMD_CPLBINFO )
++
++/* Define if want to do post memory test */
++#undef CONFIG_POST
++#ifdef CONFIG_POST
++#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
++#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
++#endif
++
++
++/*
++ * Pull in common ADI header for remaining command/environment setup
++ */
++#include <configs/bfin_adi_common.h>
++
++#include <asm/blackfin-config-post.h>
++
++#include <asm/mem_init.h>
++
++
++/* Overrides common ADI header's command/environment setup */
++
++#ifdef CONFIG_BOOTDELAY
++#undef CONFIG_BOOTDELAY
++#endif
++#define CONFIG_BOOTDELAY 10
++
++#ifdef CONFIG_BOOTCOMMAND
++#undef CONFIG_BOOTCOMMAND
++#endif
++#define CONFIG_BOOTCOMMAND "run flashboot"
++
++#ifdef CONFIG_BOOTARGS
++#undef CONFIG_BOOTARGS
++#endif
++#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m lpj=496640"
++
++#ifdef CONFIG_EBIU_SDRRC_VAL
++#undef CONFIG_EBIU_SDRRC_VAL
++#endif
++#define CONFIG_EBIU_SDRRC_VAL mem_SDRRC
++
++#ifdef CONFIG_EBIU_SDGCTL_VAL
++#undef CONFIG_EBIU_SDGCTL_VAL
++#endif
++#define CONFIG_EBIU_SDGCTL_VAL mem_SDGCTL
++
++#ifdef CONFIG_EBIU_SDBCTL_VAL
++#undef CONFIG_EBIU_SDBCTL_VAL
++#endif
++#define CONFIG_EBIU_SDBCTL_VAL mem_SDBCTL
++
++#ifdef CONFIG_EBIU_AMBCTL0_VAL
++#undef CONFIG_EBIU_AMBCTL0_VAL
++#endif
++#define CONFIG_EBIU_AMBCTL0_VAL flash_EBIU_AMBCTL0
++
++#ifdef CFG_AUTOLOAD
++#undef CFG_AUTOLOAD
++#endif
++#define CFG_AUTOLOAD ""
++
++ /* CONFIG_SERIAL_BF537 no longer used*/
++//#define CONFIG_SERIAL_BF537 1
++
++#ifdef CONFIG_POST_TEST
++#undef CONFIG_POST_TEST
++#endif
++
++#define CONFIG_METROLOGIC_IO_INIT 1
++
++#define CONFIG_CORE_VOLTAGE_MILLIVOLT 1250
++#define CONFIG_DISABLE_CLKIN_OUTPUT 1
++
++//#define CONFIG_METROLOGIC_INTERFACE_DETECTION 1
++//#define CONFIG_SUPPORT_KBW 1
++//#define CONFIG_SUPPORT_IBM 1
++//#define CONFIG_SUPPORT_MULTIFUNC 1
++//#define CONFIG_SUPPORT_BLUETOOTH 1
++//#define CONFIG_RTS_DEFAULT_ASSERTED 1
++
++//#define KBCLOCK_PIN 25
++#define RTS_PIN 25
++//#define KBW_GATE_PIN 27
++#define IBM_RS4680_RESET_PIN 27
++#define FOCUS_KBWEN_PIN 24
++
++//#define BT_LDO_PIN 27
++//#define BT_RESET_PIN 26
++//#define BT_RDY_PIN 37
++//#define BT_CONN_PIN 35
++//#define BT_DSR_PIN 34
++//#define BT_SWITCH_PIN 2
++//#define TRIG_PIN 41
++//#define BLUE_LED_PIN 31
++//#define WHITE_LED_PIN 30
++//#define YELLOW_LED_PIN 29
++
++
++#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
++//#define CFG_AUTOLOAD "no"
++
++
++/****************************************************************/
++
++#endif
+diff --git a/u-boot-1.1.6/include/configs/Orbit3.h b/u-boot-1.1.6/include/configs/Orbit3.h
+new file mode 100644
+index 0000000..d7ea48a
+--- /dev/null
++++ b/u-boot-1.1.6/include/configs/Orbit3.h
+@@ -0,0 +1,378 @@
++/*
++ * U-boot - Configuration file for BF537 STAMP board
++ */
++
++#ifndef __CONFIG_ORBIT3_H__
++#define __CONFIG_ORBIT3_H__
++
++#include <asm/blackfin-config-pre.h>
++
++
++#ifndef __ADSPBF534__
++#define __ADSPBF534__
++#endif
++#define METROLOGIC_PLATFORM "Genesis"
++#define SUPPORT_NETWORKING 0
++#define CONFIG_SILENT_CONSOLE 1
++#define CONFIG_BAUDRATE 115200
++#define CONFIG_LOADADDR 0x800000
++
++#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
++ "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
++
++#define CFG_PROMPT "bootldr> "
++#define CONFIG_ZERO_BOOTDELAY_CHECK
++#define CONFIG_AUTOBOOT_KEYED 1
++#define CONFIG_AUTOBOOT_STOP_STR "\033"
++#define CONFIG_MEM_MT48LC16M16A2TG_75 1
++//#define CONFIG_MEM_IS42S16160B_7 1
++
++//#define CONFIG_DEBUG_EARLY_SERIAL 1
++//#define DEBUG_BOOTKEYS 1
++//#define DEBUG 1
++//#define DEBUG_METRO_IO 1
++//#define DEBUG_I2C 1
++
++// We don't have a parallel flash chip there
++#define CFG_NO_FLASH
++
++
++ /*
++ * Processor Settings
++ */
++#define CONFIG_BFIN_CPU bf534-0.2
++#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
++
++
++/*
++ * Clock Settings
++ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
++ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
++ */
++/* CONFIG_CLKIN_HZ is any value in Hz */
++#define CONFIG_CLKIN_HZ 25000000
++/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
++/* 1 = CLKIN / 2 */
++#define CONFIG_CLKIN_HALF 0
++/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
++/* 1 = bypass PLL */
++#define CONFIG_PLL_BYPASS 0
++/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
++/* Values can range from 0-63 (where 0 means 64) */
++#define CONFIG_VCO_MULT 20
++/* CCLK_DIV controls the core clock divider */
++/* Values can be 1, 2, 4, or 8 ONLY */
++#define CONFIG_CCLK_DIV 1
++/* SCLK_DIV controls the system clock divider */
++/* Values can range from 1-15 */
++#define CONFIG_SCLK_DIV 4
++
++
++/*
++ * Memory Settings
++ */
++#define CONFIG_MEM_ADD_WDTH 9
++#define CONFIG_MEM_SIZE 32
++
++//#define CONFIG_EBIU_SDRRC_VAL 0x306
++//#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
++//#define CONFIG_EBIU_SDBCTL_VAL (EBSZ_64 | EBCAW_10 | EBE)
++
++#define CONFIG_EBIU_AMGCTL_VAL 0xFF
++//#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
++#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
++
++#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for monitor */
++#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 384 kB for malloc() (video/spi are big) */
++#define CFG_GBL_DATA_SIZE 0x4000
++
++
++/*
++ * Network Settings
++ */
++#if SUPPORT_NETWORKING
++#ifndef __ADSPBF534__
++#define ADI_CMDS_NETWORK 1
++#define CONFIG_BFIN_MAC
++#define CONFIG_NETCONSOLE 1
++#define CONFIG_NET_MULTI 1
++#else
++#define ADI_CMDS_NETWORK 0
++#endif
++#endif
++//#define CONFIG_HOSTNAME bf537-stamp
++/* Uncomment next line to use fixed MAC address */
++/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
++
++
++/*
++ * Flash Settings
++ */
++#define CFG_FLASH_BASE 0x20000000
++#define CFG_FLASH_CFI /* The flash is CFI compatible */
++//#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
++//#define CFG_FLASH_PROTECTION
++#define CFG_MAX_FLASH_BANKS 1
++#define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
++#define FLASH_SIZE 0x800000
++#define CFG_FLASH_SIZE 0x800000
++
++#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
++#define CFG_ENV_IS_IN_EEPROM 1
++#define CFG_ENV_OFFSET 0x4000
++#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
++#else
++#define CFG_ENV_IS_IN_FLASH 1
++#define CFG_ENV_ADDR 0x20004000
++#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
++#endif
++#define CFG_ENV_SIZE 0x2000
++#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
++#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
++#define ENV_IS_EMBEDDED
++#else
++#define ENV_IS_EMBEDDED_CUSTOM
++#endif
++
++/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
++/* Values can range from 2-65535 */
++/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
++#define CONFIG_SPI
++#define CONFIG_SPI_BAUD 2
++#define CONFIG_SPI_BAUD_INITBLOCK 3
++
++
++/*
++ * I2C Settings
++ */
++#define CONFIG_HARD_I2C 1 /* I2C TWI */
++#define CFG_I2C_SPEED 50000
++#define CFG_I2C_SLAVE 0
++
++
++/*
++ * NAND Settings
++ */
++/* #define CONFIG_BF537_NAND */
++#ifdef CONFIG_BF537_NAND
++# define ADD_NAND_CMD CFG_CMD_NAND
++#else
++# define ADD_NAND_CMD 0
++#endif
++
++#define CFG_NAND_ADDR 0x20212000
++#define CFG_NAND_BASE CFG_NAND_ADDR
++#define CFG_MAX_NAND_DEVICE 1
++#define SECTORSIZE 512
++#define ADDR_COLUMN 1
++#define ADDR_PAGE 2
++#define ADDR_COLUMN_PAGE 3
++#define NAND_ChipID_UNKNOWN 0x00
++#define NAND_MAX_FLOORS 1
++#define NAND_MAX_CHIPS 1
++#define BFIN_NAND_READY PF3
++
++#define NAND_WAIT_READY(nand) \
++ do { \
++ int timeout = 0; \
++ while(!(*pPORTFIO & PF3)) \
++ if (timeout++ > 100000) \
++ break; \
++ } while (0)
++
++#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
++#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
++
++#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
++#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
++#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
++#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
++
++
++/*
++ * CF-CARD IDE-HDD Support
++ */
++/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
++/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
++/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
++
++#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
++# define CONFIG_BFIN_IDE 1
++# define ADD_IDE_CMD CFG_CMD_IDE
++#else
++# define ADD_IDE_CMD 0
++#endif
++
++#if defined(CONFIG_BFIN_IDE)
++
++#define CONFIG_DOS_PARTITION 1
++/*
++ * IDE/ATA stuff
++ */
++#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
++#undef CONFIG_IDE_LED /* no led for ide supported */
++#undef CONFIG_IDE_RESET /* no reset for ide supported */
++
++#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
++#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
++
++#undef CONFIG_EBIU_AMBCTL1_VAL
++#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
++
++#define CONFIG_CF_ATASEL_DIS 0x20311800
++#define CONFIG_CF_ATASEL_ENA 0x20311802
++
++#if defined(CONFIG_BFIN_TRUE_IDE)
++/*
++ * Note that these settings aren't for the most part used in include/ata.h
++ * when all of the ATA registers are setup
++ */
++#define CFG_ATA_BASE_ADDR 0x2031C000
++#define CFG_ATA_IDE0_OFFSET 0x0000
++#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
++#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
++#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
++#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
++#endif /* CONFIG_BFIN_TRUE_IDE */
++
++#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
++#define CFG_ATA_BASE_ADDR 0x20211800
++#define CFG_ATA_IDE0_OFFSET 0x0000
++#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
++#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
++#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
++#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
++#endif /* CONFIG_BFIN_CF_IDE */
++
++#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
++#define CFG_ATA_BASE_ADDR 0x20314000
++#define CFG_ATA_IDE0_OFFSET 0x0000
++#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
++#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
++#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
++#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
++
++#undef CONFIG_SCLK_DIV
++#define CONFIG_SCLK_DIV 8
++#endif /* CONFIG_BFIN_HDD_IDE */
++
++#endif /*CONFIG_BFIN_IDE */
++
++
++/*
++ * Misc Settings
++ */
++#define CONFIG_MISC_INIT_R
++//#define CONFIG_RTC_BFIN
++
++/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
++
++//#define ADI_CMDS_EXTRA (ADD_IDE_CMD | ADD_NAND_CMD)
++#define CONFIG_BFIN_COMMANDS \
++ ( CFG_BFIN_CMD_BOOTLDR | \
++ CFG_BFIN_CMD_CPLBINFO )
++
++/* Define if want to do post memory test */
++#undef CONFIG_POST
++#ifdef CONFIG_POST
++#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
++#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
++#endif
++
++
++/*
++ * Pull in common ADI header for remaining command/environment setup
++ */
++#include <configs/bfin_adi_common.h>
++
++#include <asm/blackfin-config-post.h>
++
++#include <asm/mem_init.h>
++
++
++/* Overrides common ADI header's command/environment setup */
++
++#ifdef CONFIG_BOOTDELAY
++#undef CONFIG_BOOTDELAY
++#endif
++#define CONFIG_BOOTDELAY 10
++
++#ifdef CONFIG_BOOTCOMMAND
++#undef CONFIG_BOOTCOMMAND
++#endif
++#define CONFIG_BOOTCOMMAND "run flashboot"
++
++#ifdef CONFIG_BOOTARGS
++#undef CONFIG_BOOTARGS
++#endif
++#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m lpj=496640"
++
++#ifdef CONFIG_EBIU_SDRRC_VAL
++#undef CONFIG_EBIU_SDRRC_VAL
++#endif
++#define CONFIG_EBIU_SDRRC_VAL mem_SDRRC
++
++#ifdef CONFIG_EBIU_SDGCTL_VAL
++#undef CONFIG_EBIU_SDGCTL_VAL
++#endif
++#define CONFIG_EBIU_SDGCTL_VAL mem_SDGCTL
++
++#ifdef CONFIG_EBIU_SDBCTL_VAL
++#undef CONFIG_EBIU_SDBCTL_VAL
++#endif
++#define CONFIG_EBIU_SDBCTL_VAL mem_SDBCTL
++
++#ifdef CONFIG_EBIU_AMBCTL0_VAL
++#undef CONFIG_EBIU_AMBCTL0_VAL
++#endif
++#define CONFIG_EBIU_AMBCTL0_VAL flash_EBIU_AMBCTL0
++
++#ifdef CFG_AUTOLOAD
++#undef CFG_AUTOLOAD
++#endif
++#define CFG_AUTOLOAD ""
++
++ /* CONFIG_SERIAL_BF537 no longer used*/
++//#define CONFIG_SERIAL_BF537 1
++
++#ifdef CONFIG_POST_TEST
++#undef CONFIG_POST_TEST
++#endif
++
++#define CONFIG_METROLOGIC_IO_INIT 1
++
++#define CONFIG_CORE_VOLTAGE_MILLIVOLT 1250
++#define CONFIG_DISABLE_CLKIN_OUTPUT 1
++
++//#define CONFIG_METROLOGIC_INTERFACE_DETECTION 1
++//#define CONFIG_SUPPORT_KBW 1
++//#define CONFIG_SUPPORT_IBM 1
++//#define CONFIG_SUPPORT_MULTIFUNC 1
++//#define CONFIG_SUPPORT_BLUETOOTH 1
++//#define CONFIG_RTS_DEFAULT_ASSERTED 1
++
++//#define KBCLOCK_PIN 25
++#define RTS_PIN 25
++//#define KBW_GATE_PIN 27
++#define IBM_RS4680_RESET_PIN 27
++#define FOCUS_KBWEN_PIN 24
++
++//#define BT_LDO_PIN 27
++//#define BT_RESET_PIN 26
++//#define BT_RDY_PIN 37
++//#define BT_CONN_PIN 35
++//#define BT_DSR_PIN 34
++//#define BT_SWITCH_PIN 2
++//#define TRIG_PIN 41
++//#define BLUE_LED_PIN 31
++//#define WHITE_LED_PIN 30
++//#define YELLOW_LED_PIN 29
++
++
++#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
++//#define CFG_AUTOLOAD "no"
++
++
++/****************************************************************/
++
++#endif
+diff --git a/u-boot-1.1.6/include/configs/VuQuest2D.h b/u-boot-1.1.6/include/configs/VuQuest2D.h
+new file mode 100644
+index 0000000..2d9995f
+--- /dev/null
++++ b/u-boot-1.1.6/include/configs/VuQuest2D.h
+@@ -0,0 +1,309 @@
++/*
++ * U-boot - Configuration file for BF533 STAMP board
++ */
++
++#ifndef __CONFIG_VUQUEST2D_H__
++#define __CONFIG_VUQUEST2D_H__
++
++#include <asm/blackfin-config-pre.h>
++
++
++#ifndef __ADSPBF531__
++#define __ADSPBF531__
++#endif
++#define METROLOGIC_PLATFORM "VuQuest2D"
++#define SUPPORT_NETWORKING 0
++#define CONFIG_SILENT_CONSOLE 1
++#define CONFIG_BAUDRATE 115200
++#define CONFIG_LOADADDR 0x800000
++
++//#define METROLOGIC_FLASH_BOOT_ENV_PARAM "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
++
++#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
++ "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
++
++#define CFG_PROMPT "bootldr> "
++#define CONFIG_ZERO_BOOTDELAY_CHECK
++#define CONFIG_AUTOBOOT_KEYED 1
++#define CONFIG_AUTOBOOT_STOP_STR "\033"
++#define CONFIG_MEM_MT48LC16M16A2TG_75 1
++//#define CONFIG_MEM_IS42S16160B_7 1
++
++//#define CONFIG_DEBUG_EARLY_SERIAL 1
++//#define DEBUG_BOOTKEYS 1
++//#define DEBUG 1
++
++// We don't have a parallel flash chip there
++#define CFG_NO_FLASH
++
++
++/*
++ * Processor Settings
++ */
++#define CONFIG_BFIN_CPU bf531-0.3
++#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
++
++
++/*
++ * Clock Settings
++ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
++ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
++ */
++/* CONFIG_CLKIN_HZ is any value in Hz */
++#define CONFIG_CLKIN_HZ 25000000
++/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
++/* 1 = CLKIN / 2 */
++#define CONFIG_CLKIN_HALF 0
++/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
++/* 1 = bypass PLL */
++#define CONFIG_PLL_BYPASS 0
++/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
++/* Values can range from 0-63 (where 0 means 64) */
++#define CONFIG_VCO_MULT 15
++/* CCLK_DIV controls the core clock divider */
++/* Values can be 1, 2, 4, or 8 ONLY */
++#define CONFIG_CCLK_DIV 1
++/* SCLK_DIV controls the system clock divider */
++/* Values can range from 1-15 */
++#define CONFIG_SCLK_DIV 3
++
++
++/*
++ * Memory Settings
++ */
++#define CONFIG_MEM_ADD_WDTH 9
++#define CONFIG_MEM_SIZE 32
++
++#define CONFIG_EBIU_SDRRC_VAL 0x268
++#define CONFIG_EBIU_SDGCTL_VAL 0x911109
++#define CONFIG_EBIU_SDBCTL_VAL (EBSZ_128 | EBCAW_11 | EBE)
++
++#define CONFIG_EBIU_AMGCTL_VAL 0xFF
++#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
++#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
++
++#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for monitor */
++#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 384 kB for malloc() (video/spi are big) */
++#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */
++
++
++/*
++ * Network Settings
++
++ */
++#if SUPPORT_NETWORKING
++
++#define ADI_CMDS_NETWORK 0
++#define CONFIG_DRIVER_SMC91111 0
++#define CONFIG_SMC91111_BASE 0x20300300
++#define SMC91111_EEPROM_INIT() { *pFIO_DIR = 0x01; *pFIO_FLAG_S = 0x01; SSYNC(); }
++
++#endif /* SUPPORT_NETWORKING */
++
++#define CONFIG_HOSTNAME bf533-stamp
++/* To remove hardcoding and enable MAC storage in EEPROM */
++/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
++
++
++/*
++ * Flash Settings
++ */
++#define CFG_FLASH_CFI /* The flash is CFI compatible */
++//#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
++#define CFG_FLASH_CFI_AMD_RESET
++
++#define CFG_FLASH_BASE 0x20000000
++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
++#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
++#define FLASH_SIZE 0x800000
++#define CFG_FLASH_SIZE 0x800000
++
++#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
++#define CFG_ENV_IS_IN_EEPROM 1
++#define CFG_ENV_OFFSET 0x4000
++#else
++#define CFG_ENV_IS_IN_FLASH 1
++#define CFG_ENV_ADDR 0x20004000
++#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
++#endif
++#define CFG_ENV_SIZE 0x2000
++#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
++#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
++#define ENV_IS_EMBEDDED
++#else
++#define ENV_IS_EMBEDDED_CUSTOM
++#endif
++
++/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
++/* Values can range from 2-65535 */
++/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
++#define CONFIG_SPI
++#define CONFIG_SPI_BAUD 2
++#define CONFIG_SPI_BAUD_INITBLOCK 3
++#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
++
++
++/*
++ * I2C Settings
++ * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
++ */
++#define CONFIG_SOFT_I2C
++#define PF_SCL PF0
++#define PF_SDA PF1
++#ifdef CONFIG_SOFT_I2C
++#define I2C_INIT do { *pFIO_DIR |= PF_SCL; SSYNC(); } while (0)
++#define I2C_ACTIVE do { *pFIO_DIR |= PF_SDA; *pFIO_INEN &= ~PF_SDA; SSYNC(); } while (0)
++#define I2C_TRISTATE do { *pFIO_DIR &= ~PF_SDA; *pFIO_INEN |= PF_SDA; SSYNC(); } while (0)
++#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0)
++#define I2C_SDA(bit) \
++ do { \
++ if (bit) \
++ *pFIO_FLAG_S = PF_SDA; \
++ else \
++ *pFIO_FLAG_C = PF_SDA; \
++ SSYNC(); \
++ } while (0)
++#define I2C_SCL(bit) \
++ do { \
++ if (bit) \
++ *pFIO_FLAG_S = PF_SCL; \
++ else \
++ *pFIO_FLAG_C = PF_SCL; \
++ SSYNC(); \
++ } while (0)
++#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
++
++#define CFG_I2C_SPEED 50000
++#define CFG_I2C_SLAVE 0
++#endif
++
++
++/*
++ * Compact Flash / IDE / ATA Settings
++ */
++
++/* Enabled below option for CF support */
++/* #define CONFIG_STAMP_CF */
++#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
++#define CONFIG_MISC_INIT_R
++#define CONFIG_DOS_PARTITION 1
++#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
++#undef CONFIG_IDE_LED /* no led for ide supported */
++#undef CONFIG_IDE_RESET /* no reset for ide supported */
++
++#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
++#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
++
++#define CFG_ATA_BASE_ADDR 0x20200000
++#define CFG_ATA_IDE0_OFFSET 0x0000
++
++#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
++#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
++#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
++
++#define CFG_ATA_STRIDE 2
++
++#undef CONFIG_EBIU_AMBCTL1_VAL
++#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
++#endif
++
++
++/*
++ * Misc Settings
++ */
++// #define CONFIG_RTC_BFIN
++
++#define CONFIG_BFIN_COMMANDS \
++ ( CFG_BFIN_CMD_CPLBINFO )
++
++/* FLASH/ETHERNET uses the same async bank */
++#define SHARED_RESOURCES 1
++
++#ifdef CONFIG_POST_TEST
++#undef CONFIG_POST_TEST
++#endif
++
++/* define to enable splash screen support */
++/* #define CONFIG_VIDEO */
++
++/*
++ * Pull in common ADI header for remaining command/environment setup
++ */
++#include <configs/bfin_adi_common.h>
++
++#include <asm/blackfin-config-post.h>
++
++#include <asm/mem_init.h>
++
++
++/* Overrides common ADI header's command/environment setup */
++
++#ifdef CONFIG_BOOTDELAY
++#undef CONFIG_BOOTDELAY
++#endif
++#define CONFIG_BOOTDELAY 0
++
++#ifdef CONFIG_BOOTCOMMAND
++#undef CONFIG_BOOTCOMMAND
++#endif
++#define CONFIG_BOOTCOMMAND "run flashboot"
++
++#ifdef CONFIG_BOOTARGS
++#undef CONFIG_BOOTARGS
++#endif
++#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m lpj=396288"
++
++#ifdef CONFIG_EBIU_SDRRC_VAL
++#undef CONFIG_EBIU_SDRRC_VAL
++#endif
++#define CONFIG_EBIU_SDRRC_VAL mem_SDRRC
++
++#ifdef CONFIG_EBIU_SDGCTL_VAL
++#undef CONFIG_EBIU_SDGCTL_VAL
++#endif
++#define CONFIG_EBIU_SDGCTL_VAL mem_SDGCTL
++
++#ifdef CONFIG_EBIU_SDBCTL_VAL
++#undef CONFIG_EBIU_SDBCTL_VAL
++#endif
++#define CONFIG_EBIU_SDBCTL_VAL mem_SDBCTL
++
++#ifdef CONFIG_EBIU_AMBCTL0_VAL
++#undef CONFIG_EBIU_AMBCTL0_VAL
++#endif
++#define CONFIG_EBIU_AMBCTL0_VAL flash_EBIU_AMBCTL0
++
++#ifdef CFG_AUTOLOAD
++#undef CFG_AUTOLOAD
++#endif
++#define CFG_AUTOLOAD ""
++
++ /* CONFIG_SERIAL_BF537 no longer used*/
++//#define CONFIG_SERIAL_BF537 1
++
++#define CONFIG_METROLOGIC_IO_INIT 1
++
++#define CONFIG_CORE_VOLTAGE_MILLIVOLT 1250
++#define CONFIG_DISABLE_CLKIN_OUTPUT 1
++
++#define CONFIG_METROLOGIC_INTERFACE_DETECTION 1
++#define CONFIG_METROLOGIC_VQ2D_REV 2
++//#define CONFIG_SUPPORT_KBW 1
++//#define CONFIG_SUPPORT_IBM 1
++//#define CONFIG_SUPPORT_MULTIFUNC 1
++//#define CONFIG_SUPPORT_BLUETOOTH 1
++//#define CONFIG_RTS_DEFAULT_ASSERTED 1
++
++//#define KBCLOCK_PIN 25
++#define RTS_PIN 6
++//#define KBW_GATE_PIN 27
++//#define IBM_RS4680_RESET_PIN 27
++//#define FOCUS_KBWEN_PIN 24
++
++#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
++//#define CFG_AUTOLOAD "no"
++
++
++/****************************************************************/
++
++#endif
+diff --git a/u-boot-1.1.6/include/configs/bf533-stamp.h b/u-boot-1.1.6/include/configs/bf533-stamp.h
+index 2e6a51e..6b68418 100644
+--- a/u-boot-1.1.6/include/configs/bf533-stamp.h
++++ b/u-boot-1.1.6/include/configs/bf533-stamp.h
+@@ -8,6 +8,21 @@
+ #include <asm/blackfin-config-pre.h>
+
+
++#ifndef __ADSPBF533__
++#define __ADSPBF533__
++#endif
++#define METROLOGIC_PLATFORM "ADI Eval Board"
++#define SUPPORT_NETWORKING 0
++#define CONFIG_SILENT_CONSOLE 1
++#define CONFIG_BAUDRATE 115200
++#define CONFIG_LOADADDR 0x800000
++#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
++ "flashboot=bootm 0x20060000\0"
++#define CFG_PROMPT "bootldr> "
++#define CONFIG_ZERO_BOOTDELAY_CHECK
++#define CONFIG_AUTOBOOT_KEYED 1
++#define CONFIG_AUTOBOOT_STOP_STR "\033"
++
+ /*
+ * Processor Settings
+ */
+@@ -36,8 +51,7 @@
+ #define CONFIG_CCLK_DIV 1
+ /* SCLK_DIV controls the system clock divider */
+ /* Values can range from 1-15 */
+-#define CONFIG_SCLK_DIV 5
+-
++#define CONFIG_SCLK_DIV 4
+
+ /*
+ * Memory Settings
+@@ -61,10 +75,13 @@
+ /*
+ * Network Settings
+ */
++#if SUPPORT_NETWORKING
+ #define ADI_CMDS_NETWORK 1
+ #define CONFIG_DRIVER_SMC91111 1
+ #define CONFIG_SMC91111_BASE 0x20300300
+ #define SMC91111_EEPROM_INIT() { *pFIO_DIR = 0x01; *pFIO_FLAG_S = 0x01; SSYNC(); }
++#endif /* SUPPORT_NETWORKING */
++
+ #define CONFIG_HOSTNAME bf533-stamp
+ /* To remove hardcoding and enable MAC storage in EEPROM */
+ /* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
+@@ -80,6 +97,8 @@
+ #define CFG_FLASH_BASE 0x20000000
+ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+ #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
++#define FLASH_SIZE 0x800000
++#define CFG_FLASH_SIZE 0x800000
+
+ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+ #define CFG_ENV_IS_IN_EEPROM 1
+@@ -173,7 +192,7 @@
+ /*
+ * Misc Settings
+ */
+-#define CONFIG_RTC_BFIN
++//#define CONFIG_RTC_BFIN
+
+ #define CONFIG_BFIN_COMMANDS \
+ ( CFG_BFIN_CMD_CPLBINFO )
+@@ -184,8 +203,6 @@
+ /* define to enable splash screen support */
+ /* #define CONFIG_VIDEO */
+
+-
+-
+ /*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+@@ -193,4 +210,24 @@
+
+ #include <asm/blackfin-config-post.h>
+
++#include <asm/mem_init.h>
++
++
++/* Overrides common ADI header's command/environment setup */
++
++#ifdef CONFIG_BOOTDELAY
++#undef CONFIG_BOOTDELAY
++#endif
++#define CONFIG_BOOTDELAY 1
++
++#ifdef CONFIG_BOOTCOMMAND
++#undef CONFIG_BOOTCOMMAND
++#endif
++#define CONFIG_BOOTCOMMAND "run flashboot"
++
++#ifdef CONFIG_BOOTARGS
++#undef CONFIG_BOOTARGS
++#endif
++#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m"
++
+ #endif
+diff --git a/u-boot-1.1.6/include/configs/bf537-srv1.h b/u-boot-1.1.6/include/configs/bf537-srv1.h
+index f7d5bba..83c78c8 100644
+--- a/u-boot-1.1.6/include/configs/bf537-srv1.h
++++ b/u-boot-1.1.6/include/configs/bf537-srv1.h
+@@ -155,28 +155,37 @@
+ #endif
+
+ #ifdef CONFIG_BFIN_MAC
+-# define CONFIG_BFIN_CMD (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_DHCP)
++# define CONFIG_BFIN_CMD (CONFIG_CMD_DFL | CFG_CMD_PING)
+ #else
+ # define CONFIG_BFIN_CMD (CONFIG_CMD_DFL & ~CFG_CMD_NET)
+ #endif
+
+-#ifdef CFG_NO_FLASH
+-# define CONFIG_BFIN_CMD2 (CONFIG_BFIN_CMD & ~(CFG_CMD_IMLS | CFG_CMD_FLASH))
+-#else
+-# define CONFIG_BFIN_CMD2 (CONFIG_BFIN_CMD | CFG_CMD_JFFS2)
++#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) || (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
++#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \
++ CFG_CMD_ELF | \
++ CFG_CMD_I2C | \
++ CFG_CMD_CACHE | \
++ CFG_CMD_JFFS2 | \
++ CFG_CMD_EEPROM | \
++ CFG_CMD_DHCP | \
++ ADD_IDE_CMD | \
++ ADD_NAND_CMD | \
++ CFG_CMD_POST_DIAG | \
++ CFG_CMD_DATE)
++#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
++#define CONFIG_COMMANDS (( CONFIG_BFIN_CMD| \
++ CFG_CMD_ELF | \
++ CFG_CMD_I2C | \
++ CFG_CMD_CACHE | \
++ /* CFG_CMD_JFFS2 | */ \
++ CFG_CMD_EEPROM | \
++ /* ADD_IDE_CMD | */ \
++ CFG_CMD_DATE ) \
++ & \
++ /* no image ls */ ~(CFG_CMD_IMLS | CFG_CMD_FLASH) \
++ )
+ #endif
+
+-#define CONFIG_COMMANDS \
+- (CONFIG_BFIN_CMD2 | \
+- CFG_CMD_ELF | \
+- CFG_CMD_I2C | \
+- CFG_CMD_CACHE | \
+- CFG_CMD_EEPROM | \
+- ADD_IDE_CMD | \
+- ADD_NAND_CMD | \
+- CFG_CMD_POST_DIAG | \
+- CFG_CMD_DATE)
+-
+ #define CONFIG_BFIN_COMMANDS \
+ ( CFG_BFIN_CMD_BOOTLDR | \
+ CFG_BFIN_CMD_CPLBINFO )
+@@ -189,7 +198,7 @@
+ "update=tftpboot $(loadaddr) u-boot.bin;" \
+ "protect off 0x20000000 0x2003FFFF;" \
+ "erase 0x20000000 0x2003FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0"
+-#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) || (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
++#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+ # define BOOT_ENV_SETTINGS \
+ "update=tftpboot $(loadaddr) u-boot.ldr;" \
+ "eeprom write $(loadaddr) 0x0 $(filesize);\0" \
+@@ -243,18 +252,19 @@
+
+ #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+ #define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
+-#define CFG_MALLOC_LEN (384 << 10) /* Reserve 128 kB for malloc() */
++#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+ #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+ #define CFG_GBL_DATA_SIZE 0x4000
+ #define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+ #define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
+
+
+-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
++#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) || (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
++/* for bf537-stamp, UART boot mode still store env in flash */
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR 0x20004000
+ #define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
+-#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) || (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
++#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+ #define CFG_ENV_IS_IN_EEPROM 1
+ #define CFG_ENV_OFFSET 0x10000
+ #define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
+diff --git a/u-boot-1.1.6/include/configs/bf537-stamp.h b/u-boot-1.1.6/include/configs/bf537-stamp.h
+index aa4925f..f98c145 100644
+--- a/u-boot-1.1.6/include/configs/bf537-stamp.h
++++ b/u-boot-1.1.6/include/configs/bf537-stamp.h
+@@ -8,7 +8,22 @@
+ #include <asm/blackfin-config-pre.h>
+
+
+-/*
++#ifndef __ADSPBF537__
++#define __ADSPBF537__
++#endif
++#define METROLOGIC_PLATFORM "ADI Eval Board"
++#define SUPPORT_NETWORKING 1
++#define CONFIG_SILENT_CONSOLE 1
++#define CONFIG_BAUDRATE 115200
++#define CONFIG_LOADADDR 0x800000
++#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
++ "flashboot=bootm 0x20060000\0"
++#define CFG_PROMPT "bootldr> "
++#define CONFIG_ZERO_BOOTDELAY_CHECK
++#define CONFIG_AUTOBOOT_KEYED 1
++#define CONFIG_AUTOBOOT_STOP_STR "\033"
++
++ /*
+ * Processor Settings
+ */
+ #define CONFIG_BFIN_CPU bf537-0.2
+@@ -36,7 +51,7 @@
+ #define CONFIG_CCLK_DIV 1
+ /* SCLK_DIV controls the system clock divider */
+ /* Values can range from 1-15 */
+-#define CONFIG_SCLK_DIV 5
++#define CONFIG_SCLK_DIV 4
+
+
+ /*
+@@ -61,11 +76,15 @@
+ /*
+ * Network Settings
+ */
++#if SUPPORT_NETWORKING
+ #ifndef __ADSPBF534__
+ #define ADI_CMDS_NETWORK 1
+ #define CONFIG_BFIN_MAC
+ #define CONFIG_NETCONSOLE 1
+ #define CONFIG_NET_MULTI 1
++#else
++#define ADI_CMDS_NETWORK 0
++#endif
+ #endif
+ #define CONFIG_HOSTNAME bf537-stamp
+ /* Uncomment next line to use fixed MAC address */
+@@ -78,9 +97,11 @@
+ #define CFG_FLASH_BASE 0x20000000
+ #define CFG_FLASH_CFI /* The flash is CFI compatible */
+ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+-#define CFG_FLASH_PROTECTION
++//#define CFG_FLASH_PROTECTION
+ #define CFG_MAX_FLASH_BANKS 1
+ #define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
++#define FLASH_SIZE 0x800000
++#define CFG_FLASH_SIZE 0x800000
+
+ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+ #define CFG_ENV_IS_IN_EEPROM 1
+@@ -228,11 +249,11 @@
+ * Misc Settings
+ */
+ #define CONFIG_MISC_INIT_R
+-#define CONFIG_RTC_BFIN
++//#define CONFIG_RTC_BFIN
+
+ /* #define CONFIG_BF537_STAMP_LEDCMD 1 */
+
+-#define ADI_CMDS_EXTRA (ADD_IDE_CMD | ADD_NAND_CMD)
++//#define ADI_CMDS_EXTRA (ADD_IDE_CMD | ADD_NAND_CMD)
+ #define CONFIG_BFIN_COMMANDS \
+ ( CFG_BFIN_CMD_BOOTLDR | \
+ CFG_BFIN_CMD_CPLBINFO )
+@@ -244,7 +265,6 @@
+ #define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
+ #endif
+
+-
+ /*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+@@ -252,4 +272,24 @@
+
+ #include <asm/blackfin-config-post.h>
+
++#include <asm/mem_init.h>
++
++
++/* Overrides common ADI header's command/environment setup */
++
++#ifdef CONFIG_BOOTDELAY
++#undef CONFIG_BOOTDELAY
++#endif
++#define CONFIG_BOOTDELAY 1
++
++#ifdef CONFIG_BOOTCOMMAND
++#undef CONFIG_BOOTCOMMAND
++#endif
++#define CONFIG_BOOTCOMMAND "run flashboot"
++
++#ifdef CONFIG_BOOTARGS
++#undef CONFIG_BOOTARGS
++#endif
++#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m"
++
+ #endif
+diff --git a/u-boot-1.1.6/include/configs/bfin_adi_common.h b/u-boot-1.1.6/include/configs/bfin_adi_common.h
+index 1b4b851..faddc0e 100644
+--- a/u-boot-1.1.6/include/configs/bfin_adi_common.h
++++ b/u-boot-1.1.6/include/configs/bfin_adi_common.h
+@@ -9,10 +9,15 @@
+ * Command Settings
+ */
+ #ifndef CONFIG_COMMANDS
++# ifdef CFG_NO_FLASH
++# define ADI_CMDS_BASE1 (CONFIG_CMD_DFL & ~(CFG_CMD_IMLS | CFG_CMD_FLASH))
++#else
++# define ADI_CMDS_BASE1 (CONFIG_CMD_DFL)
++# endif
+ # if ADI_CMDS_NETWORK
+-# define ADI_CMDS_BASE (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_DHCP)
++# define ADI_CMDS_BASE (ADI_CMDS_BASE1 | CFG_CMD_PING | CFG_CMD_DHCP)
+ # else
+-# define ADI_CMDS_BASE (CONFIG_CMD_DFL & ~CFG_CMD_NET)
++# define ADI_CMDS_BASE (ADI_CMDS_BASE1 & ~CFG_CMD_NET)
+ # endif
+ # ifdef CONFIG_RTC_BFIN
+ # define ADI_CMDS_DATE (CFG_CMD_DATE)
+@@ -144,9 +149,16 @@
+ #else
+ # define NETWORK_ENV_SETTINGS
+ #endif
++
++#ifdef METROLOGIC_FLASH_BOOT_ENV_PARAM
++ #define EXTRA_ENV_SETTINGS METROLOGIC_FLASH_BOOT_ENV_PARAM
++#else
++ #define EXTRA_ENV_SETTINGS "flashboot=bootm 0x20060000\0"
++#endif
++
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ NETWORK_ENV_SETTINGS \
+- "flashboot=bootm 0x20100000\0"
++ EXTRA_ENV_SETTINGS
+
+ /*
+ * Network Settings
+diff --git a/u-boot-1.1.6/include/flash.h b/u-boot-1.1.6/include/flash.h
+index c9129cd..c35d87e 100644
+--- a/u-boot-1.1.6/include/flash.h
++++ b/u-boot-1.1.6/include/flash.h
+@@ -24,7 +24,6 @@
+ #ifndef _FLASH_H_
+ #define _FLASH_H_
+
+-#ifndef CFG_NO_FLASH
+ /*-----------------------------------------------------------------------
+ * FLASH Info: contains chip specific data, per FLASH bank
+ */
+@@ -49,6 +48,8 @@ typedef struct {
+ #endif
+ } flash_info_t;
+
++#ifndef CFG_NO_FLASH
++
+ /*
+ * Values for the width of the port
+ */
+diff --git a/u-boot-1.1.6/include/metro_pf.h b/u-boot-1.1.6/include/metro_pf.h
+new file mode 100644
+index 0000000..f274139
+--- /dev/null
++++ b/u-boot-1.1.6/include/metro_pf.h
+@@ -0,0 +1,103 @@
++#ifndef METRO_PF_H
++#define METRO_PF_H
++
++
++#ifndef PF_bit
++#define PF_bit(pfx) ( 1 << (pfx & 0x0f) )
++#endif
++
++//#ifndef CSYNC
++//#define CSYNC asm("csync;")
++//#endif
++
++//#ifndef SSYNC
++//#define SSYNC asm("ssync;")
++//#endif
++
++
++#if (defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)) || \
++ defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
++
++#define Metro_set_pfx_level(pf_num, level) \
++{ \
++ if ((pf_num >= 0) && (pf_num < 48)) \
++ { \
++ if (level) \
++ { \
++ if (pf_num < 16) \
++ *pPORTFIO_SET = PF_bit(pf_num); \
++ else if (pf_num < 32) \
++ *pPORTGIO_SET = PF_bit(pf_num); \
++ else \
++ *pPORTHIO_SET = PF_bit(pf_num); \
++ } \
++ else \
++ { \
++ if (pf_num < 16) \
++ *pPORTFIO_CLEAR = PF_bit(pf_num); \
++ else if (pf_num < 32) \
++ *pPORTGIO_CLEAR = PF_bit(pf_num); \
++ else \
++ *pPORTHIO_CLEAR = PF_bit(pf_num); \
++ } \
++ SSYNC(); \
++ } \
++}
++
++/*
++ * Return value:
++ * 0: level low
++ * 1: level high
++ */
++#define Metro_get_pfx_level(pf_num) ( (pf_num < 16) ? \
++ ( ( (*pPORTFIO ^ *pPORTFIO_POLAR) & PF_bit(pf_num) ) ? 1 : 0) : \
++ (pf_num < 32) ? \
++ ( ( (*pPORTGIO ^ *pPORTGIO_POLAR) & PF_bit(pf_num) ) ? 1 : 0) : \
++ ( ( (*pPORTHIO ^ *pPORTHIO_POLAR) & PF_bit(pf_num) ) ? 1 : 0) )
++
++#elif (defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) || \
++defined(__ADSPBF531__)) || defined(__ADSPBF532__) || defined(__ADSPBF533__)
++
++#define Metro_set_pfx_level(pf_num, level) \
++{ \
++ if ((pf_num >= 0) && (pf_num < 16)) \
++ { \
++ if (level) \
++ *pFIO_FLAG_S = PF_bit(pf_num); \
++ else \
++ *pFIO_FLAG_C = PF_bit(pf_num); \
++ SSYNC(); \
++ } \
++}
++
++/*
++ * Return value:
++ * 0: level low
++ * 1: level high
++ */
++#define Metro_get_pfx_level(pf_num) ( ( (*pFIO_FLAG_D ^ *pFIO_POLAR) & PF_bit(pf_num) ) ? 1 : 0)
++
++#else
++
++#error "Platform not supported"
++
++#endif
++
++
++
++//#define GPDRX_OUT(gpio_pin) { Metro_set_pfx_dir(gpio_pin, 1, -1); }
++//#define GPDRX_IN(gpio_pin) { Metro_set_pfx_dir(gpio_pin, 0, -1); }
++
++//#define SET_PIN(gpio_pin) { Metro_set_pfx_level(gpio_pin, 1); }
++//#define CLR_PIN(gpio_pin) { Metro_set_pfx_level(gpio_pin, 0); }
++//#define GET_PIN_LEVEL(gpio_pin) ( Metro_get_pfx_level(gpio_pin) )
++
++extern int Metro_set_pfx_dir(int pf_num, int dir, int initial_val);
++extern int Metro_get_pfx_dir(int pf_num);
++
++extern int set_pfx_dir(int pf_num, int dir);
++extern int get_pfx_dir(int pf_num);
++extern int get_pfx_level(int pf_num);
++extern int set_pfx_level(int pf_num, int level);
++
++#endif /* METRO_PF_H */
+diff --git a/u-boot-1.1.6/lib_blackfin/board.c b/u-boot-1.1.6/lib_blackfin/board.c
+index 942bfbc..5d32f12 100644
+--- a/u-boot-1.1.6/lib_blackfin/board.c
++++ b/u-boot-1.1.6/lib_blackfin/board.c
+@@ -46,7 +46,15 @@
+ int post_flag;
+ #endif
+
+-const char version_string[] = U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ")";
++#define VERSION_STRING_FORMAT "%s (%s - %s)\n%s\n%s (%s)\n"
++#define METROLOGIC_NAME "Metrologic Instruments, Inc."
++#define METROLOGIC_VERSION "Alex_2008R1_Ver1"
++#ifndef METROLOGIC_PLATFORM
++#define METROLOGIC_PLATFORM "UNKNOWN_PLATFORM"
++#endif
++const char version_string[] = U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ") " METROLOGIC_NAME " " METROLOGIC_PLATFORM " " METROLOGIC_VERSION ;
++
++//const char version_string[] = U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ")";
+
+ __attribute__((always_inline))
+ static inline void serial_early_puts(const char *s)
+@@ -160,7 +168,9 @@ static void display_global_data(void)
+ printf(" |-jt(%x): %x\n", gd->jt, *(gd->jt));
+ printf(" \\-bd: %x\n", gd->bd);
+ printf(" |-bi_baudrate: %x\n", bd->bi_baudrate);
++#if (CONFIG_COMMANDS & CFG_CMD_NET)
+ printf(" |-bi_ip_addr: %x\n", bd->bi_ip_addr);
++#endif
+ printf(" |-bi_enetaddr: %x %x %x %x %x %x\n",
+ bd->bi_enetaddr[0], bd->bi_enetaddr[1],
+ bd->bi_enetaddr[2], bd->bi_enetaddr[3],
+@@ -464,6 +474,24 @@ void board_init_r(gd_t * id, ulong dest_addr)
+ post_run(NULL, POST_RAM | post_bootmode_get(0));
+ #endif
+
++#if defined(CONFIG_METROLOGIC_IO_INIT)
++ /* miscellaneous platform dependent initialisations */
++#if defined(DEBUG_METRO_IO)
++ printf("start metrologic_io_init()\r\n");
++#endif
++ udelay(50 * 1000);
++ metrologic_io_init();
++#if defined(DEBUG_METRO_IO)
++ printf("done metrologic_io_init()\r\n");
++#endif
++#endif
++
++#if defined(CONFIG_CORE_VOLTAGE_MILLIVOLT)
++ program_vrctl(CONFIG_CORE_VOLTAGE_MILLIVOLT);
++#elif defined(CONFIG_DISABLE_CLKIN_OUTPUT)
++ program_vrctl(0);
++#endif // CONFIG_CORE_VOLTAGE_MILLIVOLT
++
+ /* main_loop() can return to retry autoboot, if so just run it again. */
+ for (;;) {
+ main_loop();
+diff --git a/u-boot-1.1.6/uses.mak b/u-boot-1.1.6/uses.mak
+new file mode 100644
+index 0000000..84483e4
+--- /dev/null
++++ b/u-boot-1.1.6/uses.mak
+@@ -0,0 +1,5 @@
++KERNEL_REV = 2007R1/Bfin_422
++TOOLCHAIN_REV = Ver_2008R1.5
++
++
++CROSS_COMPILE_PATH = /usr/src/blackfin/ADI_release/tools/$(TOOLCHAIN_REV)/bfin-uclinux/bin
+--
+1.6.0.2
+
projects / patches.git / commitdiff