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1 | Index: include/asm-blackfin/mach-bf548/anomaly.h | |
2 | =================================================================== | |
3 | --- include/asm-blackfin/mach-bf548/anomaly.h (revision 3448) | |
4 | +++ include/asm-blackfin/mach-bf548/anomaly.h (working copy) | |
5 | @@ -6,46 +6,62 @@ | |
6 | * Licensed under the GPL-2 or later. | |
7 | */ | |
8 | ||
9 | +/* This file shoule be up to date with: | |
10 | + * - Revision B, April 6, 2007; ADSP-BF549 Silicon Anomaly List | |
11 | + */ | |
12 | + | |
13 | #ifndef _MACH_ANOMALY_H_ | |
14 | #define _MACH_ANOMALY_H_ | |
15 | ||
16 | -#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in | |
17 | - * slot1 and store of a P register in slot 2 is not | |
18 | - * supported */ | |
19 | -#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive | |
20 | - * Channel DMA stops */ | |
21 | -#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR | |
22 | - * registers. */ | |
23 | -#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the | |
24 | - * Shadow of a Conditional Branch */ | |
25 | -#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event | |
26 | - * interrupt not functional */ | |
27 | -#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on | |
28 | - * SPORT external receive and transmit clocks. */ | |
29 | -#define ANOMALY_05000272 /* Certain data cache write through modes fail for | |
30 | - * VDDint <=0.9V */ | |
31 | -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is | |
32 | - * not restored */ | |
33 | -#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the | |
34 | - * Boundary of Reserved Memory */ | |
35 | -#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and | |
36 | - * LC Registers Are Interrupted */ | |
37 | -#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */ | |
38 | -#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */ | |
39 | -#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to | |
40 | - * the USB FIFO Simultaneously */ | |
41 | -#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write() | |
42 | - * function */ | |
43 | -#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional | |
44 | - * */ | |
45 | -#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */ | |
46 | -#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM | |
47 | - * Skew */ | |
48 | -#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */ | |
49 | -#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration | |
50 | - * of Host DMA Port */ | |
51 | -#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent | |
52 | - * Allowed Configuration on Host DMA Port */ | |
53 | -#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ | |
54 | +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ | |
55 | +#define ANOMALY_05000074 (1) | |
56 | +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | |
57 | +#define ANOMALY_05000119 (1) | |
58 | +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | |
59 | +#define ANOMALY_05000122 (1) | |
60 | +/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | |
61 | +#define ANOMALY_05000245 (1) | |
62 | +/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ | |
63 | +#define ANOMALY_05000255 (1) | |
64 | +/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | |
65 | +#define ANOMALY_05000265 (1) | |
66 | +/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | |
67 | +#define ANOMALY_05000272 (1) | |
68 | +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | |
69 | +#define ANOMALY_05000310 (1) | |
70 | +/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | |
71 | +#define ANOMALY_05000312 (1) | |
72 | +/* TWI Slave Boot Mode Is Not Functional */ | |
73 | +#define ANOMALY_05000324 (1) | |
74 | +/* External FIFO Boot Mode Is Not Functional */ | |
75 | +#define ANOMALY_05000325 (1) | |
76 | +/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ | |
77 | +#define ANOMALY_05000327 (1) | |
78 | +/* Incorrect Access of OTP_STATUS During otp_write() Function */ | |
79 | +#define ANOMALY_05000328 (1) | |
80 | +/* Synchronous Burst Flash Boot Mode Is Not Functional */ | |
81 | +#define ANOMALY_05000329 (1) | |
82 | +/* Host DMA Boot Mode Is Not Functional */ | |
83 | +#define ANOMALY_05000330 (1) | |
84 | +/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ | |
85 | +#define ANOMALY_05000334 (1) | |
86 | +/* Inadequate Rotary Debounce Logic Duration */ | |
87 | +#define ANOMALY_05000335 (1) | |
88 | +/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ | |
89 | +#define ANOMALY_05000336 (1) | |
90 | +/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ | |
91 | +#define ANOMALY_05000337 (1) | |
92 | +/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ | |
93 | +#define ANOMALY_05000338 (1) | |
94 | ||
95 | -#endif /* _MACH_ANOMALY_H_ */ | |
96 | +/* Anomalies that don't exist on this proc */ | |
97 | +#define ANOMALY_05000125 (0) | |
98 | +#define ANOMALY_05000183 (0) | |
99 | +#define ANOMALY_05000198 (0) | |
100 | +#define ANOMALY_05000244 (0) | |
101 | +#define ANOMALY_05000263 (0) | |
102 | +#define ANOMALY_05000266 (0) | |
103 | +#define ANOMALY_05000273 (0) | |
104 | +#define ANOMALY_05000311 (0) | |
105 | + | |
106 | +#endif | |
107 | Index: include/asm-blackfin/blackfin.h | |
108 | =================================================================== | |
109 | --- include/asm-blackfin/blackfin.h (revision 3448) | |
110 | +++ include/asm-blackfin/blackfin.h (working copy) | |
111 | @@ -17,72 +17,64 @@ | |
112 | #ifndef __ASSEMBLY__ | |
113 | ||
114 | /* SSYNC implementation for C file */ | |
115 | -#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244) | |
116 | -static inline void SSYNC (void) | |
117 | +static inline void SSYNC(void) | |
118 | { | |
119 | int _tmp; | |
120 | - __asm__ __volatile__ ("cli %0;\n\t" | |
121 | - "nop;nop;\n\t" | |
122 | - "ssync;\n\t" | |
123 | - "sti %0;\n\t" | |
124 | - :"=d"(_tmp):); | |
125 | + if (ANOMALY_05000312 && ANOMALY_05000244) | |
126 | + __asm__ __volatile__ ( | |
127 | + "cli %0;" | |
128 | + "nop;nop;" | |
129 | + "ssync;" | |
130 | + "sti %0;" | |
131 | + : "=d" (_tmp) | |
132 | + ); | |
133 | + else if (ANOMALY_05000312 && !ANOMALY_05000244) | |
134 | + __asm__ __volatile__ ( | |
135 | + "cli %0;" | |
136 | + "ssync;" | |
137 | + "sti %0;" | |
138 | + : "=d" (_tmp) | |
139 | + ); | |
140 | + else if (!ANOMALY_05000312 && ANOMALY_05000244) | |
141 | + __asm__ __volatile__ ( | |
142 | + "nop;" | |
143 | + "nop;" | |
144 | + "nop;" | |
145 | + "ssync;" | |
146 | + ); | |
147 | + else | |
148 | + __asm__ __volatile__ ("ssync;"); | |
149 | } | |
150 | -#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) | |
151 | -static inline void SSYNC (void) | |
152 | -{ | |
153 | - int _tmp; | |
154 | - __asm__ __volatile__ ("cli %0;\n\t" | |
155 | - "ssync;\n\t" | |
156 | - "sti %0;\n\t" | |
157 | - :"=d"(_tmp):); | |
158 | -} | |
159 | -#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244) | |
160 | -static inline void SSYNC (void) | |
161 | -{ | |
162 | - __asm__ __volatile__ ("nop; nop; nop;\n\t" | |
163 | - "ssync;\n\t" | |
164 | - ::); | |
165 | -} | |
166 | -#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) | |
167 | -static inline void SSYNC (void) | |
168 | -{ | |
169 | - __asm__ __volatile__ ("ssync;\n\t"); | |
170 | -} | |
171 | -#endif | |
172 | ||
173 | /* CSYNC implementation for C file */ | |
174 | -#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244) | |
175 | -static inline void CSYNC (void) | |
176 | +static inline void CSYNC(void) | |
177 | { | |
178 | int _tmp; | |
179 | - __asm__ __volatile__ ("cli %0;\n\t" | |
180 | - "nop;nop;\n\t" | |
181 | - "csync;\n\t" | |
182 | - "sti %0;\n\t" | |
183 | - :"=d"(_tmp):); | |
184 | + if (ANOMALY_05000312 && ANOMALY_05000244) | |
185 | + __asm__ __volatile__ ( | |
186 | + "cli %0;" | |
187 | + "nop;nop;" | |
188 | + "csync;" | |
189 | + "sti %0;" | |
190 | + : "=d" (_tmp) | |
191 | + ); | |
192 | + else if (ANOMALY_05000312 && !ANOMALY_05000244) | |
193 | + __asm__ __volatile__ ( | |
194 | + "cli %0;" | |
195 | + "csync;" | |
196 | + "sti %0;" | |
197 | + : "=d" (_tmp) | |
198 | + ); | |
199 | + else if (!ANOMALY_05000312 && ANOMALY_05000244) | |
200 | + __asm__ __volatile__ ( | |
201 | + "nop;" | |
202 | + "nop;" | |
203 | + "nop;" | |
204 | + "ssync;" | |
205 | + ); | |
206 | + else | |
207 | + __asm__ __volatile__ ("csync;"); | |
208 | } | |
209 | -#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) | |
210 | -static inline void CSYNC (void) | |
211 | -{ | |
212 | - int _tmp; | |
213 | - __asm__ __volatile__ ("cli %0;\n\t" | |
214 | - "csync;\n\t" | |
215 | - "sti %0;\n\t" | |
216 | - :"=d"(_tmp):); | |
217 | -} | |
218 | -#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244) | |
219 | -static inline void CSYNC (void) | |
220 | -{ | |
221 | - __asm__ __volatile__ ("nop; nop; nop;\n\t" | |
222 | - "ssync;\n\t" | |
223 | - ::); | |
224 | -} | |
225 | -#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) | |
226 | -static inline void CSYNC (void) | |
227 | -{ | |
228 | - __asm__ __volatile__ ("csync;\n\t"); | |
229 | -} | |
230 | -#endif | |
231 | ||
232 | #else /* __ASSEMBLY__ */ | |
233 | ||
234 | @@ -91,19 +83,19 @@ | |
235 | #define ssync(x) SSYNC(x) | |
236 | #define csync(x) CSYNC(x) | |
237 | ||
238 | -#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244) | |
239 | +#if ANOMALY_05000312 && ANOMALY_05000244 | |
240 | #define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch; | |
241 | #define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch; | |
242 | ||
243 | -#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) | |
244 | +#elif ANOMALY_05000312 && !ANOMALY_05000244 | |
245 | #define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch; | |
246 | #define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch; | |
247 | ||
248 | -#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244) | |
249 | +#elif !ANOMALY_05000312 && ANOMALY_05000244 | |
250 | #define SSYNC(scratch) nop; nop; nop; SSYNC; | |
251 | #define CSYNC(scratch) nop; nop; nop; CSYNC; | |
252 | ||
253 | -#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) | |
254 | +#elif !ANOMALY_05000312 && !ANOMALY_05000244 | |
255 | #define SSYNC(scratch) SSYNC; | |
256 | #define CSYNC(scratch) CSYNC; | |
257 | ||
258 | Index: include/asm-blackfin/mach-bf561/anomaly.h | |
259 | =================================================================== | |
260 | --- include/asm-blackfin/mach-bf561/anomaly.h (revision 3448) | |
261 | +++ include/asm-blackfin/mach-bf561/anomaly.h (working copy) | |
262 | @@ -7,155 +7,249 @@ | |
263 | */ | |
264 | ||
265 | /* This file shoule be up to date with: | |
266 | - * - Revision L, Aug 10, 2006; ADSP-BF561 Silicon Anomaly List | |
267 | + * - Revision N, March 28, 2007; ADSP-BF561 Silicon Anomaly List | |
268 | */ | |
269 | ||
270 | #ifndef _MACH_ANOMALY_H_ | |
271 | #define _MACH_ANOMALY_H_ | |
272 | ||
273 | -/* We do not support 0.1 or 0.4 silicon - sorry */ | |
274 | -#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || defined(CONFIG_BF_REV_0_4)) | |
275 | -#error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4 | |
276 | +/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */ | |
277 | +#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4 | |
278 | +# error Kernel will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 | |
279 | #endif | |
280 | ||
281 | -/* Issues that are common to 0.5 and 0.3 silicon */ | |
282 | -#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) | |
283 | -#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in | |
284 | - * slot1 and store of a P register in slot 2 is not | |
285 | - * supported */ | |
286 | -#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not | |
287 | - * updated at the same time. */ | |
288 | -#define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned | |
289 | - * memory locations */ | |
290 | -#define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR | |
291 | - * registers */ | |
292 | -#define ANOMALY_05000127 /* Signbits instruction not functional under certain | |
293 | - * conditions */ | |
294 | -#define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */ | |
295 | -#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out | |
296 | - * upper bits */ | |
297 | -#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ | |
298 | -#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame | |
299 | - * syncs */ | |
300 | -#define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz | |
301 | - * and higher devices */ | |
302 | -#define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */ | |
303 | -#define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */ | |
304 | -#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not | |
305 | - * functional */ | |
306 | -#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the | |
307 | - * shadow of a conditional branch */ | |
308 | -#define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop | |
309 | - * may cause bad instruction fetches */ | |
310 | -#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on | |
311 | - * external SPORT TX and RX clocks */ | |
312 | -#define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */ | |
313 | -#define ANOMALY_05000269 /* High I/O activity causes output voltage of internal | |
314 | - * voltage regulator (VDDint) to increase */ | |
315 | -#define ANOMALY_05000270 /* High I/O activity causes output voltage of internal | |
316 | - * voltage regulator (VDDint) to decrease */ | |
317 | -#define ANOMALY_05000272 /* Certain data cache write through modes fail for | |
318 | - * VDDint <=0.9V */ | |
319 | -#define ANOMALY_05000274 /* Data cache write back to external synchronous memory | |
320 | - * may be lost */ | |
321 | -#define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */ | |
322 | -#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC | |
323 | - * registers are interrupted */ | |
324 | +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ | |
325 | +#define ANOMALY_05000074 (1) | |
326 | +/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ | |
327 | +#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) | |
328 | +/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */ | |
329 | +#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) | |
330 | +/* Testset instructions restricted to 32-bit aligned memory locations */ | |
331 | +#define ANOMALY_05000120 (1) | |
332 | +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | |
333 | +#define ANOMALY_05000122 (1) | |
334 | +/* Erroneous exception when enabling cache */ | |
335 | +#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) | |
336 | +/* Signbits instruction not functional under certain conditions */ | |
337 | +#define ANOMALY_05000127 (1) | |
338 | +/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ | |
339 | +#define ANOMALY_05000134 (__SILICON_REVISION__ < 3) | |
340 | +/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */ | |
341 | +#define ANOMALY_05000135 (__SILICON_REVISION__ < 3) | |
342 | +/* Stall in multi-unit DMA operations */ | |
343 | +#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) | |
344 | +/* Allowing the SPORT RX FIFO to fill will cause an overflow */ | |
345 | +#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) | |
346 | +/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ | |
347 | +#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) | |
348 | +/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ | |
349 | +#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) | |
350 | +/* DMA and TESTSET conflict when both are accessing external memory */ | |
351 | +#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) | |
352 | +/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ | |
353 | +#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) | |
354 | +/* MDMA may lose the first few words of a descriptor chain */ | |
355 | +#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) | |
356 | +/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ | |
357 | +#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) | |
358 | +/* IMDMA S1/D1 channel may stall */ | |
359 | +#define ANOMALY_05000149 (1) | |
360 | +/* DMA engine may lose data due to incorrect handshaking */ | |
361 | +#define ANOMALY_05000150 (__SILICON_REVISION__ < 3) | |
362 | +/* DMA stalls when all three controllers read data from the same source */ | |
363 | +#define ANOMALY_05000151 (__SILICON_REVISION__ < 3) | |
364 | +/* Execution stall when executing in L2 and doing external accesses */ | |
365 | +#define ANOMALY_05000152 (__SILICON_REVISION__ < 3) | |
366 | +/* Frame Delay in SPORT Multichannel Mode */ | |
367 | +#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) | |
368 | +/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ | |
369 | +#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) | |
370 | +/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ | |
371 | +#define ANOMALY_05000156 (__SILICON_REVISION__ < 4) | |
372 | +/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ | |
373 | +#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) | |
374 | +/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ | |
375 | +#define ANOMALY_05000159 (__SILICON_REVISION__ < 3) | |
376 | +/* A read from external memory may return a wrong value with data cache enabled */ | |
377 | +#define ANOMALY_05000160 (__SILICON_REVISION__ < 3) | |
378 | +/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */ | |
379 | +#define ANOMALY_05000161 (__SILICON_REVISION__ < 3) | |
380 | +/* DMEM_CONTROL<12> is not set on Reset */ | |
381 | +#define ANOMALY_05000162 (__SILICON_REVISION__ < 3) | |
382 | +/* SPORT transmit data is not gated by external frame sync in certain conditions */ | |
383 | +#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) | |
384 | +/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ | |
385 | +#define ANOMALY_05000166 (1) | |
386 | +/* Turning Serial Ports on with External Frame Syncs */ | |
387 | +#define ANOMALY_05000167 (1) | |
388 | +/* SDRAM auto-refresh and subsequent Power Ups */ | |
389 | +#define ANOMALY_05000168 (__SILICON_REVISION__ < 5) | |
390 | +/* DATA CPLB page miss can result in lost write-through cache data writes */ | |
391 | +#define ANOMALY_05000169 (__SILICON_REVISION__ < 5) | |
392 | +/* Boot-ROM code modifies SICA_IWRx wakeup registers */ | |
393 | +#define ANOMALY_05000171 (__SILICON_REVISION__ < 5) | |
394 | +/* DSPID register values incorrect */ | |
395 | +#define ANOMALY_05000172 (__SILICON_REVISION__ < 3) | |
396 | +/* DMA vs Core accesses to external memory */ | |
397 | +#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) | |
398 | +/* Cache Fill Buffer Data lost */ | |
399 | +#define ANOMALY_05000174 (__SILICON_REVISION__ < 5) | |
400 | +/* Overlapping Sequencer and Memory Stalls */ | |
401 | +#define ANOMALY_05000175 (__SILICON_REVISION__ < 5) | |
402 | +/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ | |
403 | +#define ANOMALY_05000176 (__SILICON_REVISION__ < 5) | |
404 | +/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ | |
405 | +#define ANOMALY_05000179 (__SILICON_REVISION__ < 5) | |
406 | +/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ | |
407 | +#define ANOMALY_05000180 (1) | |
408 | +/* Disabling the PPI resets the PPI configuration registers */ | |
409 | +#define ANOMALY_05000181 (__SILICON_REVISION__ < 5) | |
410 | +/* IMDMA does not operate to full speed for 600MHz and higher devices */ | |
411 | +#define ANOMALY_05000182 (1) | |
412 | +/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */ | |
413 | +#define ANOMALY_05000184 (__SILICON_REVISION__ < 5) | |
414 | +/* PPI TX Mode with 2 External Frame Syncs */ | |
415 | +#define ANOMALY_05000185 (__SILICON_REVISION__ < 5) | |
416 | +/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */ | |
417 | +#define ANOMALY_05000186 (__SILICON_REVISION__ < 5) | |
418 | +/* IMDMA Corrupted Data after a Halt */ | |
419 | +#define ANOMALY_05000187 (1) | |
420 | +/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ | |
421 | +#define ANOMALY_05000188 (__SILICON_REVISION__ < 5) | |
422 | +/* False Protection Exceptions */ | |
423 | +#define ANOMALY_05000189 (__SILICON_REVISION__ < 5) | |
424 | +/* PPI not functional at core voltage < 1Volt */ | |
425 | +#define ANOMALY_05000190 (1) | |
426 | +/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ | |
427 | +#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) | |
428 | +/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ | |
429 | +#define ANOMALY_05000193 (__SILICON_REVISION__ < 5) | |
430 | +/* Restarting SPORT in Specific Modes May Cause Data Corruption */ | |
431 | +#define ANOMALY_05000194 (__SILICON_REVISION__ < 5) | |
432 | +/* Failing MMR Accesses When Stalled by Preceding Memory Read */ | |
433 | +#define ANOMALY_05000198 (__SILICON_REVISION__ < 5) | |
434 | +/* Current DMA Address Shows Wrong Value During Carry Fix */ | |
435 | +#define ANOMALY_05000199 (__SILICON_REVISION__ < 5) | |
436 | +/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ | |
437 | +#define ANOMALY_05000200 (__SILICON_REVISION__ < 5) | |
438 | +/* Possible Infinite Stall with Specific Dual-DAG Situation */ | |
439 | +#define ANOMALY_05000202 (__SILICON_REVISION__ < 5) | |
440 | +/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ | |
441 | +#define ANOMALY_05000204 (__SILICON_REVISION__ < 5) | |
442 | +/* Specific sequence that can cause DMA error or DMA stopping */ | |
443 | +#define ANOMALY_05000205 (__SILICON_REVISION__ < 5) | |
444 | +/* Recovery from "Brown-Out" Condition */ | |
445 | +#define ANOMALY_05000207 (__SILICON_REVISION__ < 5) | |
446 | +/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */ | |
447 | +#define ANOMALY_05000208 (1) | |
448 | +/* Speed Path in Computational Unit Affects Certain Instructions */ | |
449 | +#define ANOMALY_05000209 (__SILICON_REVISION__ < 5) | |
450 | +/* UART TX Interrupt Masked Erroneously */ | |
451 | +#define ANOMALY_05000215 (__SILICON_REVISION__ < 5) | |
452 | +/* NMI Event at Boot Time Results in Unpredictable State */ | |
453 | +#define ANOMALY_05000219 (__SILICON_REVISION__ < 5) | |
454 | +/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ | |
455 | +#define ANOMALY_05000220 (__SILICON_REVISION__ < 5) | |
456 | +/* Incorrect Pulse-Width of UART Start Bit */ | |
457 | +#define ANOMALY_05000225 (__SILICON_REVISION__ < 5) | |
458 | +/* Scratchpad Memory Bank Reads May Return Incorrect Data */ | |
459 | +#define ANOMALY_05000227 (__SILICON_REVISION__ < 5) | |
460 | +/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ | |
461 | +#define ANOMALY_05000230 (__SILICON_REVISION__ < 5) | |
462 | +/* UART STB Bit Incorrectly Affects Receiver Setting */ | |
463 | +#define ANOMALY_05000231 (__SILICON_REVISION__ < 5) | |
464 | +/* SPORT data transmit lines are incorrectly driven in multichannel mode */ | |
465 | +#define ANOMALY_05000232 (__SILICON_REVISION__ < 5) | |
466 | +/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ | |
467 | +#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) | |
468 | +/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ | |
469 | +#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) | |
470 | +/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | |
471 | +#define ANOMALY_05000245 (__SILICON_REVISION__ < 5) | |
472 | +/* TESTSET operation forces stall on the other core */ | |
473 | +#define ANOMALY_05000248 (__SILICON_REVISION__ < 5) | |
474 | +/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ | |
475 | +#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) | |
476 | +/* Exception Not Generated for MMR Accesses in Reserved Region */ | |
477 | +#define ANOMALY_05000251 (__SILICON_REVISION__ < 5) | |
478 | +/* Maximum External Clock Speed for Timers */ | |
479 | +#define ANOMALY_05000253 (__SILICON_REVISION__ < 5) | |
480 | +/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ | |
481 | +#define ANOMALY_05000254 (__SILICON_REVISION__ > 3) | |
482 | +/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ | |
483 | +#define ANOMALY_05000257 (__SILICON_REVISION__ < 5) | |
484 | +/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ | |
485 | +#define ANOMALY_05000258 (__SILICON_REVISION__ < 5) | |
486 | +/* ICPLB_STATUS MMR Register May Be Corrupted */ | |
487 | +#define ANOMALY_05000260 (__SILICON_REVISION__ < 5) | |
488 | +/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ | |
489 | +#define ANOMALY_05000261 (__SILICON_REVISION__ < 5) | |
490 | +/* Stores To Data Cache May Be Lost */ | |
491 | +#define ANOMALY_05000262 (__SILICON_REVISION__ < 5) | |
492 | +/* Hardware Loop Corrupted When Taking an ICPLB Exception */ | |
493 | +#define ANOMALY_05000263 (__SILICON_REVISION__ < 5) | |
494 | +/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ | |
495 | +#define ANOMALY_05000264 (__SILICON_REVISION__ < 5) | |
496 | +/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | |
497 | +#define ANOMALY_05000265 (__SILICON_REVISION__ < 5) | |
498 | +/* IMDMA destination IRQ status must be read prior to using IMDMA */ | |
499 | +#define ANOMALY_05000266 (__SILICON_REVISION__ > 3) | |
500 | +/* IMDMA may corrupt data under certain conditions */ | |
501 | +#define ANOMALY_05000267 (1) | |
502 | +/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ | |
503 | +#define ANOMALY_05000269 (1) | |
504 | +/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ | |
505 | +#define ANOMALY_05000270 (1) | |
506 | +/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | |
507 | +#define ANOMALY_05000272 (1) | |
508 | +/* Data cache write back to external synchronous memory may be lost */ | |
509 | +#define ANOMALY_05000274 (1) | |
510 | +/* PPI Timing and Sampling Information Updates */ | |
511 | +#define ANOMALY_05000275 (__SILICON_REVISION__ > 2) | |
512 | +/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ | |
513 | +#define ANOMALY_05000276 (__SILICON_REVISION__ < 5) | |
514 | +/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ | |
515 | +#define ANOMALY_05000278 (__SILICON_REVISION__ < 5) | |
516 | +/* False Hardware Error Exception When ISR Context Is Not Restored */ | |
517 | +#define ANOMALY_05000281 (__SILICON_REVISION__ < 5) | |
518 | +/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ | |
519 | +#define ANOMALY_05000283 (1) | |
520 | +/* A read will receive incorrect data under certain conditions */ | |
521 | +#define ANOMALY_05000287 (__SILICON_REVISION__ < 5) | |
522 | +/* SPORTs May Receive Bad Data If FIFOs Fill Up */ | |
523 | +#define ANOMALY_05000288 (__SILICON_REVISION__ < 5) | |
524 | +/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ | |
525 | +#define ANOMALY_05000301 (1) | |
526 | +/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ | |
527 | +#define ANOMALY_05000302 (1) | |
528 | +/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ | |
529 | +#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) | |
530 | +/* SCKELOW Bit Does Not Maintain State Through Hibernate */ | |
531 | +#define ANOMALY_05000307 (__SILICON_REVISION__ < 5) | |
532 | +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | |
533 | +#define ANOMALY_05000310 (1) | |
534 | +/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | |
535 | +#define ANOMALY_05000312 (1) | |
536 | +/* PPI Is Level-Sensitive on First Transfer */ | |
537 | +#define ANOMALY_05000313 (1) | |
538 | +/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ | |
539 | +#define ANOMALY_05000315 (1) | |
540 | +/* PF2 Output Remains Asserted After SPI Master Boot */ | |
541 | +#define ANOMALY_05000320 (__SILICON_REVISION__ > 3) | |
542 | +/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */ | |
543 | +#define ANOMALY_05000323 (1) | |
544 | +/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */ | |
545 | +#define ANOMALY_05000326 (__SILICON_REVISION__ > 3) | |
546 | +/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */ | |
547 | +#define ANOMALY_05000331 (__SILICON_REVISION__ < 5) | |
548 | +/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */ | |
549 | +#define ANOMALY_05000332 (__SILICON_REVISION__ < 5) | |
550 | +/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ | |
551 | +#define ANOMALY_05000333 (__SILICON_REVISION__ < 5) | |
552 | ||
553 | -#endif /* (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */ | |
554 | +/* Anomalies that don't exist on this proc */ | |
555 | +#define ANOMALY_05000183 (0) | |
556 | +#define ANOMALY_05000273 (0) | |
557 | +#define ANOMALY_05000311 (0) | |
558 | ||
559 | -#if (defined(CONFIG_BF_REV_0_5)) | |
560 | -#define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT | |
561 | - * mode with external clock */ | |
562 | -#define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to | |
563 | - * using IMDMA */ | |
564 | #endif | |
565 | - | |
566 | -#if (defined(CONFIG_BF_REV_0_3)) | |
567 | -#define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input) | |
568 | - * Mode with 0 Frame Syncs */ | |
569 | -#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */ | |
570 | -#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through | |
571 | - * cache data writes */ | |
572 | -#define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */ | |
573 | -#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */ | |
574 | -#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */ | |
575 | -#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an | |
576 | - * accumulator saturation */ | |
577 | -#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General | |
578 | - * Purpose TX or RX modes */ | |
579 | -#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration | |
580 | - * registers */ | |
581 | -#define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with | |
582 | - * External Frame Syncs */ | |
583 | -#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */ | |
584 | -#define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits | |
585 | - * (not a meaningful mode) */ | |
586 | -#define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer | |
587 | - * Placement in Memory */ | |
588 | -#define ANOMALY_05000189 /* False Protection Exception */ | |
589 | -#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs | |
590 | - * when polarity setting is changed */ | |
591 | -#define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data | |
592 | - * corruption */ | |
593 | -#define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding | |
594 | - * memory read */ | |
595 | -#define ANOMALY_05000199 /* DMA current address shows wrong value during carry | |
596 | - * fix */ | |
597 | -#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during | |
598 | - * inactive channels in certain conditions */ | |
599 | -#define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG | |
600 | - * situation */ | |
601 | -#define ANOMALY_05000204 /* Incorrect data read with write-through cache and | |
602 | - * allocate cache lines on reads only mode */ | |
603 | -#define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA | |
604 | - * stopping */ | |
605 | -#define ANOMALY_05000207 /* Recovery from "brown-out" condition */ | |
606 | -#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain | |
607 | - * instructions */ | |
608 | -#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ | |
609 | -#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable | |
610 | - * state */ | |
611 | -#define ANOMALY_05000220 /* Data Corruption with Cached External Memory and | |
612 | - * Non-Cached On-Chip L2 Memory */ | |
613 | -#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ | |
614 | -#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect | |
615 | - * data */ | |
616 | -#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate | |
617 | - * Differences in certain Conditions */ | |
618 | -#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ | |
619 | -#define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in | |
620 | - * multichannel mode */ | |
621 | -#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to | |
622 | - * hardware reset */ | |
623 | -#define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of | |
624 | - * Control causes failures */ | |
625 | -#define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */ | |
626 | -#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel | |
627 | - * (TDM) mode in certain conditions */ | |
628 | -#define ANOMALY_05000251 /* Exception not generated for MMR accesses in | |
629 | - * reserved region */ | |
630 | -#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ | |
631 | -#define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12 | |
632 | - * of the ICPLB Data registers differ */ | |
633 | -#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ | |
634 | -#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ | |
635 | -#define ANOMALY_05000262 /* Stores to data cache may be lost */ | |
636 | -#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB | |
637 | - * exception */ | |
638 | -#define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second | |
639 | - * to last instruction in hardware loop */ | |
640 | -#define ANOMALY_05000276 /* Timing requirements change for External Frame | |
641 | - * Sync PPI Modes with non-zero PPI_DELAY */ | |
642 | -#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause | |
643 | - * DMA system instability */ | |
644 | -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is | |
645 | - * not restored */ | |
646 | -#define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed | |
647 | - * in a particular stage */ | |
648 | -#define ANOMALY_05000287 /* A read will receive incorrect data under certain | |
649 | - * conditions */ | |
650 | -#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */ | |
651 | -#endif | |
652 | - | |
653 | -#endif /* _MACH_ANOMALY_H_ */ | |
654 | Index: include/asm-blackfin/mach-bf561/bf561.h | |
655 | =================================================================== | |
656 | --- include/asm-blackfin/mach-bf561/bf561.h (revision 3448) | |
657 | +++ include/asm-blackfin/mach-bf561/bf561.h (working copy) | |
658 | @@ -311,7 +311,7 @@ | |
659 | #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly | |
660 | #endif | |
661 | ||
662 | -#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1) | |
663 | +#if ANOMALY_05000273 && (CONFIG_CCLK_DIV == 1) | |
664 | #error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK | |
665 | #endif | |
666 | ||
667 | Index: include/asm-blackfin/mach-common/def_LPBlackfin.h | |
668 | =================================================================== | |
669 | --- include/asm-blackfin/mach-common/def_LPBlackfin.h (revision 3448) | |
670 | +++ include/asm-blackfin/mach-common/def_LPBlackfin.h (working copy) | |
671 | @@ -33,80 +33,76 @@ | |
672 | ||
673 | #include <asm/mach/anomaly.h> | |
674 | ||
675 | -/*#if !defined(__ADSPLPBLACKFIN__) | |
676 | -#warning def_LPBlackfin.h should only be included for 532 compatible chips. | |
677 | -#endif | |
678 | -*/ | |
679 | - | |
680 | #define MK_BMSK_(x) (1<<x) | |
681 | ||
682 | -#if defined(ANOMALY_05000198) | |
683 | +#ifndef __ASSEMBLY__ | |
684 | ||
685 | -#define bfin_read8(addr) ({ unsigned char __v; \ | |
686 | - __asm__ __volatile__ ("NOP;\n\t" \ | |
687 | - "%0 = b[%1] (z);\n\t" \ | |
688 | - : "=d"(__v) : "a"(addr)); \ | |
689 | - __v; }) | |
690 | +#include <linux/types.h> | |
691 | ||
692 | -#define bfin_read16(addr) ({ unsigned __v; \ | |
693 | - __asm__ __volatile__ ("NOP;\n\t"\ | |
694 | - "%0 = w[%1] (z);\n\t"\ | |
695 | - : "=d"(__v) : "a"(addr)); (unsigned short)__v; }) | |
696 | - | |
697 | -#define bfin_read32(addr) ({ unsigned __v; \ | |
698 | - __asm__ __volatile__ ("NOP;\n\t"\ | |
699 | - "%0 = [%1];\n\t"\ | |
700 | - : "=d"(__v) : "a"(addr)); __v; }) | |
701 | - | |
702 | -#define bfin_write8(addr, val) ({ \ | |
703 | - __asm__ __volatile__ ("NOP;\n\t" \ | |
704 | - "b[%0] = %1;\n\t" \ | |
705 | - : : "a"(addr), "d"(val) : "memory");}) | |
706 | - | |
707 | -#define bfin_write16(addr,val) ({\ | |
708 | - __asm__ __volatile__ ("NOP;\n\t"\ | |
709 | - "w[%0] = %1;\n\t"\ | |
710 | - : : "a"(addr) , "d"(val) : "memory");}) | |
711 | - | |
712 | -#define bfin_write32(addr,val) ({\ | |
713 | - __asm__ __volatile__ ("NOP;\n\t"\ | |
714 | - "[%0] = %1;\n\t"\ | |
715 | - : : "a"(addr) , "d"(val) : "memory");}) | |
716 | - | |
717 | +#if ANOMALY_05000198 | |
718 | +# define NOP_PAD_ANOMALY_05000198 "nop;" | |
719 | #else | |
720 | +# define NOP_PAD_ANOMALY_05000198 | |
721 | +#endif | |
722 | ||
723 | -#define bfin_read8(addr) ({ unsigned char __v; \ | |
724 | - __asm__ __volatile__ ( \ | |
725 | - "%0 = b[%1] (z);\n\t" \ | |
726 | - :"=d"(__v) : "a"(addr)); \ | |
727 | - __v; }) | |
728 | +#define bfin_read8(addr) ({ \ | |
729 | + uint8_t __v; \ | |
730 | + __asm__ __volatile__ ( \ | |
731 | + NOP_PAD_ANOMALY_05000198 \ | |
732 | + "%0 = b[%1] (z);" \ | |
733 | + : "=d" (__v) \ | |
734 | + : "a" (addr) \ | |
735 | + ); \ | |
736 | + __v; }) | |
737 | ||
738 | -#define bfin_read16(addr) ({ unsigned __v; \ | |
739 | - __asm__ __volatile__ (\ | |
740 | - "%0 = w[%1] (z);\n\t"\ | |
741 | - : "=d"(__v) : "a"(addr)); (unsigned short)__v; }) | |
742 | +#define bfin_read16(addr) ({ \ | |
743 | + uint16_t __v; \ | |
744 | + __asm__ __volatile__ ( \ | |
745 | + NOP_PAD_ANOMALY_05000198 \ | |
746 | + "%0 = w[%1] (z);" \ | |
747 | + : "=d" (__v) \ | |
748 | + : "a" (addr) \ | |
749 | + ); \ | |
750 | + __v; }) | |
751 | ||
752 | -#define bfin_read32(addr) ({ unsigned __v; \ | |
753 | - __asm__ __volatile__ (\ | |
754 | - "%0 = [%1];\n\t"\ | |
755 | - : "=d"(__v) : "a"(addr)); __v; }) | |
756 | +#define bfin_read32(addr) ({ \ | |
757 | + uint32_t __v; \ | |
758 | + __asm__ __volatile__ ( \ | |
759 | + NOP_PAD_ANOMALY_05000198 \ | |
760 | + "%0 = [%1];" \ | |
761 | + : "=d" (__v) \ | |
762 | + : "a" (addr) \ | |
763 | + ); \ | |
764 | + __v; }) | |
765 | ||
766 | #define bfin_write8(addr, val) ({ \ | |
767 | - __asm__ __volatile__ ( \ | |
768 | - "b[%0] = %1; \n\t" \ | |
769 | - ::"a"(addr), "d"(val) : "memory");}) | |
770 | + __asm__ __volatile__ ( \ | |
771 | + NOP_PAD_ANOMALY_05000198 \ | |
772 | + "b[%0] = %1;" \ | |
773 | + : \ | |
774 | + : "a" (addr), "d" (val) \ | |
775 | + : "memory" \ | |
776 | + ); }) | |
777 | ||
778 | -#define bfin_write16(addr,val) ({\ | |
779 | - __asm__ __volatile__ (\ | |
780 | - "w[%0] = %1;\n\t"\ | |
781 | - : : "a"(addr) , "d"(val) : "memory");}) | |
782 | +#define bfin_write16(addr, val) ({ \ | |
783 | + __asm__ __volatile__ ( \ | |
784 | + NOP_PAD_ANOMALY_05000198 \ | |
785 | + "w[%0] = %1;" \ | |
786 | + : \ | |
787 | + : "a" (addr), "d" (val) \ | |
788 | + : "memory" \ | |
789 | + ); }) | |
790 | ||
791 | -#define bfin_write32(addr,val) ({\ | |
792 | - __asm__ __volatile__ (\ | |
793 | - "[%0] = %1;\n\t"\ | |
794 | - : : "a"(addr) , "d"(val) : "memory");}) | |
795 | +#define bfin_write32(addr, val) ({ \ | |
796 | + __asm__ __volatile__ ( \ | |
797 | + NOP_PAD_ANOMALY_05000198 \ | |
798 | + "[%0] = %1;" \ | |
799 | + : \ | |
800 | + : "a" (addr), "d" (val) \ | |
801 | + : "memory" \ | |
802 | + ); }) | |
803 | ||
804 | -#endif | |
805 | +#endif /* __ASSEMBLY__ */ | |
806 | ||
807 | /************************************************** | |
808 | * System Register Bits | |
809 | Index: include/asm-blackfin/mach-common/cdef_LPBlackfin.h | |
810 | =================================================================== | |
811 | --- include/asm-blackfin/mach-common/cdef_LPBlackfin.h (revision 3448) | |
812 | +++ include/asm-blackfin/mach-common/cdef_LPBlackfin.h (working copy) | |
813 | @@ -39,7 +39,7 @@ | |
814 | #define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS) | |
815 | #define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) | |
816 | #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) | |
817 | -#ifdef ANOMALY_05000125 | |
818 | +#if ANOMALY_05000125 | |
819 | extern void bfin_write_DMEM_CONTROL(unsigned int val); | |
820 | #else | |
821 | #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) | |
822 | @@ -129,7 +129,7 @@ | |
823 | #define DTEST_DATA3 0xFFE0040C | |
824 | */ | |
825 | #define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) | |
826 | -#ifdef ANOMALY_05000125 | |
827 | +#if ANOMALY_05000125 | |
828 | extern void bfin_write_IMEM_CONTROL(unsigned int val); | |
829 | #else | |
830 | #define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) | |
831 | Index: include/asm-blackfin/system.h | |
832 | =================================================================== | |
833 | --- include/asm-blackfin/system.h (revision 3448) | |
834 | +++ include/asm-blackfin/system.h (working copy) | |
835 | @@ -36,6 +36,7 @@ | |
836 | ||
837 | #include <linux/linkage.h> | |
838 | #include <linux/compiler.h> | |
839 | +#include <asm/mach/anomaly.h> | |
840 | ||
841 | /* | |
842 | * Interrupt configuring macros. | |
843 | @@ -56,23 +57,22 @@ | |
844 | :"=d" (_tmp_dummy):); \ | |
845 | } while (0) | |
846 | ||
847 | -#if defined(ANOMALY_05000244) && defined (CONFIG_BLKFIN_CACHE) | |
848 | -#define idle_with_irq_disabled() do { \ | |
849 | - __asm__ __volatile__ ( \ | |
850 | - "nop; nop;\n" \ | |
851 | - ".align 8;\n" \ | |
852 | - "sti %0; idle;\n" \ | |
853 | - ::"d" (irq_flags)); \ | |
854 | -} while (0) | |
855 | +#if ANOMALY_05000244 && defined(CONFIG_BLKFIN_CACHE) | |
856 | +# define NOP_PAD_ANOMALY_05000244 "nop; nop;" | |
857 | #else | |
858 | -#define idle_with_irq_disabled() do { \ | |
859 | - __asm__ __volatile__ ( \ | |
860 | - ".align 8;\n" \ | |
861 | - "sti %0; idle;\n" \ | |
862 | - ::"d" (irq_flags)); \ | |
863 | -} while (0) | |
864 | +# define NOP_PAD_ANOMALY_05000244 | |
865 | #endif | |
866 | ||
867 | +#define idle_with_irq_disabled() \ | |
868 | + __asm__ __volatile__ ( \ | |
869 | + NOP_PAD_ANOMALY_05000244 \ | |
870 | + ".align 8;" \ | |
871 | + "sti %0;" \ | |
872 | + "idle;" \ | |
873 | + : \ | |
874 | + : "d" (irq_flags) \ | |
875 | + ); | |
876 | + | |
877 | #ifdef CONFIG_DEBUG_HWERR | |
878 | #define __save_and_cli(x) do { \ | |
879 | __asm__ __volatile__ ( \ | |
880 | Index: include/asm-blackfin/mach-bf533/anomaly.h | |
881 | =================================================================== | |
882 | --- include/asm-blackfin/mach-bf533/anomaly.h (revision 3448) | |
883 | +++ include/asm-blackfin/mach-bf533/anomaly.h (working copy) | |
884 | @@ -7,219 +7,252 @@ | |
885 | */ | |
886 | ||
887 | /* This file shoule be up to date with: | |
888 | - * - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List | |
889 | - * - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List | |
890 | - * - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List | |
891 | + * - Revision X, March 23, 2007; ADSP-BF533 Blackfin Processor Anomaly List | |
892 | + * - Revision AB, March 23, 2007; ADSP-BF532 Blackfin Processor Anomaly List | |
893 | + * - Revision W, March 23, 2007; ADSP-BF531 Blackfin Processor Anomaly List | |
894 | */ | |
895 | ||
896 | #ifndef _MACH_ANOMALY_H_ | |
897 | #define _MACH_ANOMALY_H_ | |
898 | ||
899 | /* We do not support 0.1 or 0.2 silicon - sorry */ | |
900 | -#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2)) | |
901 | -#error Kernel will not work on BF533 Version 0.1 or 0.2 | |
902 | +#if __SILICON_REVISION__ < 3 | |
903 | +# error Kernel will not work on BF533 silicon version 0.0, 0.1, or 0.2 | |
904 | #endif | |
905 | ||
906 | -/* Issues that are common to 0.5, 0.4, and 0.3 silicon */ | |
907 | -#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \ | |
908 | - || defined(CONFIG_BF_REV_0_3)) | |
909 | -#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in | |
910 | - * slot1 and store of a P register in slot 2 is not | |
911 | - * supported */ | |
912 | -#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on | |
913 | - * every corresponding match */ | |
914 | -#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive | |
915 | - * Channel DMA stops */ | |
916 | -#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR | |
917 | - * registers. */ | |
918 | -#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out | |
919 | - * upper bits*/ | |
920 | -#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ | |
921 | -#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame | |
922 | - * syncs */ | |
923 | -#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not | |
924 | - * functional */ | |
925 | -#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable | |
926 | - * state */ | |
927 | -#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */ | |
928 | -#define ANOMALY_05000272 /* Certain data cache write through modes fail for | |
929 | - * VDDint <=0.9V */ | |
930 | -#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */ | |
931 | -#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after | |
932 | - * an edge is detected may clear interrupt */ | |
933 | -#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause | |
934 | - * DMA system instability */ | |
935 | -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is | |
936 | - * not restored */ | |
937 | -#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic | |
938 | - * control */ | |
939 | -#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when | |
940 | - * killed in a particular stage*/ | |
941 | -#define ANOMALY_05000311 /* Erroneous flag pin operations under specific | |
942 | - * sequences */ | |
943 | -#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC | |
944 | - * registers are interrupted */ | |
945 | -#define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer */ | |
946 | -#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On | |
947 | - * Next System MMR Access */ | |
948 | -#define ANOMALY_05000319 /* Internal Voltage Regulator Values of 1.05V, 1.10V | |
949 | - * and 1.15V Not Allowed for LQFP Packages */ | |
950 | -#endif /* Issues that are common to 0.5, 0.4, and 0.3 silicon */ | |
951 | +#if defined(__ADSPBF531__) | |
952 | +# define ANOMALY_BF531 1 | |
953 | +#else | |
954 | +# define ANOMALY_BF531 0 | |
955 | +#endif | |
956 | +#if defined(__ADSPBF532__) | |
957 | +# define ANOMALY_BF532 1 | |
958 | +#else | |
959 | +# define ANOMALY_BF532 0 | |
960 | +#endif | |
961 | +#if defined(__ADSPBF533__) | |
962 | +# define ANOMALY_BF533 1 | |
963 | +#else | |
964 | +# define ANOMALY_BF533 0 | |
965 | +#endif | |
966 | ||
967 | -/* These issues only occur on 0.3 or 0.4 BF533 */ | |
968 | -#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) | |
969 | -#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not | |
970 | - * updated at the same time. */ | |
971 | -#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data | |
972 | - * Cache Fill can be corrupted after or during | |
973 | - * Instruction DMA if certain core stalls exist */ | |
974 | -#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General | |
975 | - * Purpose TX or RX modes */ | |
976 | -#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by | |
977 | - * preceding memory read */ | |
978 | -#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during | |
979 | - * inactive channels in certain conditions */ | |
980 | -#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag | |
981 | - * situation */ | |
982 | -#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ | |
983 | -#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ | |
984 | -#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect | |
985 | - * data*/ | |
986 | -#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate | |
987 | - * Differences in certain Conditions */ | |
988 | -#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ | |
989 | -#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to | |
990 | - * hardware reset */ | |
991 | -#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or | |
992 | - * IDLE around a Change of Control causes | |
993 | - * unpredictable results */ | |
994 | -#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the | |
995 | - * shadow of a conditional branch */ | |
996 | -#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware | |
997 | - * errors */ | |
998 | -#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ | |
999 | -#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event | |
1000 | - * interrupt not functional */ | |
1001 | -#define ANOMALY_05000257 /* An interrupt or exception during short Hardware | |
1002 | - * loops may cause the instruction fetch unit to | |
1003 | - * malfunction */ | |
1004 | -#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of | |
1005 | - * the ICPLB Data registers differ */ | |
1006 | -#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ | |
1007 | -#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ | |
1008 | -#define ANOMALY_05000262 /* Stores to data cache may be lost */ | |
1009 | -#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */ | |
1010 | -#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE | |
1011 | - * instruction will cause an infinite stall in the | |
1012 | - * second to last instruction in a hardware loop */ | |
1013 | -#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on | |
1014 | - * SPORT external receive and transmit clocks. */ | |
1015 | -#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the | |
1016 | - * internal voltage regulator (VDDint) to increase. */ | |
1017 | -#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the | |
1018 | - * internal voltage regulator (VDDint) to decrease */ | |
1019 | -#endif /* issues only occur on 0.3 or 0.4 BF533 */ | |
1020 | +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ | |
1021 | +#define ANOMALY_05000074 (1) | |
1022 | +/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ | |
1023 | +#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) | |
1024 | +/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */ | |
1025 | +#define ANOMALY_05000105 (1) | |
1026 | +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | |
1027 | +#define ANOMALY_05000119 (1) | |
1028 | +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | |
1029 | +#define ANOMALY_05000122 (1) | |
1030 | +/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ | |
1031 | +#define ANOMALY_05000158 (__SILICON_REVISION__ < 5) | |
1032 | +/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ | |
1033 | +#define ANOMALY_05000166 (1) | |
1034 | +/* Turning Serial Ports on with External Frame Syncs */ | |
1035 | +#define ANOMALY_05000167 (1) | |
1036 | +/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ | |
1037 | +#define ANOMALY_05000179 (__SILICON_REVISION__ < 5) | |
1038 | +/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ | |
1039 | +#define ANOMALY_05000180 (1) | |
1040 | +/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ | |
1041 | +#define ANOMALY_05000183 (__SILICON_REVISION__ < 4) | |
1042 | +/* False Protection Exceptions */ | |
1043 | +#define ANOMALY_05000189 (__SILICON_REVISION__ < 4) | |
1044 | +/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ | |
1045 | +#define ANOMALY_05000193 (__SILICON_REVISION__ < 4) | |
1046 | +/* Restarting SPORT in Specific Modes May Cause Data Corruption */ | |
1047 | +#define ANOMALY_05000194 (__SILICON_REVISION__ < 4) | |
1048 | +/* Failing MMR Accesses When Stalled by Preceding Memory Read */ | |
1049 | +#define ANOMALY_05000198 (__SILICON_REVISION__ < 5) | |
1050 | +/* Current DMA Address Shows Wrong Value During Carry Fix */ | |
1051 | +#define ANOMALY_05000199 (__SILICON_REVISION__ < 4) | |
1052 | +/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ | |
1053 | +#define ANOMALY_05000200 (__SILICON_REVISION__ < 5) | |
1054 | +/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */ | |
1055 | +#define ANOMALY_05000201 (__SILICON_REVISION__ < 4) | |
1056 | +/* Possible Infinite Stall with Specific Dual-DAG Situation */ | |
1057 | +#define ANOMALY_05000202 (__SILICON_REVISION__ < 5) | |
1058 | +/* Specific Sequence That Can Cause DMA Error or DMA Stopping */ | |
1059 | +#define ANOMALY_05000203 (__SILICON_REVISION__ < 4) | |
1060 | +/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ | |
1061 | +#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) | |
1062 | +/* Recovery from "Brown-Out" Condition */ | |
1063 | +#define ANOMALY_05000207 (__SILICON_REVISION__ < 4) | |
1064 | +/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */ | |
1065 | +#define ANOMALY_05000208 (1) | |
1066 | +/* Speed Path in Computational Unit Affects Certain Instructions */ | |
1067 | +#define ANOMALY_05000209 (__SILICON_REVISION__ < 4) | |
1068 | +/* UART TX Interrupt Masked Erroneously */ | |
1069 | +#define ANOMALY_05000215 (__SILICON_REVISION__ < 5) | |
1070 | +/* NMI Event at Boot Time Results in Unpredictable State */ | |
1071 | +#define ANOMALY_05000219 (1) | |
1072 | +/* Incorrect Pulse-Width of UART Start Bit */ | |
1073 | +#define ANOMALY_05000225 (__SILICON_REVISION__ < 5) | |
1074 | +/* Scratchpad Memory Bank Reads May Return Incorrect Data */ | |
1075 | +#define ANOMALY_05000227 (__SILICON_REVISION__ < 5) | |
1076 | +/* SPI Slave Boot Mode Modifies Registers from Reset Value */ | |
1077 | +#define ANOMALY_05000229 (1) | |
1078 | +/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ | |
1079 | +#define ANOMALY_05000230 (__SILICON_REVISION__ < 5) | |
1080 | +/* UART STB Bit Incorrectly Affects Receiver Setting */ | |
1081 | +#define ANOMALY_05000231 (__SILICON_REVISION__ < 5) | |
1082 | +/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ | |
1083 | +#define ANOMALY_05000233 (__SILICON_REVISION__ < 4) | |
1084 | +/* Incorrect Revision Number in DSPID Register */ | |
1085 | +#define ANOMALY_05000234 (__SILICON_REVISION__ == 4) | |
1086 | +/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ | |
1087 | +#define ANOMALY_05000242 (__SILICON_REVISION__ < 4) | |
1088 | +/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ | |
1089 | +#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) | |
1090 | +/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | |
1091 | +#define ANOMALY_05000245 (1) | |
1092 | +/* Data CPLBs Should Prevent Spurious Hardware Errors */ | |
1093 | +#define ANOMALY_05000246 (__SILICON_REVISION__ < 5) | |
1094 | +/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ | |
1095 | +#define ANOMALY_05000250 (__SILICON_REVISION__ == 4) | |
1096 | +/* Maximum External Clock Speed for Timers */ | |
1097 | +#define ANOMALY_05000253 (__SILICON_REVISION__ < 5) | |
1098 | +/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ | |
1099 | +#define ANOMALY_05000254 (__SILICON_REVISION__ > 4) | |
1100 | +/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ | |
1101 | +#define ANOMALY_05000255 (__SILICON_REVISION__ < 5) | |
1102 | +/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ | |
1103 | +#define ANOMALY_05000257 (__SILICON_REVISION__ < 5) | |
1104 | +/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ | |
1105 | +#define ANOMALY_05000258 (__SILICON_REVISION__ < 5) | |
1106 | +/* ICPLB_STATUS MMR Register May Be Corrupted */ | |
1107 | +#define ANOMALY_05000260 (__SILICON_REVISION__ < 5) | |
1108 | +/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ | |
1109 | +#define ANOMALY_05000261 (__SILICON_REVISION__ < 5) | |
1110 | +/* Stores To Data Cache May Be Lost */ | |
1111 | +#define ANOMALY_05000262 (__SILICON_REVISION__ < 5) | |
1112 | +/* Hardware Loop Corrupted When Taking an ICPLB Exception */ | |
1113 | +#define ANOMALY_05000263 (__SILICON_REVISION__ < 5) | |
1114 | +/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ | |
1115 | +#define ANOMALY_05000264 (__SILICON_REVISION__ < 5) | |
1116 | +/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | |
1117 | +#define ANOMALY_05000265 (__SILICON_REVISION__ < 5) | |
1118 | +/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ | |
1119 | +#define ANOMALY_05000269 (__SILICON_REVISION__ < 5) | |
1120 | +/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ | |
1121 | +#define ANOMALY_05000270 (__SILICON_REVISION__ < 5) | |
1122 | +/* Spontaneous Reset of Internal Voltage Regulator */ | |
1123 | +#define ANOMALY_05000271 (__SILICON_REVISION__ < 4) | |
1124 | +/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | |
1125 | +#define ANOMALY_05000272 (1) | |
1126 | +/* Writes to Synchronous SDRAM Memory May Be Lost */ | |
1127 | +#define ANOMALY_05000273 (1) | |
1128 | +/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ | |
1129 | +#define ANOMALY_05000276 (1) | |
1130 | +/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ | |
1131 | +#define ANOMALY_05000277 (1) | |
1132 | +/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ | |
1133 | +#define ANOMALY_05000278 (1) | |
1134 | +/* False Hardware Error Exception When ISR Context Is Not Restored */ | |
1135 | +#define ANOMALY_05000281 (1) | |
1136 | +/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ | |
1137 | +#define ANOMALY_05000282 (1) | |
1138 | +/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ | |
1139 | +#define ANOMALY_05000283 (1) | |
1140 | +/* SPORTs May Receive Bad Data If FIFOs Fill Up */ | |
1141 | +#define ANOMALY_05000288 (1) | |
1142 | +/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ | |
1143 | +#define ANOMALY_05000301 (1) | |
1144 | +/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ | |
1145 | +#define ANOMALY_05000302 (__SILICON_REVISION__ < 5) | |
1146 | +/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ | |
1147 | +#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) | |
1148 | +/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ | |
1149 | +#define ANOMALY_05000306 (__SILICON_REVISION__ < 5) | |
1150 | +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | |
1151 | +#define ANOMALY_05000310 (1) | |
1152 | +/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ | |
1153 | +#define ANOMALY_05000311 (1) | |
1154 | +/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | |
1155 | +#define ANOMALY_05000312 (1) | |
1156 | +/* PPI Is Level-Sensitive on First Transfer */ | |
1157 | +#define ANOMALY_05000313 (1) | |
1158 | +/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ | |
1159 | +#define ANOMALY_05000315 (1) | |
1160 | +/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ | |
1161 | +#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532) | |
1162 | ||
1163 | -/* These issues are only on 0.4 silicon */ | |
1164 | -#if (defined(CONFIG_BF_REV_0_4)) | |
1165 | -#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */ | |
1166 | -#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel | |
1167 | - * (TDM) */ | |
1168 | -#endif /* issues are only on 0.4 silicon */ | |
1169 | +/* These anomalies have been "phased" out of analog.com anomaly sheets and are | |
1170 | + * here to show running on older silicon just isn't feasible. | |
1171 | + */ | |
1172 | ||
1173 | -/* These issues are only on 0.3 silicon */ | |
1174 | -#if defined(CONFIG_BF_REV_0_3) | |
1175 | -#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with | |
1176 | - * External Frame Syncs */ | |
1177 | -#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative | |
1178 | - * Instruction or Data Fetches, or by Fetches at the | |
1179 | - * boundary of reserved memory space */ | |
1180 | -#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs | |
1181 | - * when polarity setting is changed */ | |
1182 | -#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data | |
1183 | - * corruption */ | |
1184 | -#define ANOMALY_05000199 /* DMA current address shows wrong value during carry | |
1185 | - * fix */ | |
1186 | -#define ANOMALY_05000201 /* Receive frame sync not ignored during active | |
1187 | - * frames in sport MCM */ | |
1188 | -#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA | |
1189 | - * stopping */ | |
1190 | -#if defined(CONFIG_BF533) | |
1191 | -#define ANOMALY_05000204 /* Incorrect data read with write-through cache and | |
1192 | - * allocate cache lines on reads only mode */ | |
1193 | -#endif /* CONFIG_BF533 */ | |
1194 | -#define ANOMALY_05000207 /* Recovery from "brown-out" condition */ | |
1195 | -#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain | |
1196 | - * instructions */ | |
1197 | -#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame | |
1198 | - * Sync Transmit Mode */ | |
1199 | -#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */ | |
1200 | -#endif /* only on 0.3 silicon */ | |
1201 | +/* Watchpoints (Hardware Breakpoints) are not supported */ | |
1202 | +#define ANOMALY_05000067 (__SILICON_REVISION__ < 3) | |
1203 | +/* Reserved bits in SYSCFG register not set at power on */ | |
1204 | +#define ANOMALY_05000109 (__SILICON_REVISION__ < 3) | |
1205 | +/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ | |
1206 | +#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) | |
1207 | +/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */ | |
1208 | +#define ANOMALY_05000123 (__SILICON_REVISION__ < 3) | |
1209 | +/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ | |
1210 | +#define ANOMALY_05000124 (__SILICON_REVISION__ < 3) | |
1211 | +/* Erroneous exception when enabling cache */ | |
1212 | +#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) | |
1213 | +/* SPI clock polarity and phase bits incorrect during booting */ | |
1214 | +#define ANOMALY_05000126 (__SILICON_REVISION__ < 3) | |
1215 | +/* DMEM_CONTROL is not set on Reset */ | |
1216 | +#define ANOMALY_05000137 (__SILICON_REVISION__ < 3) | |
1217 | +/* SPI boot will not complete if there is a zero fill block in the loader file */ | |
1218 | +#define ANOMALY_05000138 (__SILICON_REVISION__ < 3) | |
1219 | +/* Allowing the SPORT RX FIFO to fill will cause an overflow */ | |
1220 | +#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) | |
1221 | +/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ | |
1222 | +#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) | |
1223 | +/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ | |
1224 | +#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) | |
1225 | +/* A read from external memory may return a wrong value with data cache enabled */ | |
1226 | +#define ANOMALY_05000143 (__SILICON_REVISION__ < 3) | |
1227 | +/* DMA and TESTSET conflict when both are accessing external memory */ | |
1228 | +#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) | |
1229 | +/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ | |
1230 | +#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) | |
1231 | +/* MDMA may lose the first few words of a descriptor chain */ | |
1232 | +#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) | |
1233 | +/* The source MDMA descriptor may stop with a DMA Error */ | |
1234 | +#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) | |
1235 | +/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ | |
1236 | +#define ANOMALY_05000148 (__SILICON_REVISION__ < 3) | |
1237 | +/* Frame Delay in SPORT Multichannel Mode */ | |
1238 | +#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) | |
1239 | +/* SPORT TFS signal is active in Multi-channel mode outside of valid channels */ | |
1240 | +#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) | |
1241 | +/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ | |
1242 | +#define ANOMALY_05000155 (__SILICON_REVISION__ < 3) | |
1243 | +/* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */ | |
1244 | +#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) | |
1245 | +/* SPORT transmit data is not gated by external frame sync in certain conditions */ | |
1246 | +#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) | |
1247 | +/* SDRAM auto-refresh and subsequent Power Ups */ | |
1248 | +#define ANOMALY_05000168 (__SILICON_REVISION__ < 3) | |
1249 | +/* DATA CPLB page miss can result in lost write-through cache data writes */ | |
1250 | +#define ANOMALY_05000169 (__SILICON_REVISION__ < 3) | |
1251 | +/* DMA vs Core accesses to external memory */ | |
1252 | +#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) | |
1253 | +/* Cache Fill Buffer Data lost */ | |
1254 | +#define ANOMALY_05000174 (__SILICON_REVISION__ < 3) | |
1255 | +/* Overlapping Sequencer and Memory Stalls */ | |
1256 | +#define ANOMALY_05000175 (__SILICON_REVISION__ < 3) | |
1257 | +/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ | |
1258 | +#define ANOMALY_05000176 (__SILICON_REVISION__ < 3) | |
1259 | +/* Disabling the PPI resets the PPI configuration registers */ | |
1260 | +#define ANOMALY_05000181 (__SILICON_REVISION__ < 3) | |
1261 | +/* PPI TX Mode with 2 External Frame Syncs */ | |
1262 | +#define ANOMALY_05000185 (__SILICON_REVISION__ < 3) | |
1263 | +/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ | |
1264 | +#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) | |
1265 | +/* In PPI Transmit Modes with External Frame Syncs POLC */ | |
1266 | +#define ANOMALY_05000192 (__SILICON_REVISION__ < 3) | |
1267 | +/* Internal Voltage Regulator may not start up */ | |
1268 | +#define ANOMALY_05000206 (__SILICON_REVISION__ < 3) | |
1269 | ||
1270 | -#if defined(CONFIG_BF_REV_0_2) | |
1271 | -#define ANOMALY_05000067 /* Watchpoints (Hardware Breakpoints) are not | |
1272 | - * supported */ | |
1273 | -#define ANOMALY_05000109 /* Reserved bits in SYSCFG register not set at | |
1274 | - * power on */ | |
1275 | -#define ANOMALY_05000116 /* Trace Buffers may record discontinuities into | |
1276 | - * emulation mode and/or exception, NMI, reset | |
1277 | - * handlers */ | |
1278 | -#define ANOMALY_05000123 /* DTEST_COMMAND initiated memory access may be | |
1279 | - * incorrect if data cache or DMA is active */ | |
1280 | -#define ANOMALY_05000124 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, | |
1281 | - * or 1:1 */ | |
1282 | -#define ANOMALY_05000125 /* Erroneous exception when enabling cache */ | |
1283 | -#define ANOMALY_05000126 /* SPI clock polarity and phase bits incorrect | |
1284 | - * during booting */ | |
1285 | -#define ANOMALY_05000137 /* DMEM_CONTROL is not set on Reset */ | |
1286 | -#define ANOMALY_05000138 /* SPI boot will not complete if there is a zero fill | |
1287 | - * block in the loader file */ | |
1288 | -#define ANOMALY_05000140 /* Allowing the SPORT RX FIFO to fill will cause an | |
1289 | - * overflow */ | |
1290 | -#define ANOMALY_05000141 /* An Infinite Stall occurs with a particular sequence | |
1291 | - * of consecutive dual dag events */ | |
1292 | -#define ANOMALY_05000142 /* Interrupts may be lost when a programmable input | |
1293 | - * flag is configured to be edge sensitive */ | |
1294 | -#define ANOMALY_05000143 /* A read from external memory may return a wrong | |
1295 | - * value with data cache enabled */ | |
1296 | -#define ANOMALY_05000144 /* DMA and TESTSET conflict when both are accessing | |
1297 | - * external memory */ | |
1298 | -#define ANOMALY_05000145 /* In PWM_OUT mode, you must enable the PPI block to | |
1299 | - * generate a waveform from PPI_CLK */ | |
1300 | -#define ANOMALY_05000146 /* MDMA may lose the first few words of a descriptor | |
1301 | - * chain */ | |
1302 | -#define ANOMALY_05000147 /* The source MDMA descriptor may stop with a DMA | |
1303 | - * Error */ | |
1304 | -#define ANOMALY_05000148 /* When booting from a 16-bit asynchronous memory | |
1305 | - * device, the upper 8-bits of each word must be | |
1306 | - * 0x00 */ | |
1307 | -#define ANOMALY_05000153 /* Frame Delay in SPORT Multichannel Mode */ | |
1308 | -#define ANOMALY_05000154 /* SPORT TFS signal is active in Multi-channel mode | |
1309 | - * outside of valid channels */ | |
1310 | -#define ANOMALY_05000155 /* Timer1 can not be used for PWMOUT mode when a | |
1311 | - * certain PPI mode is in use */ | |
1312 | -#define ANOMALY_05000157 /* A killed 32-bit System MMR write will lead to | |
1313 | - * the next system MMR access thinking it should be | |
1314 | - * 32-bit. */ | |
1315 | -#define ANOMALY_05000163 /* SPORT transmit data is not gated by external frame | |
1316 | - * sync in certain conditions */ | |
1317 | -#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */ | |
1318 | -#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost | |
1319 | - * write-through cache data writes */ | |
1320 | -#define ANOMALY_05000173 /* DMA vs Core accesses to external memory */ | |
1321 | -#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */ | |
1322 | -#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */ | |
1323 | -#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an | |
1324 | - * accumulator saturation */ | |
1325 | -#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration | |
1326 | - * registers */ | |
1327 | -#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */ | |
1328 | -#define ANOMALY_05000191 /* PPI does not invert the Driving PPICLK edge in | |
1329 | - * Transmit Modes */ | |
1330 | -#define ANOMALY_05000192 /* In PPI Transmit Modes with External Frame Syncs | |
1331 | - * POLC */ | |
1332 | -#define ANOMALY_05000206 /* Internal Voltage Regulator may not start up */ | |
1333 | +/* Anomalies that don't exist on this proc */ | |
1334 | +#define ANOMALY_05000266 (0) | |
1335 | ||
1336 | #endif | |
1337 | - | |
1338 | -#endif /* _MACH_ANOMALY_H_ */ | |
1339 | Index: include/asm-blackfin/mach-bf533/bf533.h | |
1340 | =================================================================== | |
1341 | --- include/asm-blackfin/mach-bf533/bf533.h (revision 3448) | |
1342 | +++ include/asm-blackfin/mach-bf533/bf533.h (working copy) | |
1343 | @@ -226,7 +226,7 @@ | |
1344 | #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly | |
1345 | #endif | |
1346 | ||
1347 | -#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1) | |
1348 | +#if ANOMALY_05000273 && (CONFIG_CCLK_DIV == 1) | |
1349 | #error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK | |
1350 | #endif | |
1351 | ||
1352 | Index: include/asm-blackfin/mach-bf537/anomaly.h | |
1353 | =================================================================== | |
1354 | --- include/asm-blackfin/mach-bf537/anomaly.h (revision 3448) | |
1355 | +++ include/asm-blackfin/mach-bf537/anomaly.h (working copy) | |
1356 | @@ -7,109 +7,137 @@ | |
1357 | */ | |
1358 | ||
1359 | /* This file shoule be up to date with: | |
1360 | - * - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List | |
1361 | - * - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List | |
1362 | - * - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List | |
1363 | + * - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List | |
1364 | + * - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List | |
1365 | + * - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List | |
1366 | */ | |
1367 | ||
1368 | #ifndef _MACH_ANOMALY_H_ | |
1369 | #define _MACH_ANOMALY_H_ | |
1370 | ||
1371 | /* We do not support 0.1 silicon - sorry */ | |
1372 | -#if (defined(CONFIG_BF_REV_0_1)) | |
1373 | -#error Kernel will not work on BF537/6/4 Version 0.1 | |
1374 | +#if __SILICON_REVISION__ < 2 | |
1375 | +# error Kernel will not work on BF537 silicon version 0.0 or 0.1 | |
1376 | #endif | |
1377 | ||
1378 | -#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2)) | |
1379 | -#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in | |
1380 | - * slot1 and store of a P register in slot 2 is not | |
1381 | - * supported */ | |
1382 | -#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive | |
1383 | - * Channel DMA stops */ | |
1384 | -#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR | |
1385 | - * registers. */ | |
1386 | -#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out | |
1387 | - * upper bits*/ | |
1388 | -#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame | |
1389 | - * syncs */ | |
1390 | -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) | |
1391 | -#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is | |
1392 | - * Changed */ | |
1393 | +#if defined(__ADSPBF534__) | |
1394 | +# define ANOMALY_BF534 1 | |
1395 | +#else | |
1396 | +# define ANOMALY_BF534 0 | |
1397 | #endif | |
1398 | -#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on | |
1399 | - * SPORT external receive and transmit clocks. */ | |
1400 | -#define ANOMALY_05000272 /* Certain data cache write through modes fail for | |
1401 | - * VDDint <=0.9V */ | |
1402 | -#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */ | |
1403 | -#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after | |
1404 | - * an edge is detected may clear interrupt */ | |
1405 | -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is | |
1406 | - * not restored */ | |
1407 | -#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic | |
1408 | - * control */ | |
1409 | -#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when | |
1410 | - * killed in a particular stage*/ | |
1411 | -#define ANOMALY_05000310 /* False hardware errors caused by fetches at the | |
1412 | - * boundary of reserved memory */ | |
1413 | -#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC | |
1414 | - * registers are interrupted */ | |
1415 | -#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */ | |
1416 | -#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not | |
1417 | - * received properly */ | |
1418 | +#if defined(__ADSPBF536__) | |
1419 | +# define ANOMALY_BF536 1 | |
1420 | +#else | |
1421 | +# define ANOMALY_BF536 0 | |
1422 | #endif | |
1423 | +#if defined(__ADSPBF537__) | |
1424 | +# define ANOMALY_BF537 1 | |
1425 | +#else | |
1426 | +# define ANOMALY_BF537 0 | |
1427 | +#endif | |
1428 | ||
1429 | -#if defined(CONFIG_BF_REV_0_2) | |
1430 | -#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or | |
1431 | - * IDLE around a Change of Control causes | |
1432 | - * unpredictable results */ | |
1433 | -#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel | |
1434 | - * (TDM) */ | |
1435 | -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) | |
1436 | -#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */ | |
1437 | +/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ | |
1438 | +#define ANOMALY_05000074 (1) | |
1439 | +/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */ | |
1440 | +#define ANOMALY_05000119 (1) | |
1441 | +/* Rx.H cannot be used to access 16-bit System MMR registers */ | |
1442 | +#define ANOMALY_05000122 (1) | |
1443 | +/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ | |
1444 | +#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) | |
1445 | +/* PPI Data Lengths Between 8 and 16 do not zero out upper bits*/ | |
1446 | +#define ANOMALY_05000166 (1) /* XXX: deleted from BF537 sheet ? */ | |
1447 | +/* PPI_DELAY not functional in PPI modes with 0 frame syncs */ | |
1448 | +#define ANOMALY_05000180 (1) | |
1449 | +/* Instruction Cache Is Not Functional */ | |
1450 | +#define ANOMALY_05000237 (__SILICON_REVISION__ < 2) | |
1451 | +/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */ | |
1452 | +#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) | |
1453 | +/* Spurious Hardware Error from an access in the shadow of a conditional branch */ | |
1454 | +#define ANOMALY_05000245 (1) | |
1455 | +/* CLKIN Buffer Output Enable Reset Behavior Is Changed */ | |
1456 | +#define ANOMALY_05000247 (1) | |
1457 | +/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */ | |
1458 | +#define ANOMALY_05000250 (__SILICON_REVISION__ < 3) | |
1459 | +/* EMAC Tx DMA error after an early frame abort */ | |
1460 | +#define ANOMALY_05000252 (__SILICON_REVISION__ < 3) | |
1461 | +/* Maximum external clock speed for Timers */ | |
1462 | +#define ANOMALY_05000253 (__SILICON_REVISION__ < 3) | |
1463 | +/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */ | |
1464 | +#define ANOMALY_05000254 (__SILICON_REVISION__ > 2) | |
1465 | +/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */ | |
1466 | +#define ANOMALY_05000255 (__SILICON_REVISION__ < 3) | |
1467 | +/* EMAC MDIO input latched on wrong MDC edge */ | |
1468 | +#define ANOMALY_05000256 (__SILICON_REVISION__ < 3) | |
1469 | +/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */ | |
1470 | +#define ANOMALY_05000257 (__SILICON_REVISION__ < 3) | |
1471 | +/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */ | |
1472 | +#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2) | |
1473 | +/* ICPLB_STATUS MMR register may be corrupted */ | |
1474 | +#define ANOMALY_05000260 (__SILICON_REVISION__ == 2) | |
1475 | +/* DCPLB_FAULT_ADDR MMR register may be corrupted */ | |
1476 | +#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) | |
1477 | +/* Stores to data cache may be lost */ | |
1478 | +#define ANOMALY_05000262 (__SILICON_REVISION__ < 3) | |
1479 | +/* Hardware loop corrupted when taking an ICPLB exception */ | |
1480 | +#define ANOMALY_05000263 (__SILICON_REVISION__ == 2) | |
1481 | +/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */ | |
1482 | +#define ANOMALY_05000264 (__SILICON_REVISION__ < 3) | |
1483 | +/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */ | |
1484 | +#define ANOMALY_05000265 (1) | |
1485 | +/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ | |
1486 | +#define ANOMALY_05000268 (__SILICON_REVISION__ < 3) | |
1487 | +/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */ | |
1488 | +#define ANOMALY_05000270 (__SILICON_REVISION__ < 3) | |
1489 | +/* Certain data cache write through modes fail for VDDint <=0.9V */ | |
1490 | +#define ANOMALY_05000272 (1) | |
1491 | +/* Writes to Synchronous SDRAM memory may be lost */ | |
1492 | +#define ANOMALY_05000273 (__SILICON_REVISION__ < 3) | |
1493 | +/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */ | |
1494 | +#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) | |
1495 | +/* Disabling Peripherals with DMA running may cause DMA system instability */ | |
1496 | +#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) | |
1497 | +/* SPI Master boot mode does not work well with Atmel Data flash devices */ | |
1498 | +#define ANOMALY_05000280 (1) | |
1499 | +/* False Hardware Error Exception when ISR context is not restored */ | |
1500 | +#define ANOMALY_05000281 (__SILICON_REVISION__ < 3) | |
1501 | +/* Memory DMA corruption with 32-bit data and traffic control */ | |
1502 | +#define ANOMALY_05000282 (__SILICON_REVISION__ < 3) | |
1503 | +/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ | |
1504 | +#define ANOMALY_05000283 (__SILICON_REVISION__ < 3) | |
1505 | +/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ | |
1506 | +#define ANOMALY_05000285 (__SILICON_REVISION__ < 3) | |
1507 | +/* SPORTs may receive bad data if FIFOs fill up */ | |
1508 | +#define ANOMALY_05000288 (__SILICON_REVISION__ < 3) | |
1509 | +/* Memory to memory DMA source/destination descriptors must be in same memory space */ | |
1510 | +#define ANOMALY_05000301 (1) | |
1511 | +/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ | |
1512 | +#define ANOMALY_05000304 (__SILICON_REVISION__ < 3) | |
1513 | +/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ | |
1514 | +#define ANOMALY_05000305 (__SILICON_REVISION__ < 3) | |
1515 | +/* SCKELOW Bit Does Not Maintain State Through Hibernate */ | |
1516 | +#define ANOMALY_05000307 (__SILICON_REVISION__ < 3) | |
1517 | +/* Writing UART_THR while UART clock is disabled sends erroneous start bit */ | |
1518 | +#define ANOMALY_05000309 (__SILICON_REVISION__ < 3) | |
1519 | +/* False hardware errors caused by fetches at the boundary of reserved memory */ | |
1520 | +#define ANOMALY_05000310 (1) | |
1521 | +/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */ | |
1522 | +#define ANOMALY_05000312 (1) | |
1523 | +/* PPI is level sensitive on first transfer */ | |
1524 | +#define ANOMALY_05000313 (1) | |
1525 | +/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ | |
1526 | +#define ANOMALY_05000315 (__SILICON_REVISION__ < 3) | |
1527 | +/* EMAC RMII mode: collisions occur in Full Duplex mode */ | |
1528 | +#define ANOMALY_05000316 (__SILICON_REVISION__ < 3) | |
1529 | +/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */ | |
1530 | +#define ANOMALY_05000321 (__SILICON_REVISION__ < 3) | |
1531 | +/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ | |
1532 | +#define ANOMALY_05000322 (1) | |
1533 | + | |
1534 | +/* Anomalies that don't exist on this proc */ | |
1535 | +#define ANOMALY_05000125 (0) | |
1536 | +#define ANOMALY_05000183 (0) | |
1537 | +#define ANOMALY_05000198 (0) | |
1538 | +#define ANOMALY_05000266 (0) | |
1539 | +#define ANOMALY_05000311 (0) | |
1540 | + | |
1541 | #endif | |
1542 | -#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ | |
1543 | -#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event | |
1544 | - * interrupt not functional */ | |
1545 | -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) | |
1546 | -#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */ | |
1547 | -#endif | |
1548 | -#define ANOMALY_05000257 /* An interrupt or exception during short Hardware | |
1549 | - * loops may cause the instruction fetch unit to | |
1550 | - * malfunction */ | |
1551 | -#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of | |
1552 | - * the ICPLB Data registers differ */ | |
1553 | -#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ | |
1554 | -#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ | |
1555 | -#define ANOMALY_05000262 /* Stores to data cache may be lost */ | |
1556 | -#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */ | |
1557 | -#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE | |
1558 | - * instruction will cause an infinite stall in the | |
1559 | - * second to last instruction in a hardware loop */ | |
1560 | -#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running | |
1561 | - * and non-zero DEB_TRAFFIC_PERIOD value */ | |
1562 | -#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the | |
1563 | - * internal voltage regulator (VDDint) to decrease */ | |
1564 | -#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after | |
1565 | - * an edge is detected may clear interrupt */ | |
1566 | -#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause | |
1567 | - * DMA system instability */ | |
1568 | -#define ANOMALY_05000280 /* SPI Master boot mode does not work well with | |
1569 | - * Atmel Dataflash devices */ | |
1570 | -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context | |
1571 | - * is not restored */ | |
1572 | -#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic | |
1573 | - * control */ | |
1574 | -#define ANOMALY_05000283 /* System MMR Write Is Stalled Indefinitely When | |
1575 | - * Killed in a Particular Stage */ | |
1576 | -#define ANOMALY_05000285 /* New Feature: EMAC TX DMA Word Alignment | |
1577 | - * (Not Available On Older Silicon) */ | |
1578 | -#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */ | |
1579 | -#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously | |
1580 | - * On Next System MMR Access */ | |
1581 | -#define ANOMALY_05000316 /* EMAC RMII mode: collisions occur in Full Duplex | |
1582 | - * mode */ | |
1583 | -#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with | |
1584 | - * status No Carrier */ | |
1585 | -#endif /* CONFIG_BF_REV_0_2 */ | |
1586 | - | |
1587 | -#endif /* _MACH_ANOMALY_H_ */ | |
1588 | Index: include/asm-blackfin/mach-bf537/bf537.h | |
1589 | =================================================================== | |
1590 | --- include/asm-blackfin/mach-bf537/bf537.h (revision 3448) | |
1591 | +++ include/asm-blackfin/mach-bf537/bf537.h (working copy) | |
1592 | @@ -206,7 +206,7 @@ | |
1593 | #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly | |
1594 | #endif | |
1595 | ||
1596 | -#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1) | |
1597 | +#if ANOMALY_05000273 && (CONFIG_CCLK_DIV == 1) | |
1598 | #error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK | |
1599 | #endif | |
1600 | ||
1601 | Index: arch/blackfin/kernel/setup.c | |
1602 | =================================================================== | |
1603 | --- arch/blackfin/kernel/setup.c (revision 3448) | |
1604 | +++ arch/blackfin/kernel/setup.c (working copy) | |
1605 | @@ -179,14 +179,16 @@ | |
1606 | cclk = get_cclk(); | |
1607 | sclk = get_sclk(); | |
1608 | ||
1609 | -#if !defined(CONFIG_BFIN_KERNEL_CLOCK) && defined(ANOMALY_05000273) | |
1610 | - if (cclk == sclk) | |
1611 | +#if !defined(CONFIG_BFIN_KERNEL_CLOCK) | |
1612 | + if (ANOMALY_05000273 && cclk == sclk) | |
1613 | panic("ANOMALY 05000273, SCLK can not be same as CCLK"); | |
1614 | #endif | |
1615 | ||
1616 | -#if defined(ANOMALY_05000266) | |
1617 | - bfin_read_IMDMA_D0_IRQ_STATUS(); | |
1618 | - bfin_read_IMDMA_D1_IRQ_STATUS(); | |
1619 | +#ifdef BF561_FAMILY | |
1620 | + if (ANOMALY_05000266) { | |
1621 | + bfin_read_IMDMA_D0_IRQ_STATUS(); | |
1622 | + bfin_read_IMDMA_D1_IRQ_STATUS(); | |
1623 | + } | |
1624 | #endif | |
1625 | ||
1626 | #ifdef DEBUG_SERIAL_EARLY_INIT | |
1627 | @@ -260,7 +262,7 @@ | |
1628 | && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) | |
1629 | mtd_size = | |
1630 | PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); | |
1631 | -# if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263)) | |
1632 | +# if (defined(CONFIG_BLKFIN_CACHE) && ANOMALY_05000263) | |
1633 | /* Due to a Hardware Anomaly we need to limit the size of usable | |
1634 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | |
1635 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | |
1636 | @@ -289,7 +291,7 @@ | |
1637 | _ebss = memory_mtd_start; /* define _ebss for compatible */ | |
1638 | #endif /* CONFIG_MTD_UCLINUX */ | |
1639 | ||
1640 | -#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263)) | |
1641 | +#if (defined(CONFIG_BLKFIN_CACHE) && ANOMALY_05000263) | |
1642 | /* Due to a Hardware Anomaly we need to limit the size of usable | |
1643 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | |
1644 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | |
1645 | @@ -337,10 +339,8 @@ | |
1646 | printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu Mhz System Clock\n", | |
1647 | cclk / 1000000, sclk / 1000000); | |
1648 | ||
1649 | -#if defined(ANOMALY_05000273) | |
1650 | - if ((cclk >> 1) <= sclk) | |
1651 | + if (ANOMALY_05000273 && (cclk >> 1) <= sclk) | |
1652 | printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n"); | |
1653 | -#endif | |
1654 | ||
1655 | printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20); | |
1656 | printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20); | |
1657 | Index: arch/blackfin/kernel/cplbinit.c | |
1658 | =================================================================== | |
1659 | --- arch/blackfin/kernel/cplbinit.c (revision 3448) | |
1660 | +++ arch/blackfin/kernel/cplbinit.c (working copy) | |
1661 | @@ -230,8 +230,8 @@ | |
1662 | cplb_data[i].psize, | |
1663 | cplb_data[i].i_conf); | |
1664 | } else { | |
1665 | -#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263)) | |
1666 | - if (i == SDRAM_KERN) { | |
1667 | +#if defined(CONFIG_BLKFIN_CACHE) | |
1668 | + if (ANOMALY_05000263 && i == SDRAM_KERN) { | |
1669 | fill_cplbtab(t, | |
1670 | cplb_data[i].start, | |
1671 | cplb_data[i].end, | |
1672 | Index: arch/blackfin/kernel/bfin_gpio.c | |
1673 | =================================================================== | |
1674 | --- arch/blackfin/kernel/bfin_gpio.c (revision 3448) | |
1675 | +++ arch/blackfin/kernel/bfin_gpio.c (working copy) | |
1676 | @@ -330,7 +330,7 @@ | |
1677 | SET_GPIO_SC(maska) | |
1678 | SET_GPIO_SC(maskb) | |
1679 | ||
1680 | -#if defined(ANOMALY_05000311) | |
1681 | +#if ANOMALY_05000311 | |
1682 | void set_gpio_data(unsigned short gpio, unsigned short arg) | |
1683 | { | |
1684 | unsigned long flags; | |
1685 | @@ -349,7 +349,7 @@ | |
1686 | #endif | |
1687 | ||
1688 | ||
1689 | -#if defined(ANOMALY_05000311) | |
1690 | +#if ANOMALY_05000311 | |
1691 | void set_gpio_toggle(unsigned short gpio) | |
1692 | { | |
1693 | unsigned long flags; | |
1694 | @@ -387,7 +387,7 @@ | |
1695 | SET_GPIO_P(maskb) | |
1696 | ||
1697 | ||
1698 | -#if defined(ANOMALY_05000311) | |
1699 | +#if ANOMALY_05000311 | |
1700 | void set_gpiop_data(unsigned short gpio, unsigned short arg) | |
1701 | { | |
1702 | unsigned long flags; | |
1703 | @@ -421,7 +421,7 @@ | |
1704 | GET_GPIO(maskb) | |
1705 | ||
1706 | ||
1707 | -#if defined(ANOMALY_05000311) | |
1708 | +#if ANOMALY_05000311 | |
1709 | unsigned short get_gpio_data(unsigned short gpio) | |
1710 | { | |
1711 | unsigned long flags; | |
1712 | @@ -455,7 +455,7 @@ | |
1713 | GET_GPIO_P(maska) | |
1714 | GET_GPIO_P(maskb) | |
1715 | ||
1716 | -#if defined(ANOMALY_05000311) | |
1717 | +#if ANOMALY_05000311 | |
1718 | unsigned short get_gpiop_data(unsigned short gpio) | |
1719 | { | |
1720 | unsigned long flags; | |
1721 | Index: arch/blackfin/lib/memcmp.S | |
1722 | =================================================================== | |
1723 | --- arch/blackfin/lib/memcmp.S (revision 3448) | |
1724 | +++ arch/blackfin/lib/memcmp.S (working copy) | |
1725 | @@ -61,7 +61,7 @@ | |
1726 | ||
1727 | LSETUP (.Lquad_loop_s, .Lquad_loop_e) LC0=P1; | |
1728 | .Lquad_loop_s: | |
1729 | -#ifdef ANOMALY_05000202 | |
1730 | +#if ANOMALY_05000202 | |
1731 | R0 = [P0++]; | |
1732 | R1 = [I0++]; | |
1733 | #else | |
1734 | Index: arch/blackfin/lib/memcpy.S | |
1735 | =================================================================== | |
1736 | --- arch/blackfin/lib/memcpy.S (revision 3448) | |
1737 | +++ arch/blackfin/lib/memcpy.S (working copy) | |
1738 | @@ -98,7 +98,7 @@ | |
1739 | R0 = R1; | |
1740 | I1 = P1; | |
1741 | R3 = [I1++]; | |
1742 | -#ifdef ANOMALY_05000202 | |
1743 | +#if ANOMALY_05000202 | |
1744 | .Lword_loops: | |
1745 | [P0++] = R3; | |
1746 | .Lword_loope: | |
1747 | Index: arch/blackfin/lib/memmove.S | |
1748 | =================================================================== | |
1749 | --- arch/blackfin/lib/memmove.S (revision 3448) | |
1750 | +++ arch/blackfin/lib/memmove.S (working copy) | |
1751 | @@ -70,7 +70,7 @@ | |
1752 | R1 = [I0++]; | |
1753 | ||
1754 | LSETUP (.Lquad_loops, .Lquad_loope) LC0=P1; | |
1755 | -#ifdef ANOMALY_05000202 | |
1756 | +#if ANOMALY_05000202 | |
1757 | .Lquad_loops: | |
1758 | [P0++] = R1; | |
1759 | .Lquad_loope: | |
1760 | @@ -102,7 +102,7 @@ | |
1761 | R1 = B[P3--] (Z); | |
1762 | CC = P2 == 0; | |
1763 | IF CC JUMP .Lno_loop; | |
1764 | -#ifdef ANOMALY_05000245 | |
1765 | +#if ANOMALY_05000245 | |
1766 | NOP; | |
1767 | NOP; | |
1768 | #endif | |
1769 | Index: arch/blackfin/mach-bf533/head.S | |
1770 | =================================================================== | |
1771 | --- arch/blackfin/mach-bf533/head.S (revision 3448) | |
1772 | +++ arch/blackfin/mach-bf533/head.S (working copy) | |
1773 | @@ -151,13 +151,13 @@ | |
1774 | R0 = R0 & R1; | |
1775 | ||
1776 | /* Anomaly 05000125 */ | |
1777 | -#ifdef ANOMALY_05000125 | |
1778 | +#if ANOMALY_05000125 | |
1779 | CLI R2; | |
1780 | SSYNC; | |
1781 | #endif | |
1782 | [p0] = R0; | |
1783 | SSYNC; | |
1784 | -#ifdef ANOMALY_05000125 | |
1785 | +#if ANOMALY_05000125 | |
1786 | STI R2; | |
1787 | #endif | |
1788 | ||
1789 | @@ -169,13 +169,13 @@ | |
1790 | R0 = R0 & R1; | |
1791 | ||
1792 | /* Anomaly 05000125 */ | |
1793 | -#ifdef ANOMALY_05000125 | |
1794 | +#if ANOMALY_05000125 | |
1795 | CLI R2; | |
1796 | SSYNC; | |
1797 | #endif | |
1798 | [p0] = R0; | |
1799 | SSYNC; | |
1800 | -#ifdef ANOMALY_05000125 | |
1801 | +#if ANOMALY_05000125 | |
1802 | STI R2; | |
1803 | #endif | |
1804 | ||
1805 | @@ -264,7 +264,7 @@ | |
1806 | p0.l = .LWAIT_HERE; | |
1807 | p0.h = .LWAIT_HERE; | |
1808 | reti = p0; | |
1809 | -#if defined(ANOMALY_05000281) | |
1810 | +#if ANOMALY_05000281 | |
1811 | nop; nop; nop; | |
1812 | #endif | |
1813 | rti; | |
1814 | Index: arch/blackfin/mach-bf561/head.S | |
1815 | =================================================================== | |
1816 | --- arch/blackfin/mach-bf561/head.S (revision 3448) | |
1817 | +++ arch/blackfin/mach-bf561/head.S (working copy) | |
1818 | @@ -106,14 +106,13 @@ | |
1819 | R0 = ~ENICPLB; | |
1820 | R0 = R0 & R1; | |
1821 | ||
1822 | - /* Anomaly 05000125 */ | |
1823 | -#ifdef ANOMALY_05000125 | |
1824 | +#if ANOMALY_05000125 | |
1825 | CLI R2; | |
1826 | SSYNC; | |
1827 | #endif | |
1828 | [p0] = R0; | |
1829 | SSYNC; | |
1830 | -#ifdef ANOMALY_05000125 | |
1831 | +#if ANOMALY_05000125 | |
1832 | STI R2; | |
1833 | #endif | |
1834 | ||
1835 | @@ -125,13 +124,13 @@ | |
1836 | R0 = R0 & R1; | |
1837 | ||
1838 | /* Anomaly 05000125 */ | |
1839 | -#ifdef ANOMALY_05000125 | |
1840 | +#if ANOMALY_05000125 | |
1841 | CLI R2; | |
1842 | SSYNC; | |
1843 | #endif | |
1844 | [p0] = R0; | |
1845 | SSYNC; | |
1846 | -#ifdef ANOMALY_05000125 | |
1847 | +#if ANOMALY_05000125 | |
1848 | STI R2; | |
1849 | #endif | |
1850 | ||
1851 | @@ -220,7 +219,7 @@ | |
1852 | p0.l = .LWAIT_HERE; | |
1853 | p0.h = .LWAIT_HERE; | |
1854 | reti = p0; | |
1855 | -#if defined(ANOMALY_05000281) | |
1856 | +#if ANOMALY_05000281 | |
1857 | nop; nop; nop; | |
1858 | #endif | |
1859 | rti; | |
1860 | Index: arch/blackfin/mach-bf537/head.S | |
1861 | =================================================================== | |
1862 | --- arch/blackfin/mach-bf537/head.S (revision 3448) | |
1863 | +++ arch/blackfin/mach-bf537/head.S (working copy) | |
1864 | @@ -107,13 +107,13 @@ | |
1865 | R0 = R0 & R1; | |
1866 | ||
1867 | /* Anomaly 05000125 */ | |
1868 | -#ifdef ANOMALY_05000125 | |
1869 | +#if ANOMALY_05000125 | |
1870 | CLI R2; | |
1871 | SSYNC; | |
1872 | #endif | |
1873 | [p0] = R0; | |
1874 | SSYNC; | |
1875 | -#ifdef ANOMALY_05000125 | |
1876 | +#if ANOMALY_05000125 | |
1877 | STI R2; | |
1878 | #endif | |
1879 | ||
1880 | @@ -125,13 +125,13 @@ | |
1881 | R0 = R0 & R1; | |
1882 | ||
1883 | /* Anomaly 05000125 */ | |
1884 | -#ifdef ANOMALY_05000125 | |
1885 | +#if ANOMALY_05000125 | |
1886 | CLI R2; | |
1887 | SSYNC; | |
1888 | #endif | |
1889 | [p0] = R0; | |
1890 | SSYNC; | |
1891 | -#ifdef ANOMALY_05000125 | |
1892 | +#if ANOMALY_05000125 | |
1893 | STI R2; | |
1894 | #endif | |
1895 | ||
1896 | @@ -141,12 +141,12 @@ | |
1897 | */ | |
1898 | p0.h = hi(BFIN_PORT_MUX); | |
1899 | p0.l = lo(BFIN_PORT_MUX); | |
1900 | -#ifdef ANOMALY_05000212 | |
1901 | +#if ANOMALY_05000212 | |
1902 | R0.L = W[P0]; /* Read */ | |
1903 | SSYNC; | |
1904 | #endif | |
1905 | R0 = (PGDE_UART | PFTE_UART)(Z); | |
1906 | -#ifdef ANOMALY_05000212 | |
1907 | +#if ANOMALY_05000212 | |
1908 | W[P0] = R0.L; /* Write */ | |
1909 | SSYNC; | |
1910 | #endif | |
1911 | @@ -155,12 +155,12 @@ | |
1912 | ||
1913 | p0.h = hi(PORTF_FER); | |
1914 | p0.l = lo(PORTF_FER); | |
1915 | -#ifdef ANOMALY_05000212 | |
1916 | +#if ANOMALY_05000212 | |
1917 | R0.L = W[P0]; /* Read */ | |
1918 | SSYNC; | |
1919 | #endif | |
1920 | R0 = 0x000F(Z); | |
1921 | -#ifdef ANOMALY_05000212 | |
1922 | +#if ANOMALY_05000212 | |
1923 | W[P0] = R0.L; /* Write */ | |
1924 | SSYNC; | |
1925 | #endif | |
1926 | @@ -274,7 +274,7 @@ | |
1927 | p0.l = .LWAIT_HERE; | |
1928 | p0.h = .LWAIT_HERE; | |
1929 | reti = p0; | |
1930 | -#if defined(ANOMALY_05000281) | |
1931 | +#if ANOMALY_05000281 | |
1932 | nop; nop; nop; | |
1933 | #endif | |
1934 | rti; | |
1935 | Index: arch/blackfin/mach-bf548/head.S | |
1936 | =================================================================== | |
1937 | --- arch/blackfin/mach-bf548/head.S (revision 3448) | |
1938 | +++ arch/blackfin/mach-bf548/head.S (working copy) | |
1939 | @@ -172,7 +172,7 @@ | |
1940 | p0.l = .LWAIT_HERE; | |
1941 | p0.h = .LWAIT_HERE; | |
1942 | reti = p0; | |
1943 | -#if defined (ANOMALY_05000281) | |
1944 | +#if ANOMALY_05000281 | |
1945 | nop; | |
1946 | nop; | |
1947 | nop; | |
1948 | Index: arch/blackfin/mach-common/entry.S | |
1949 | =================================================================== | |
1950 | --- arch/blackfin/mach-common/entry.S (revision 3448) | |
1951 | +++ arch/blackfin/mach-common/entry.S (working copy) | |
1952 | @@ -69,7 +69,7 @@ | |
1953 | * patch up CPLB misses on the kernel stack. | |
1954 | */ | |
1955 | ENTRY(_ex_dcplb) | |
1956 | -#if defined(ANOMALY_05000261) | |
1957 | +#if ANOMALY_05000261 | |
1958 | /* | |
1959 | * Work around an anomaly: if we see a new DCPLB fault, return | |
1960 | * without doing anything. Then, if we get the same fault again, | |
1961 | @@ -137,7 +137,7 @@ | |
1962 | ||
1963 | _return_from_exception: | |
1964 | DEBUG_START_HWTRACE(p5, r7) | |
1965 | -#ifdef ANOMALY_05000257 | |
1966 | +#if ANOMALY_05000257 | |
1967 | R7=LC0; | |
1968 | LC0=R7; | |
1969 | R7=LC1; | |
1970 | @@ -634,7 +634,7 @@ | |
1971 | p1.h = _schedule_and_signal_from_int; | |
1972 | [p0] = p1; | |
1973 | csync; | |
1974 | -#if defined(ANOMALY_05000281) | |
1975 | +#if ANOMALY_05000281 | |
1976 | r0.l = lo(CONFIG_BOOT_LOAD); | |
1977 | r0.h = hi(CONFIG_BOOT_LOAD); | |
1978 | reti = r0; | |
1979 | @@ -648,7 +648,7 @@ | |
1980 | ENDPROC(_return_from_int) | |
1981 | ||
1982 | ENTRY(_lower_to_irq14) | |
1983 | -#if defined(ANOMALY_05000281) | |
1984 | +#if ANOMALY_05000281 | |
1985 | r0.l = lo(CONFIG_BOOT_LOAD); | |
1986 | r0.h = hi(CONFIG_BOOT_LOAD); | |
1987 | reti = r0; | |
1988 | @@ -1242,7 +1242,7 @@ | |
1989 | .endr | |
1990 | _exception_stack_top: | |
1991 | ||
1992 | -#if defined(ANOMALY_05000261) | |
1993 | +#if ANOMALY_05000261 | |
1994 | /* Used by the assembly entry point to work around an anomaly. */ | |
1995 | _last_cplb_fault_retx: | |
1996 | .long 0; | |
1997 | Index: arch/blackfin/mach-common/cplbmgr.S | |
1998 | =================================================================== | |
1999 | --- arch/blackfin/mach-common/cplbmgr.S (revision 3448) | |
2000 | +++ arch/blackfin/mach-common/cplbmgr.S (working copy) | |
2001 | @@ -405,7 +405,7 @@ | |
2002 | P3.L = _page_size_table; /* retrieve end address */ | |
2003 | P3.H = _page_size_table; /* retrieve end address */ | |
2004 | R3 = 0x1002; /* 16th - position, 2 bits -length */ | |
2005 | -#ifdef ANOMALY_05000209 | |
2006 | +#if ANOMALY_05000209 | |
2007 | nop; /* Anomaly 05000209 */ | |
2008 | #endif | |
2009 | R7 = EXTRACT(R1,R3.l); | |
2010 | Index: arch/blackfin/mach-common/cacheinit.S | |
2011 | =================================================================== | |
2012 | --- arch/blackfin/mach-common/cacheinit.S (revision 3448) | |
2013 | +++ arch/blackfin/mach-common/cacheinit.S (working copy) | |
2014 | @@ -38,7 +38,7 @@ | |
2015 | ||
2016 | .text | |
2017 | ||
2018 | -#ifdef ANOMALY_05000125 | |
2019 | +#if ANOMALY_05000125 | |
2020 | #if defined(CONFIG_BLKFIN_CACHE) | |
2021 | ENTRY(_bfin_write_IMEM_CONTROL) | |
2022 | ||
2023 | Index: arch/blackfin/mach-common/interrupt.S | |
2024 | =================================================================== | |
2025 | --- arch/blackfin/mach-common/interrupt.S (revision 3448) | |
2026 | +++ arch/blackfin/mach-common/interrupt.S (working copy) | |
2027 | @@ -140,7 +140,7 @@ | |
2028 | fp = 0; | |
2029 | #endif | |
2030 | ||
2031 | -#if defined (ANOMALY_05000283) || defined (ANOMALY_05000315) | |
2032 | +#if ANOMALY_05000283 || ANOMALY_05000315 | |
2033 | cc = r7 == r7; | |
2034 | p5.h = 0xffc0; | |
2035 | p5.l = 0x0014; | |
2036 | @@ -163,7 +163,7 @@ | |
2037 | #ifdef CONFIG_FRAME_POINTER | |
2038 | fp = 0; | |
2039 | #endif | |
2040 | -#ifdef ANOMALY_05000283 | |
2041 | +#if ANOMALY_05000283 | |
2042 | cc = r7 == r7; | |
2043 | p5.h = 0xffc0; | |
2044 | p5.l = 0x0014; | |
2045 | @@ -207,7 +207,7 @@ | |
2046 | #ifdef CONFIG_FRAME_POINTER | |
2047 | fp = 0; | |
2048 | #endif | |
2049 | -#ifdef ANOMALY_05000283 | |
2050 | +#if ANOMALY_05000283 | |
2051 | cc = r7 == r7; | |
2052 | p5.h = 0xffc0; | |
2053 | p5.l = 0x0014; | |
2054 | Index: drivers/video/bfin_adv7393fb.c | |
2055 | =================================================================== | |
2056 | --- drivers/video/bfin_adv7393fb.c (revision 3448) | |
2057 | +++ drivers/video/bfin_adv7393fb.c (working copy) | |
2058 | @@ -288,10 +288,10 @@ | |
2059 | #endif | |
2060 | ||
2061 | ||
2062 | -#if defined(ANOMALY_05000183) | |
2063 | - bfin_write_TIMER2_CONFIG(WDTH_CAP); | |
2064 | - bfin_write_TIMER_ENABLE(TIMEN2); | |
2065 | -#endif | |
2066 | + if (ANOMALY_05000183) { | |
2067 | + bfin_write_TIMER2_CONFIG(WDTH_CAP); | |
2068 | + bfin_write_TIMER_ENABLE(TIMEN2); | |
2069 | + } | |
2070 | ||
2071 | bfin_write_PPI_CONTROL(0x381E); | |
2072 | bfin_write_PPI_FRAME(fbdev->modes[mode].tot_lines); |