1 From 9ecb85954275f5a62293e1416dba107058609117 Mon Sep 17 00:00:00 2001
2 From: Mike Frysinger <vapier@gentoo.org>
3 Date: Tue, 14 Oct 2008 18:06:33 -0400
4 Subject: [PATCH] metrologic fork
7 u-boot-1.1.6/Makefile | 22 +-
8 u-boot-1.1.6/board/Focus/Focus.c | 516 +++++++++++++++++++
9 u-boot-1.1.6/board/Focus/Makefile | 59 +++
10 u-boot-1.1.6/board/IS4980/IS4980.c | 516 +++++++++++++++++++
11 u-boot-1.1.6/board/IS4980/Makefile | 59 +++
12 u-boot-1.1.6/board/Orbit3/Makefile | 59 +++
13 u-boot-1.1.6/board/Orbit3/Orbit3.c | 516 +++++++++++++++++++
14 u-boot-1.1.6/board/VuQuest2D/Makefile | 59 +++
15 u-boot-1.1.6/board/VuQuest2D/VuQuest2D.c | 418 +++++++++++++++
16 u-boot-1.1.6/board/VuQuest2D/VuQuest2D.h | 53 ++
17 u-boot-1.1.6/board/VuQuest2D/config.mk | 15 +
18 u-boot-1.1.6/board/VuQuest2D/spi.c | 533 ++++++++++++++++++++
19 u-boot-1.1.6/board/VuQuest2D/spi_flash.c | 2 +
20 u-boot-1.1.6/board/VuQuest2D/u-boot.lds.S | 136 +++++
21 u-boot-1.1.6/board/VuQuest2D/video.c | 187 +++++++
22 u-boot-1.1.6/board/VuQuest2D/video.h | 25 +
23 u-boot-1.1.6/common/Makefile | 2 +-
24 u-boot-1.1.6/common/cmd_bdinfo.c | 40 +-
25 u-boot-1.1.6/common/cmd_bootm.c | 13 +
26 u-boot-1.1.6/common/cmd_eeprom.c | 12 +
27 u-boot-1.1.6/common/cmd_load.c | 456 +++++++++++++++++
28 u-boot-1.1.6/common/cmd_mem.c | 96 ++++
29 u-boot-1.1.6/common/interface_select.c | 526 +++++++++++++++++++
30 u-boot-1.1.6/common/main.c | 123 +++++-
31 u-boot-1.1.6/common/metro_pf.c | 318 ++++++++++++
32 u-boot-1.1.6/cpu/blackfin/i2c.c | 36 ++-
33 u-boot-1.1.6/cpu/blackfin/serial.c | 82 +++
34 u-boot-1.1.6/examples/Makefile | 14 +
35 u-boot-1.1.6/include/Metrologic_Hardware.h | 69 +++
36 .../include/asm-blackfin/blackfin-config-post.h | 50 +--
37 .../include/asm-blackfin/blackfin_clocks.h | 56 ++
38 u-boot-1.1.6/include/asm-blackfin/mem_init.h | 338 +++++++++++++
39 u-boot-1.1.6/include/configs/Focus.h | 381 ++++++++++++++
40 u-boot-1.1.6/include/configs/IS4980.h | 378 ++++++++++++++
41 u-boot-1.1.6/include/configs/Orbit3.h | 378 ++++++++++++++
42 u-boot-1.1.6/include/configs/VuQuest2D.h | 309 ++++++++++++
43 u-boot-1.1.6/include/configs/bf533-stamp.h | 47 ++-
44 u-boot-1.1.6/include/configs/bf537-srv1.h | 50 ++-
45 u-boot-1.1.6/include/configs/bf537-stamp.h | 52 ++-
46 u-boot-1.1.6/include/configs/bfin_adi_common.h | 18 +-
47 u-boot-1.1.6/include/flash.h | 3 +-
48 u-boot-1.1.6/include/metro_pf.h | 103 ++++
49 u-boot-1.1.6/lib_blackfin/board.c | 30 ++-
50 u-boot-1.1.6/uses.mak | 5 +
51 44 files changed, 7051 insertions(+), 109 deletions(-)
52 create mode 100644 u-boot-1.1.6/board/Focus/Focus.c
53 create mode 100644 u-boot-1.1.6/board/Focus/Makefile
54 create mode 100644 u-boot-1.1.6/board/IS4980/IS4980.c
55 create mode 100644 u-boot-1.1.6/board/IS4980/Makefile
56 create mode 100644 u-boot-1.1.6/board/Orbit3/Makefile
57 create mode 100644 u-boot-1.1.6/board/Orbit3/Orbit3.c
58 create mode 100644 u-boot-1.1.6/board/VuQuest2D/Makefile
59 create mode 100644 u-boot-1.1.6/board/VuQuest2D/VuQuest2D.c
60 create mode 100644 u-boot-1.1.6/board/VuQuest2D/VuQuest2D.h
61 create mode 100644 u-boot-1.1.6/board/VuQuest2D/config.mk
62 create mode 100644 u-boot-1.1.6/board/VuQuest2D/spi.c
63 create mode 100644 u-boot-1.1.6/board/VuQuest2D/spi_flash.c
64 create mode 100644 u-boot-1.1.6/board/VuQuest2D/u-boot.lds.S
65 create mode 100644 u-boot-1.1.6/board/VuQuest2D/video.c
66 create mode 100644 u-boot-1.1.6/board/VuQuest2D/video.h
67 create mode 100644 u-boot-1.1.6/common/interface_select.c
68 create mode 100644 u-boot-1.1.6/common/metro_pf.c
69 create mode 100644 u-boot-1.1.6/include/Metrologic_Hardware.h
70 create mode 100644 u-boot-1.1.6/include/asm-blackfin/blackfin_clocks.h
71 create mode 100644 u-boot-1.1.6/include/asm-blackfin/mem_init.h
72 create mode 100644 u-boot-1.1.6/include/configs/Focus.h
73 create mode 100644 u-boot-1.1.6/include/configs/IS4980.h
74 create mode 100644 u-boot-1.1.6/include/configs/Orbit3.h
75 create mode 100644 u-boot-1.1.6/include/configs/VuQuest2D.h
76 create mode 100644 u-boot-1.1.6/include/metro_pf.h
77 create mode 100644 u-boot-1.1.6/uses.mak
79 diff --git a/u-boot-1.1.6/Makefile b/u-boot-1.1.6/Makefile
80 index b3502bb..e4e761d 100644
81 --- a/u-boot-1.1.6/Makefile
82 +++ b/u-boot-1.1.6/Makefile
86 # (C) Copyright 2000-2006
87 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
88 @@ -147,7 +148,7 @@ ifeq ($(ARCH),microblaze)
91 ifeq ($(ARCH),blackfin)
92 -CROSS_COMPILE = bfin-uclinux-
93 +CROSS_COMPILE = $(CROSS_COMPILE_PATH)/bfin-uclinux-
96 CROSS_COMPILE = avr32-
97 @@ -191,9 +192,21 @@ endif
98 LIBS += lib_$(ARCH)/lib$(ARCH).a
99 LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
100 fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a
102 +ifneq ($(BOARD), IS4980)
103 +ifneq ($(BOARD), Orbit3)
104 +ifneq ($(BOARD), VuQuest2D)
105 +ifneq ($(BOARD), Focus)
106 +ifneq ($(BOARD), bf533-stamp)
108 LIBS += disk/libdisk.a
117 LIBS += drivers/libdrivers.a
118 LIBS += drivers/nand/libnand.a
119 @@ -2264,6 +2277,9 @@ BFIN_BOARDS += cm-bf533 cm-bf537e cm-bf548 cm-bf561
120 # Misc third party boards
121 BFIN_BOARDS += bf537-minotaur bf537-srv1
124 +BFIN_BOARDS += Focus Orbit3 VuQuest2D IS4980
126 $(BFIN_BOARDS:%=%_config) : unconfig
127 @$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
128 @[ "$(SRCTREE)" != "$(OBJTREE)" ] && LNPREFIX="../../include2/asm/" || LNPREFIX="" ; \
129 @@ -2321,6 +2337,10 @@ clean:
130 rm -f $(obj)board/cm-bf537e/u-boot.lds
131 rm -f $(obj)board/cm-bf548/u-boot.lds
132 rm -f $(obj)board/cm-bf561/u-boot.lds
133 + rm -f $(obj)board/Focus/u-boot.lds
134 + rm -f $(obj)board/Orbit3/u-boot.lds
135 + rm -f $(obj)board/IS4980/u-boot.lds
136 + rm -f $(obj)board/VuQuest2D/u-boot.lds
137 rm -f $(obj)cpu/blackfin/bootrom-asm-offsets.[chs] $(obj).syms.u-boot.S
138 rm -f $(obj)include/bmp_logo.h
139 rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
140 diff --git a/u-boot-1.1.6/board/Focus/Focus.c b/u-boot-1.1.6/board/Focus/Focus.c
142 index 0000000..d2ab196
144 +++ b/u-boot-1.1.6/board/Focus/Focus.c
149 + * Copyright (c) 2008 Metrologic Instruments Inc.
150 + * Copyright (c) 2005-2007 Analog Devices Inc.
152 + * (C) Copyright 2000-2004
153 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
155 + * See file CREDITS for list of people who contributed to this
158 + * This program is free software; you can redistribute it and/or
159 + * modify it under the terms of the GNU General Public License as
160 + * published by the Free Software Foundation; either version 2 of
161 + * the License, or (at your option) any later version.
163 + * This program is distributed in the hope that it will be useful,
164 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
165 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
166 + * GNU General Public License for more details.
168 + * You should have received a copy of the GNU General Public License
169 + * along with this program; if not, write to the Free Software
170 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
171 + * MA 02110-1301 USA
176 +#include <command.h>
177 +#include <asm/blackfin.h>
179 +#include <linux/etherdevice.h>
181 +#define POST_WORD_ADDR 0xFF903FFC
183 +int checkboard(void)
185 + printf("Board: Metrologic Focus Decode Board\n");
186 + printf(" Support: http://www.metrologic.com/\n");
190 +#if defined(CONFIG_BFIN_IDE)
192 +void cf_outb(unsigned char val, volatile unsigned char *addr)
198 +unsigned char cf_inb(volatile unsigned char *addr)
200 + volatile unsigned char c;
208 +void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
212 + for (i = 0; i < words; i++)
213 + *(sect_buf + i) = *(addr);
217 +void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
221 + for (i = 0; i < words; i++)
222 + *(addr) = *(sect_buf + i);
225 +#endif /* CONFIG_BFIN_IDE */
227 +long int initdram(int board_type)
229 + DECLARE_GLOBAL_DATA_PTR;
232 + char *tmp = getenv("baudrate");
233 + brate = simple_strtoul(tmp, NULL, 16);
234 + printf("Serial Port initialized with Baud rate = %x\n", brate);
235 + printf("SDRAM attributes:\n");
236 + printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
237 + "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
239 + printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
240 + printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
242 + gd->bd->bi_memstart = CFG_SDRAM_BASE;
243 + gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
244 + return CFG_MAX_RAM_SIZE;
247 +int board_get_enetaddr(uchar *mac_addr)
250 +# define USE_MAC_IN_FLASH 0
252 +# define USE_MAC_IN_FLASH 1
254 + if (USE_MAC_IN_FLASH) {
255 + /* we cram the MAC in the last flash sector */
256 + uchar *board_mac_addr = (uchar *)0x203F0000;
258 + if (is_valid_ether_addr(board_mac_addr)) {
259 + memcpy(mac_addr, board_mac_addr, 6);
264 + puts("Warning: Generating 'random' MAC address\n");
266 + /* make something up */
267 + const char s[] = __DATE__;
270 + for (i = 0; i < 6; ++i) {
271 + asm("%0 = CYCLES;" : "=r" (cycles));
272 + mac_addr[i] = cycles ^ s[i];
274 + mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */
278 +void board_reset(void)
279 +{ /* FIXME: Alex Au: Don't know if we need to use this workaround... */
280 + /* workaround for weak pull ups on ssel */
281 + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
282 + bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10);
283 + bfin_write_PORTFIO_SET(PF10);
290 +#ifdef CONFIG_METROLOGIC_IO_INIT
292 +int metrologic_io_init(void)
296 + 0 (out) <<< Host RS232 TX >>>
297 + 1 (in) <<< Host RS232 RX >>>
298 + 2 (out) <<< I/O TX >>> / RDATA [h] (bfin_serial driver takes care of FER)
299 + 3 (in) <<< I/O RX >>> / CLKOUT (bfin_serial driver takes care of FER)
302 + 6 (out) cam_sync [l]
303 + 7 (out) PSOC RESET [l]
304 + 8 (in) <<< PPI_VSYNC >>> [later, input]
305 + 9 (in) <<< PPI_HSYNC >>> [later, input]
306 + 10 (out) <<< SPI_CS >>>
307 + 11 (out) <<< SPI_MOSI >>>
308 + 12 (in) <<< SPI_MISO >>>
309 + 13 (out) <<< SPI_CLOCK >>>
310 + 14 (out) SPI_WP [h]
311 + 15 (in) <<< PPI_Clock >>> [later, input]
315 + *pPORTF_FER = PF0|PF1|PF2|PF3|PF10|PF11|PF12|PF13; /* PPI enabled in image device driver */
316 + *pPORTFIO_DIR |= PF4|PF5|PF6|PF7|PF14;
317 + *pPORTFIO_DIR &= ~(PF8|PF9|PF15);
318 + *pPORTFIO_INEN &= ~(PF4|PF5|PF6|PF7|PF14 | PF8|PF9|PF15);
319 + *pPORTFIO &= ~(PF4|PF5|PF6|PF7);
324 + 0 (in) <<< PPI_Data >>> [later, input]
325 + 1 (in) <<< PPI_Data >>> [later, input]
326 + 2 (in) <<< PPI_Data >>> [later, input]
327 + 3 (in) <<< PPI_Data >>> [later, input]
328 + 4 (in) <<< PPI_Data >>> [later, input]
329 + 5 (in) <<< PPI_Data >>> [later, input]
330 + 6 (in) <<< PPI_Data >>> [later, input]
331 + 7 (in) <<< PPI_Data >>> [later, input]
332 + 8 (out) FOCUS_KBWEN [l] when all I/O are set, then low
333 + 9 (out) HOSTRTS ( Leave as input / output high until polarity is known )
334 + 10 (out) FOCUS_IORTS ( Leave as input / output high until polarity is known )
335 + 11 (out) FOCUS_KBWGATE [l]
336 + 12 (out) LED Voltage Enable [h]
337 + 13 (out) LED yellow [h]
338 + 14 (out) LED white [h]
339 + 15 (out) LED Blue [h]
344 + *pPORTGIO_DIR = PG8|PG9|PG10|PG11|PG12|PG13|PG14|PG15;
345 + *pPORTGIO_INEN = 0;
346 + *pPORTGIO |= PG9|PG10|PG12|PG13|PG14|PG15;
347 + *pPORTGIO &= ~(PG8|PG11);
351 + 0 (out) KBW_PCClk [l]
352 + 1 (out) KBS_PCDATA [l]
355 + 4 (in) PC_DET / IBM/USB_EN
358 + 7 (in) I/O CTS / SDATA
361 + 10 (in) READ SWITCH
362 + 11 (out) FRAM_WP [h]
363 + 12 (in) IR NEAR / FAR
364 + 13 (out) Ocillator En. (Active high) [h]
365 + 14 (out) Sensor Standby (Active low-Micron) [h]
366 + 15 (out) Sensor Reset (Active High-Micron)[l]
371 + *pPORTHIO_DIR = PH0|PH1|PH11|PH13|PH14|PH15;
372 + *pPORTHIO_INEN = PH2|PH3|PH4|PH5|PH6|PH7|PH8|PH9|PH10|PH12;
373 + *pPORTHIO |= PH11|PH13|PH14;
374 + *pPORTHIO &= ~(PH0|PH1|PH15);
376 + __builtin_bfin_ssync();
378 +#if defined(DEBUG_METRO_IO)
379 + printf("start Configure_Interface_IO()\r\n");
381 + Configure_Interface_IO();
382 +#if defined(DEBUG_METRO_IO)
383 + printf("done Configure_Interface_IO()\r\n");
390 +#endif /* CONFIG_METROLOGIC_IO_INIT */
391 +#if defined(CONFIG_MISC_INIT_R)
392 +/* miscellaneous platform dependent initialisations */
393 +int misc_init_r(void)
395 +#ifndef CFG_NO_FLASH
396 + /* we use the last sector for the MAC address / POST DXE */
397 + extern flash_info_t flash_info[];
398 + flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
401 +#if defined(CONFIG_BFIN_IDE)
402 +#if defined(CONFIG_BFIN_TRUE_IDE)
403 + /* Enable ATASEL when in True IDE mode */
404 + printf("Using CF True IDE Mode\n");
405 + cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
407 +#elif defined(CONFIG_BFIN_CF_IDE)
408 + /* Disable ATASEL when we're in Common Memory Mode */
409 + printf("Using CF Common Memory Mode\n");
410 + cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
412 +#elif defined(CONFIG_BFIN_HDD_IDE)
413 + printf("Using HDD IDE Mode\n");
416 +#endif /* CONFIG_BFIN_IDE */
419 +#endif /* CONFIG_MISC_INIT_R */
422 +#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
423 +/* Using sw10-PF5 as the hotkey */
424 +int post_hotkeys_pressed(void)
429 +/* Using sw10-PF5 as the hotkey */
430 +int post_hotkeys_pressed(void)
434 + unsigned short value;
436 + *pPORTF_FER &= ~PF5;
437 + *pPORTFIO_DIR &= ~PF5;
438 + *pPORTFIO_INEN |= PF5;
440 + printf("########Press SW10 to enter Memory POST########: %2d ", delay);
442 + for (i = 0; i < 100; i++) {
443 + value = *pPORTFIO & PF5;
449 + printf("\b\b\b%2d ", delay);
451 + printf("\b\b\b 0");
456 + printf("Hotkey has been pressed, Enter POST . . . . . .\n");
463 +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
464 +void post_word_store(ulong a)
466 + volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
470 +ulong post_word_load(void)
472 + volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
478 +int uart_post_test(int flags)
483 +#define BLOCK_SIZE 0x10000
484 +#define VERIFY_ADDR 0x2000000
485 +extern int erase_block_flash(int);
486 +extern int write_data(long lStart, long lCount, uchar * pnData);
487 +int flash_post_test(int flags)
489 + unsigned short *pbuf, *temp;
494 + pbuf = (unsigned short *)VERIFY_ADDR;
496 + for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
497 + offset = (n - 7) * BLOCK_SIZE;
498 + printf("--------Erase block:%2d..", n);
499 + erase_block_flash(n);
501 + printf("--------Program block:%2d...", n);
502 + write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
504 + printf("--------Verify block:%2d...", n);
505 + for (i = 0; i < BLOCK_SIZE; i += 2) {
506 + if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
513 + printf("failed\n");
515 + printf("OK %3d%%\r",
518 + FLASH_START_POST_BLOCK) *
519 + 100 / (FLASH_END_POST_BLOCK -
520 + FLASH_START_POST_BLOCK)));
532 +/****************************************************
533 + * LED1 ---- PF6 LED2 ---- PF7 *
534 + * LED3 ---- PF8 LED4 ---- PF9 *
535 + * LED5 ---- PF10 LED6 ---- PF11 *
536 + ****************************************************/
537 +int led_post_test(int flags)
539 + *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
540 + *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
541 + *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
542 + *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
547 + printf("\b\b\b\b\b\b\b");
551 + printf("\b\b\b\b\b\b\b");
555 + printf("\b\b\b\b\b\b\b");
559 + printf("\b\b\b\b\b\b\b");
563 + printf("\b\b\b\b\b\b\b");
566 + printf("\b\b\b\b\b\b\b ");
570 +/************************************************
571 + * SW10 ---- PF5 SW11 ---- PF4 *
572 + * SW12 ---- PF3 SW13 ---- PF2 *
573 + ************************************************/
574 +int button_post_test(int flags)
577 + unsigned short value = 0;
580 + *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
581 + *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
582 + *pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
584 + printf("\n--------Press SW10: %2d ", delay);
586 + for (i = 0; i < 100; i++) {
587 + value = *pPORTFIO & PF5;
593 + printf("\b\b\b%2d ", delay);
599 + printf("\b\bfailed");
603 + printf("\n--------Press SW11: %2d ", delay);
605 + for (i = 0; i < 100; i++) {
606 + value = *pPORTFIO & PF4;
612 + printf("\b\b\b%2d ", delay);
618 + printf("\b\bfailed");
622 + printf("\n--------Press SW12: %2d ", delay);
624 + for (i = 0; i < 100; i++) {
625 + value = *pPORTFIO & PF3;
631 + printf("\b\b\b%2d ", delay);
637 + printf("\b\bfailed");
641 + printf("\n--------Press SW13: %2d ", delay);
643 + for (i = 0; i < 100; i++) {
644 + value = *pPORTFIO & PF2;
650 + printf("\b\b\b%2d ", delay);
656 + printf("\b\bfailed");
662 diff --git a/u-boot-1.1.6/board/Focus/Makefile b/u-boot-1.1.6/board/Focus/Makefile
664 index 0000000..4d03b2c
666 +++ b/u-boot-1.1.6/board/Focus/Makefile
671 +# Copyright (c) 2005-2007 Analog Device Inc.
673 +# (C) Copyright 2000-2006
674 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
676 +# See file CREDITS for list of people who contributed to this
679 +# This program is free software; you can redistribute it and/or
680 +# modify it under the terms of the GNU General Public License as
681 +# published by the Free Software Foundation; either version 2 of
682 +# the License, or (at your option) any later version.
684 +# This program is distributed in the hope that it will be useful,
685 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
686 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
687 +# GNU General Public License for more details.
689 +# You should have received a copy of the GNU General Public License
690 +# along with this program; if not, write to the Free Software
691 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
695 +include $(TOPDIR)/config.mk
697 +LIB = $(obj)lib$(BOARD).a
699 +COBJS := $(BOARD).o post-memory.o spi_flash.o cmd_bf537led.o nand.o
700 +#COBJS := $(BOARD).o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
702 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
703 +OBJS := $(addprefix $(obj),$(COBJS))
704 +SOBJS := $(addprefix $(obj),$(SOBJS))
706 +$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
707 + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
709 +u-boot.lds: u-boot.lds.S
710 + $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
714 + rm -f $(SOBJS) $(OBJS)
717 + rm -f $(LIB) core *.bak .depend
719 +#########################################################################
721 +# defines $(obj).depend target
722 +include $(SRCTREE)/rules.mk
724 +sinclude $(obj).depend
726 +#########################################################################
727 diff --git a/u-boot-1.1.6/board/IS4980/IS4980.c b/u-boot-1.1.6/board/IS4980/IS4980.c
729 index 0000000..4836853
731 +++ b/u-boot-1.1.6/board/IS4980/IS4980.c
734 + * U-boot - Orbit3.c
736 + * Copyright (c) 2008 Metrologic Instruments Inc.
737 + * Copyright (c) 2005-2007 Analog Devices Inc.
739 + * (C) Copyright 2000-2004
740 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
742 + * See file CREDITS for list of people who contributed to this
745 + * This program is free software; you can redistribute it and/or
746 + * modify it under the terms of the GNU General Public License as
747 + * published by the Free Software Foundation; either version 2 of
748 + * the License, or (at your option) any later version.
750 + * This program is distributed in the hope that it will be useful,
751 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
752 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
753 + * GNU General Public License for more details.
755 + * You should have received a copy of the GNU General Public License
756 + * along with this program; if not, write to the Free Software
757 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
758 + * MA 02110-1301 USA
763 +#include <command.h>
764 +#include <asm/blackfin.h>
766 +#include <linux/etherdevice.h>
768 +#define POST_WORD_ADDR 0xFF903FFC
770 +int checkboard(void)
772 + printf("Board: Metrologic Genesis Decode Board\n");
773 + printf(" Support: http://www.metrologic.com/\n");
777 +#if defined(CONFIG_BFIN_IDE)
779 +void cf_outb(unsigned char val, volatile unsigned char *addr)
785 +unsigned char cf_inb(volatile unsigned char *addr)
787 + volatile unsigned char c;
795 +void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
799 + for (i = 0; i < words; i++)
800 + *(sect_buf + i) = *(addr);
804 +void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
808 + for (i = 0; i < words; i++)
809 + *(addr) = *(sect_buf + i);
812 +#endif /* CONFIG_BFIN_IDE */
814 +long int initdram(int board_type)
816 + DECLARE_GLOBAL_DATA_PTR;
819 + char *tmp = getenv("baudrate");
820 + brate = simple_strtoul(tmp, NULL, 16);
821 + printf("Serial Port initialized with Baud rate = %x\n", brate);
822 + printf("SDRAM attributes:\n");
823 + printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
824 + "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
826 + printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
827 + printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
829 + gd->bd->bi_memstart = CFG_SDRAM_BASE;
830 + gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
831 + return CFG_MAX_RAM_SIZE;
834 +int board_get_enetaddr(uchar *mac_addr)
837 +# define USE_MAC_IN_FLASH 0
839 +# define USE_MAC_IN_FLASH 1
841 + if (USE_MAC_IN_FLASH) {
842 + /* we cram the MAC in the last flash sector */
843 + uchar *board_mac_addr = (uchar *)0x203F0000;
845 + if (is_valid_ether_addr(board_mac_addr)) {
846 + memcpy(mac_addr, board_mac_addr, 6);
851 + puts("Warning: Generating 'random' MAC address\n");
853 + /* make something up */
854 + const char s[] = __DATE__;
857 + for (i = 0; i < 6; ++i) {
858 + asm("%0 = CYCLES;" : "=r" (cycles));
859 + mac_addr[i] = cycles ^ s[i];
861 + mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */
865 +void board_reset(void)
866 +{ /* FIXME: Alex Au: Don't know if we need to use this workaround... */
867 + /* workaround for weak pull ups on ssel */
868 + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
869 + bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10);
870 + bfin_write_PORTFIO_SET(PF10);
877 +#ifdef CONFIG_METROLOGIC_IO_INIT
879 +int metrologic_io_init(void)
883 + 0 (out) <<< Host RS232 TX >>>
884 + 1 (in) <<< Host RS232 RX >>>
885 + 2 (out) <<< White LED (PWM) >>> [h] turns on LED
886 + 3 (Out) <<< Blue LED (PWM) >>> [h] turns on LED
889 + 6 (out) cam_sync [l]
890 + 7 (out) Force On [l]
891 + 8 (in) <<< PPI_VSYNC >>> [later, input]
892 + 9 (in) <<< PPI_HSYNC >>> [later, input]
893 + 10 (out) <<< SPI_CS >>>
894 + 11 (out) <<< SPI_MOSI >>>
895 + 12 (in) <<< SPI_MISO >>>
896 + 13 (out) <<< SPI_CLOCK >>>
897 + 14 (out) SPI_WP [h]
898 + 15 (in) <<< PPI_Clock >>> [later, input]
902 + *pPORTF_FER = PF0|PF1|PF10|PF11|PF12|PF13; /* PPI enabled in image device driver */
903 + *pPORTFIO_DIR |= PF4|PF5|PF6|PF7|PF14;
904 + *pPORTFIO_DIR &= ~(PF2|PF3|PF8|PF9|PF15);
905 + *pPORTFIO_INEN &= ~(PF2|PF3|PF4|PF5|PF6|PF7|PF8|PF9|PF14|PF15);
906 + *pPORTFIO &= ~(PF4|PF5|PF6|PF7);
911 + 0 (in) <<< PPI_Data >>> [later, input]
912 + 1 (in) <<< PPI_Data >>> [later, input]
913 + 2 (in) <<< PPI_Data >>> [later, input]
914 + 3 (in) <<< PPI_Data >>> [later, input]
915 + 4 (in) <<< PPI_Data >>> [later, input]
916 + 5 (in) <<< PPI_Data >>> [later, input]
917 + 6 (in) <<< PPI_Data >>> [later, input]
918 + 7 (in) <<< PPI_Data >>> [later, input]
919 + 8 (out) DEC_KB_PASS_EN (Act. L) [l] (switch closed)
920 + 9 (out) HOSTRTS ( Leave as input / output high until polarity is known )
921 + *10 (out) LED_HIGH_V [h] (video low, snap-shot high) / (USB high)
922 + *11 (out) RESET IF (active H) [l]
923 + 12 (out) LED Voltage Enable [h]
924 + 13 (in) USB_KBW_BF (0=KBW;1=USB)
925 + 14 (in) BUF_PC_CLOCK_COL
926 + 15 (in) BUF_BSY_OR_LPD
931 + *pPORTGIO_DIR = PG8|PG9|PG10|PG11|PG12;
932 + *pPORTGIO_INEN = PG13|PG14|PG15;
933 + *pPORTGIO |= PG9|PG10|PG12;
934 + *pPORTGIO &= ~(PG8|PG11);
938 + *0 (in) BUF_PC_DATA_COL
939 + *1 (out) DEC_KB_CLOCK_BASE [l]*
940 + *2 (out) DEC_KB_DATA_BASE [l]*
941 + *3 (out) DEC_PC_CLOCK_BASE [l]*
942 + *4 (out) DEC_PC_DATA_BASE [l]*
943 + *5 (out) DEC_LT_PEN_BASE [l]*
945 + *7 (out) DEC_REQ_UC [l]*
948 + *10 (in) BUF_SPI_REQ
949 + *11 (in) BUF_EP_FULL_PAUSE
950 + *12 (out) Ocillator En. (Active high) [h]
951 + 13 (out) DC Mode (Active low) [h]
952 + *14 (out) NEAR_SEL [l]
953 + *15 (in) DEC_DTR_FULL
958 + *pPORTHIO_DIR = PH1|PH2|PH3|PH4|PH5|PH7|PH12|PH13|PH14;
959 + *pPORTHIO_INEN = ~(PH1|PH2|PH3|PH4|PH5|PH7|PH12|PH13|PH14);
960 + *pPORTHIO |= PH12|PH13;
961 + *pPORTHIO &= ~(PH1|PH2|PH3|PH4|PH5|PH7|PH14);
963 + __builtin_bfin_ssync();
965 +#if defined(DEBUG_METRO_IO)
966 + printf("start Configure_Interface_IO()\r\n");
968 + Configure_Interface_IO();
969 +#if defined(DEBUG_METRO_IO)
970 + printf("done Configure_Interface_IO()\r\n");
977 +#endif /* CONFIG_METROLOGIC_IO_INIT */
978 +#if defined(CONFIG_MISC_INIT_R)
979 +/* miscellaneous platform dependent initialisations */
980 +int misc_init_r(void)
982 +#ifndef CFG_NO_FLASH
983 + /* we use the last sector for the MAC address / POST DXE */
984 + extern flash_info_t flash_info[];
985 + flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
988 +#if defined(CONFIG_BFIN_IDE)
989 +#if defined(CONFIG_BFIN_TRUE_IDE)
990 + /* Enable ATASEL when in True IDE mode */
991 + printf("Using CF True IDE Mode\n");
992 + cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
994 +#elif defined(CONFIG_BFIN_CF_IDE)
995 + /* Disable ATASEL when we're in Common Memory Mode */
996 + printf("Using CF Common Memory Mode\n");
997 + cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
999 +#elif defined(CONFIG_BFIN_HDD_IDE)
1000 + printf("Using HDD IDE Mode\n");
1003 +#endif /* CONFIG_BFIN_IDE */
1006 +#endif /* CONFIG_MISC_INIT_R */
1009 +#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
1010 +/* Using sw10-PF5 as the hotkey */
1011 +int post_hotkeys_pressed(void)
1016 +/* Using sw10-PF5 as the hotkey */
1017 +int post_hotkeys_pressed(void)
1021 + unsigned short value;
1023 + *pPORTF_FER &= ~PF5;
1024 + *pPORTFIO_DIR &= ~PF5;
1025 + *pPORTFIO_INEN |= PF5;
1027 + printf("########Press SW10 to enter Memory POST########: %2d ", delay);
1029 + for (i = 0; i < 100; i++) {
1030 + value = *pPORTFIO & PF5;
1036 + printf("\b\b\b%2d ", delay);
1038 + printf("\b\b\b 0");
1043 + printf("Hotkey has been pressed, Enter POST . . . . . .\n");
1050 +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
1051 +void post_word_store(ulong a)
1053 + volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
1057 +ulong post_word_load(void)
1059 + volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
1060 + return *save_addr;
1065 +int uart_post_test(int flags)
1070 +#define BLOCK_SIZE 0x10000
1071 +#define VERIFY_ADDR 0x2000000
1072 +extern int erase_block_flash(int);
1073 +extern int write_data(long lStart, long lCount, uchar * pnData);
1074 +int flash_post_test(int flags)
1076 + unsigned short *pbuf, *temp;
1081 + pbuf = (unsigned short *)VERIFY_ADDR;
1083 + for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
1084 + offset = (n - 7) * BLOCK_SIZE;
1085 + printf("--------Erase block:%2d..", n);
1086 + erase_block_flash(n);
1088 + printf("--------Program block:%2d...", n);
1089 + write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
1091 + printf("--------Verify block:%2d...", n);
1092 + for (i = 0; i < BLOCK_SIZE; i += 2) {
1093 + if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
1100 + printf("failed\n");
1102 + printf("OK %3d%%\r",
1105 + FLASH_START_POST_BLOCK) *
1106 + 100 / (FLASH_END_POST_BLOCK -
1107 + FLASH_START_POST_BLOCK)));
1119 +/****************************************************
1120 + * LED1 ---- PF6 LED2 ---- PF7 *
1121 + * LED3 ---- PF8 LED4 ---- PF9 *
1122 + * LED5 ---- PF10 LED6 ---- PF11 *
1123 + ****************************************************/
1124 +int led_post_test(int flags)
1126 + *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
1127 + *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
1128 + *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
1129 + *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
1131 + printf("LED1 on");
1134 + printf("\b\b\b\b\b\b\b");
1135 + printf("LED2 on");
1138 + printf("\b\b\b\b\b\b\b");
1139 + printf("LED3 on");
1142 + printf("\b\b\b\b\b\b\b");
1143 + printf("LED4 on");
1146 + printf("\b\b\b\b\b\b\b");
1147 + printf("LED5 on");
1148 + *pPORTFIO |= PF10;
1150 + printf("\b\b\b\b\b\b\b");
1151 + printf("lED6 on");
1152 + *pPORTFIO |= PF11;
1153 + printf("\b\b\b\b\b\b\b ");
1157 +/************************************************
1158 + * SW10 ---- PF5 SW11 ---- PF4 *
1159 + * SW12 ---- PF3 SW13 ---- PF2 *
1160 + ************************************************/
1161 +int button_post_test(int flags)
1164 + unsigned short value = 0;
1167 + *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
1168 + *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
1169 + *pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
1171 + printf("\n--------Press SW10: %2d ", delay);
1173 + for (i = 0; i < 100; i++) {
1174 + value = *pPORTFIO & PF5;
1180 + printf("\b\b\b%2d ", delay);
1186 + printf("\b\bfailed");
1190 + printf("\n--------Press SW11: %2d ", delay);
1192 + for (i = 0; i < 100; i++) {
1193 + value = *pPORTFIO & PF4;
1199 + printf("\b\b\b%2d ", delay);
1205 + printf("\b\bfailed");
1209 + printf("\n--------Press SW12: %2d ", delay);
1211 + for (i = 0; i < 100; i++) {
1212 + value = *pPORTFIO & PF3;
1218 + printf("\b\b\b%2d ", delay);
1224 + printf("\b\bfailed");
1228 + printf("\n--------Press SW13: %2d ", delay);
1230 + for (i = 0; i < 100; i++) {
1231 + value = *pPORTFIO & PF2;
1237 + printf("\b\b\b%2d ", delay);
1243 + printf("\b\bfailed");
1249 diff --git a/u-boot-1.1.6/board/IS4980/Makefile b/u-boot-1.1.6/board/IS4980/Makefile
1250 new file mode 100644
1251 index 0000000..4d03b2c
1253 +++ b/u-boot-1.1.6/board/IS4980/Makefile
1256 +# U-boot - Makefile
1258 +# Copyright (c) 2005-2007 Analog Device Inc.
1260 +# (C) Copyright 2000-2006
1261 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1263 +# See file CREDITS for list of people who contributed to this
1266 +# This program is free software; you can redistribute it and/or
1267 +# modify it under the terms of the GNU General Public License as
1268 +# published by the Free Software Foundation; either version 2 of
1269 +# the License, or (at your option) any later version.
1271 +# This program is distributed in the hope that it will be useful,
1272 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
1273 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1274 +# GNU General Public License for more details.
1276 +# You should have received a copy of the GNU General Public License
1277 +# along with this program; if not, write to the Free Software
1278 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1279 +# MA 02111-1307 USA
1282 +include $(TOPDIR)/config.mk
1284 +LIB = $(obj)lib$(BOARD).a
1286 +COBJS := $(BOARD).o post-memory.o spi_flash.o cmd_bf537led.o nand.o
1287 +#COBJS := $(BOARD).o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
1289 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
1290 +OBJS := $(addprefix $(obj),$(COBJS))
1291 +SOBJS := $(addprefix $(obj),$(SOBJS))
1293 +$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
1294 + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
1296 +u-boot.lds: u-boot.lds.S
1297 + $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
1301 + rm -f $(SOBJS) $(OBJS)
1304 + rm -f $(LIB) core *.bak .depend
1306 +#########################################################################
1308 +# defines $(obj).depend target
1309 +include $(SRCTREE)/rules.mk
1311 +sinclude $(obj).depend
1313 +#########################################################################
1314 diff --git a/u-boot-1.1.6/board/Orbit3/Makefile b/u-boot-1.1.6/board/Orbit3/Makefile
1315 new file mode 100644
1316 index 0000000..4d03b2c
1318 +++ b/u-boot-1.1.6/board/Orbit3/Makefile
1321 +# U-boot - Makefile
1323 +# Copyright (c) 2005-2007 Analog Device Inc.
1325 +# (C) Copyright 2000-2006
1326 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1328 +# See file CREDITS for list of people who contributed to this
1331 +# This program is free software; you can redistribute it and/or
1332 +# modify it under the terms of the GNU General Public License as
1333 +# published by the Free Software Foundation; either version 2 of
1334 +# the License, or (at your option) any later version.
1336 +# This program is distributed in the hope that it will be useful,
1337 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
1338 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1339 +# GNU General Public License for more details.
1341 +# You should have received a copy of the GNU General Public License
1342 +# along with this program; if not, write to the Free Software
1343 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1344 +# MA 02111-1307 USA
1347 +include $(TOPDIR)/config.mk
1349 +LIB = $(obj)lib$(BOARD).a
1351 +COBJS := $(BOARD).o post-memory.o spi_flash.o cmd_bf537led.o nand.o
1352 +#COBJS := $(BOARD).o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
1354 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
1355 +OBJS := $(addprefix $(obj),$(COBJS))
1356 +SOBJS := $(addprefix $(obj),$(SOBJS))
1358 +$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
1359 + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
1361 +u-boot.lds: u-boot.lds.S
1362 + $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
1366 + rm -f $(SOBJS) $(OBJS)
1369 + rm -f $(LIB) core *.bak .depend
1371 +#########################################################################
1373 +# defines $(obj).depend target
1374 +include $(SRCTREE)/rules.mk
1376 +sinclude $(obj).depend
1378 +#########################################################################
1379 diff --git a/u-boot-1.1.6/board/Orbit3/Orbit3.c b/u-boot-1.1.6/board/Orbit3/Orbit3.c
1380 new file mode 100644
1381 index 0000000..b40b20c
1383 +++ b/u-boot-1.1.6/board/Orbit3/Orbit3.c
1386 + * U-boot - Orbit3.c
1388 + * Copyright (c) 2008 Metrologic Instruments Inc.
1389 + * Copyright (c) 2005-2007 Analog Devices Inc.
1391 + * (C) Copyright 2000-2004
1392 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1394 + * See file CREDITS for list of people who contributed to this
1397 + * This program is free software; you can redistribute it and/or
1398 + * modify it under the terms of the GNU General Public License as
1399 + * published by the Free Software Foundation; either version 2 of
1400 + * the License, or (at your option) any later version.
1402 + * This program is distributed in the hope that it will be useful,
1403 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1404 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1405 + * GNU General Public License for more details.
1407 + * You should have received a copy of the GNU General Public License
1408 + * along with this program; if not, write to the Free Software
1409 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
1410 + * MA 02110-1301 USA
1413 +#include <common.h>
1414 +#include <config.h>
1415 +#include <command.h>
1416 +#include <asm/blackfin.h>
1417 +#include <asm/io.h>
1418 +#include <linux/etherdevice.h>
1420 +#define POST_WORD_ADDR 0xFF903FFC
1422 +int checkboard(void)
1424 + printf("Board: Metrologic Genesis Decode Board\n");
1425 + printf(" Support: http://www.metrologic.com/\n");
1429 +#if defined(CONFIG_BFIN_IDE)
1431 +void cf_outb(unsigned char val, volatile unsigned char *addr)
1437 +unsigned char cf_inb(volatile unsigned char *addr)
1439 + volatile unsigned char c;
1447 +void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
1451 + for (i = 0; i < words; i++)
1452 + *(sect_buf + i) = *(addr);
1456 +void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
1460 + for (i = 0; i < words; i++)
1461 + *(addr) = *(sect_buf + i);
1464 +#endif /* CONFIG_BFIN_IDE */
1466 +long int initdram(int board_type)
1468 + DECLARE_GLOBAL_DATA_PTR;
1471 + char *tmp = getenv("baudrate");
1472 + brate = simple_strtoul(tmp, NULL, 16);
1473 + printf("Serial Port initialized with Baud rate = %x\n", brate);
1474 + printf("SDRAM attributes:\n");
1475 + printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
1476 + "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
1478 + printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
1479 + printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
1481 + gd->bd->bi_memstart = CFG_SDRAM_BASE;
1482 + gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
1483 + return CFG_MAX_RAM_SIZE;
1486 +int board_get_enetaddr(uchar *mac_addr)
1488 +#ifdef CFG_NO_FLASH
1489 +# define USE_MAC_IN_FLASH 0
1491 +# define USE_MAC_IN_FLASH 1
1493 + if (USE_MAC_IN_FLASH) {
1494 + /* we cram the MAC in the last flash sector */
1495 + uchar *board_mac_addr = (uchar *)0x203F0000;
1497 + if (is_valid_ether_addr(board_mac_addr)) {
1498 + memcpy(mac_addr, board_mac_addr, 6);
1503 + puts("Warning: Generating 'random' MAC address\n");
1505 + /* make something up */
1506 + const char s[] = __DATE__;
1509 + for (i = 0; i < 6; ++i) {
1510 + asm("%0 = CYCLES;" : "=r" (cycles));
1511 + mac_addr[i] = cycles ^ s[i];
1513 + mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */
1517 +void board_reset(void)
1518 +{ /* FIXME: Alex Au: Don't know if we need to use this workaround... */
1519 + /* workaround for weak pull ups on ssel */
1520 + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
1521 + bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10);
1522 + bfin_write_PORTFIO_SET(PF10);
1529 +#ifdef CONFIG_METROLOGIC_IO_INIT
1531 +int metrologic_io_init(void)
1535 + 0 (out) <<< Host RS232 TX >>>
1536 + 1 (in) <<< Host RS232 RX >>>
1537 + 2 (out) <<< White LED (PWM) >>> [l]
1538 + 3 (Out) <<< Blue LED (PWM) >>> [l]
1540 + 5 (out) Target [l]
1541 + 6 (out) cam_sync [l]
1542 + 7 (out) Force On [l]
1543 + 8 (in) <<< PPI_VSYNC >>> [later, input]
1544 + 9 (in) <<< PPI_HSYNC >>> [later, input]
1545 + 10 (out) <<< SPI_CS >>>
1546 + 11 (out) <<< SPI_MOSI >>>
1547 + 12 (in) <<< SPI_MISO >>>
1548 + 13 (out) <<< SPI_CLOCK >>>
1549 + 14 (out) SPI_WP [h]
1550 + 15 (in) <<< PPI_Clock >>> [later, input]
1554 + *pPORTF_FER = PF0|PF1|PF10|PF11|PF12|PF13; /* PPI enabled in image device driver */
1555 + *pPORTFIO_DIR |= PF4|PF5|PF6|PF7|PF14;
1556 + *pPORTFIO_DIR &= ~(PF2|PF3|PF8|PF9|PF15);
1557 + *pPORTFIO_INEN &= ~(PF2|PF3|PF4|PF5|PF6|PF7|PF8|PF9|PF14|PF15);
1558 + *pPORTFIO &= ~(PF4|PF5|PF6|PF7);
1559 + *pPORTFIO |= PF14;
1563 + 0 (in) <<< PPI_Data >>> [later, input]
1564 + 1 (in) <<< PPI_Data >>> [later, input]
1565 + 2 (in) <<< PPI_Data >>> [later, input]
1566 + 3 (in) <<< PPI_Data >>> [later, input]
1567 + 4 (in) <<< PPI_Data >>> [later, input]
1568 + 5 (in) <<< PPI_Data >>> [later, input]
1569 + 6 (in) <<< PPI_Data >>> [later, input]
1570 + 7 (in) <<< PPI_Data >>> [later, input]
1571 + *8 (out) DEC_KB_PASS_EN(N) [h]
1572 + 9 (out) HOSTRTS ( Leave as input / output high until polarity is known )
1573 + *10 (out) LED_HIGH_V [h] (video low, snap-shot high) / (USB high)
1574 + *11 (out) RESET IF (active H) [l]
1575 + 12 (out) LED Voltage Enable [h]
1576 + 13 (in) Spare ? Yellow LED ?
1577 + 14 (out) BUF_PC_DATA_COL [h]
1578 + 15 (in) IF_BUSY_LT_PEN_DATA
1583 + *pPORTGIO_DIR = PG8|PG9|PG10|PG11|PG12|PG14;
1584 + *pPORTGIO_INEN = PG15;
1585 + *pPORTGIO |= PG8|PG9|PG10|PG12|PG14;
1586 + *pPORTGIO &= ~(PG11);
1590 + *0 (in) BUF_PC_DATA_COL
1591 + *1 (out) DEC_KB_CLOCK_BASE [l]*
1592 + *2 (out) DEC_KB_DATA_BASE [l]*
1593 + *3 (out) DEC_PC_CLOCK_BASE [l]*
1594 + *4 (out) DEC_PC_DATA_BASE [l]*
1595 + *5 (out) DEC_LT_PEN_BASE [l]*
1597 + *7 (out) DEC_REQ_UC [l]*
1600 + *10 (in) BUF_SPI_REQ
1601 + *11 (in) BUF_EP_FULL_PAUSE
1602 + *12 (out) Ocillator En. (Active high) [h]
1603 + 13 (out) DC Mode (Active low) [h]
1604 + *14 (out) NEAR_SEL [l]
1605 + *15 (in) DEC_DTR_FULL
1610 + *pPORTHIO_DIR = PH1|PH2|PH3|PH4|PH5|PH7|PH12|PH13|PH14;
1611 + *pPORTHIO_INEN = ~(PH1|PH2|PH3|PH4|PH5|PH7|PH12|PH13|PH14);
1612 + *pPORTHIO |= PH12|PH13;
1613 + *pPORTHIO &= ~(PH1|PH2|PH3|PH4|PH5|PH7|PH14);
1615 + __builtin_bfin_ssync();
1617 +#if defined(DEBUG_METRO_IO)
1618 + printf("start Configure_Interface_IO()\r\n");
1620 + Configure_Interface_IO();
1621 +#if defined(DEBUG_METRO_IO)
1622 + printf("done Configure_Interface_IO()\r\n");
1629 +#endif /* CONFIG_METROLOGIC_IO_INIT */
1630 +#if defined(CONFIG_MISC_INIT_R)
1631 +/* miscellaneous platform dependent initialisations */
1632 +int misc_init_r(void)
1634 +#ifndef CFG_NO_FLASH
1635 + /* we use the last sector for the MAC address / POST DXE */
1636 + extern flash_info_t flash_info[];
1637 + flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
1640 +#if defined(CONFIG_BFIN_IDE)
1641 +#if defined(CONFIG_BFIN_TRUE_IDE)
1642 + /* Enable ATASEL when in True IDE mode */
1643 + printf("Using CF True IDE Mode\n");
1644 + cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
1646 +#elif defined(CONFIG_BFIN_CF_IDE)
1647 + /* Disable ATASEL when we're in Common Memory Mode */
1648 + printf("Using CF Common Memory Mode\n");
1649 + cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
1651 +#elif defined(CONFIG_BFIN_HDD_IDE)
1652 + printf("Using HDD IDE Mode\n");
1655 +#endif /* CONFIG_BFIN_IDE */
1658 +#endif /* CONFIG_MISC_INIT_R */
1661 +#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
1662 +/* Using sw10-PF5 as the hotkey */
1663 +int post_hotkeys_pressed(void)
1668 +/* Using sw10-PF5 as the hotkey */
1669 +int post_hotkeys_pressed(void)
1673 + unsigned short value;
1675 + *pPORTF_FER &= ~PF5;
1676 + *pPORTFIO_DIR &= ~PF5;
1677 + *pPORTFIO_INEN |= PF5;
1679 + printf("########Press SW10 to enter Memory POST########: %2d ", delay);
1681 + for (i = 0; i < 100; i++) {
1682 + value = *pPORTFIO & PF5;
1688 + printf("\b\b\b%2d ", delay);
1690 + printf("\b\b\b 0");
1695 + printf("Hotkey has been pressed, Enter POST . . . . . .\n");
1702 +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
1703 +void post_word_store(ulong a)
1705 + volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
1709 +ulong post_word_load(void)
1711 + volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
1712 + return *save_addr;
1717 +int uart_post_test(int flags)
1722 +#define BLOCK_SIZE 0x10000
1723 +#define VERIFY_ADDR 0x2000000
1724 +extern int erase_block_flash(int);
1725 +extern int write_data(long lStart, long lCount, uchar * pnData);
1726 +int flash_post_test(int flags)
1728 + unsigned short *pbuf, *temp;
1733 + pbuf = (unsigned short *)VERIFY_ADDR;
1735 + for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
1736 + offset = (n - 7) * BLOCK_SIZE;
1737 + printf("--------Erase block:%2d..", n);
1738 + erase_block_flash(n);
1740 + printf("--------Program block:%2d...", n);
1741 + write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
1743 + printf("--------Verify block:%2d...", n);
1744 + for (i = 0; i < BLOCK_SIZE; i += 2) {
1745 + if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
1752 + printf("failed\n");
1754 + printf("OK %3d%%\r",
1757 + FLASH_START_POST_BLOCK) *
1758 + 100 / (FLASH_END_POST_BLOCK -
1759 + FLASH_START_POST_BLOCK)));
1771 +/****************************************************
1772 + * LED1 ---- PF6 LED2 ---- PF7 *
1773 + * LED3 ---- PF8 LED4 ---- PF9 *
1774 + * LED5 ---- PF10 LED6 ---- PF11 *
1775 + ****************************************************/
1776 +int led_post_test(int flags)
1778 + *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
1779 + *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
1780 + *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
1781 + *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
1783 + printf("LED1 on");
1786 + printf("\b\b\b\b\b\b\b");
1787 + printf("LED2 on");
1790 + printf("\b\b\b\b\b\b\b");
1791 + printf("LED3 on");
1794 + printf("\b\b\b\b\b\b\b");
1795 + printf("LED4 on");
1798 + printf("\b\b\b\b\b\b\b");
1799 + printf("LED5 on");
1800 + *pPORTFIO |= PF10;
1802 + printf("\b\b\b\b\b\b\b");
1803 + printf("lED6 on");
1804 + *pPORTFIO |= PF11;
1805 + printf("\b\b\b\b\b\b\b ");
1809 +/************************************************
1810 + * SW10 ---- PF5 SW11 ---- PF4 *
1811 + * SW12 ---- PF3 SW13 ---- PF2 *
1812 + ************************************************/
1813 +int button_post_test(int flags)
1816 + unsigned short value = 0;
1819 + *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
1820 + *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
1821 + *pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
1823 + printf("\n--------Press SW10: %2d ", delay);
1825 + for (i = 0; i < 100; i++) {
1826 + value = *pPORTFIO & PF5;
1832 + printf("\b\b\b%2d ", delay);
1838 + printf("\b\bfailed");
1842 + printf("\n--------Press SW11: %2d ", delay);
1844 + for (i = 0; i < 100; i++) {
1845 + value = *pPORTFIO & PF4;
1851 + printf("\b\b\b%2d ", delay);
1857 + printf("\b\bfailed");
1861 + printf("\n--------Press SW12: %2d ", delay);
1863 + for (i = 0; i < 100; i++) {
1864 + value = *pPORTFIO & PF3;
1870 + printf("\b\b\b%2d ", delay);
1876 + printf("\b\bfailed");
1880 + printf("\n--------Press SW13: %2d ", delay);
1882 + for (i = 0; i < 100; i++) {
1883 + value = *pPORTFIO & PF2;
1889 + printf("\b\b\b%2d ", delay);
1895 + printf("\b\bfailed");
1901 diff --git a/u-boot-1.1.6/board/VuQuest2D/Makefile b/u-boot-1.1.6/board/VuQuest2D/Makefile
1902 new file mode 100644
1903 index 0000000..1a924d9
1905 +++ b/u-boot-1.1.6/board/VuQuest2D/Makefile
1908 +# U-boot - Makefile
1910 +# Copyright (c) 2005-2008 Analog Device Inc.
1912 +# (C) Copyright 2000-2006
1913 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1915 +# See file CREDITS for list of people who contributed to this
1918 +# This program is free software; you can redistribute it and/or
1919 +# modify it under the terms of the GNU General Public License as
1920 +# published by the Free Software Foundation; either version 2 of
1921 +# the License, or (at your option) any later version.
1923 +# This program is distributed in the hope that it will be useful,
1924 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
1925 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1926 +# GNU General Public License for more details.
1928 +# You should have received a copy of the GNU General Public License
1929 +# along with this program; if not, write to the Free Software
1930 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1931 +# MA 02111-1307 USA
1934 +include $(TOPDIR)/config.mk
1936 +LIB = $(obj)lib$(BOARD).a
1938 +#COBJS := $(BOARD).o spi_flash.o video.o
1939 +COBJS := $(BOARD).o spi.o video.o
1941 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
1942 +OBJS := $(addprefix $(obj),$(COBJS))
1943 +SOBJS := $(addprefix $(obj),$(SOBJS))
1945 +$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
1946 + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
1948 +u-boot.lds: u-boot.lds.S
1949 + $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
1953 + rm -f $(SOBJS) $(OBJS)
1956 + rm -f $(LIB) core *.bak .depend
1958 +#########################################################################
1960 +# defines $(obj).depend target
1961 +include $(SRCTREE)/rules.mk
1963 +sinclude $(obj).depend
1965 +#########################################################################
1966 diff --git a/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.c b/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.c
1967 new file mode 100644
1968 index 0000000..04647d7
1970 +++ b/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.c
1973 + * U-boot - stamp.c STAMP board specific routines
1975 + * Copyright (c) 2005-2007 Analog Devices Inc.
1977 + * (C) Copyright 2000-2004
1978 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1980 + * See file CREDITS for list of people who contributed to this
1983 + * This program is free software; you can redistribute it and/or
1984 + * modify it under the terms of the GNU General Public License as
1985 + * published by the Free Software Foundation; either version 2 of
1986 + * the License, or (at your option) any later version.
1988 + * This program is distributed in the hope that it will be useful,
1989 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1990 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1991 + * GNU General Public License for more details.
1993 + * You should have received a copy of the GNU General Public License
1994 + * along with this program; if not, write to the Free Software
1995 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
1996 + * MA 02110-1301 USA
1999 +#include <common.h>
2000 +#include <asm/blackfin.h>
2001 +#include <asm/io.h>
2002 +#include <asm/mach-common/bits/ebiu.h>
2003 +#include "VuQuest2D.h"
2004 +#include "Metrologic_Hardware.h"
2006 +#define STATUS_LED_OFF 0
2007 +#define STATUS_LED_ON 1
2009 +#ifdef CONFIG_SHOW_BOOT_PROGRESS
2010 +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
2012 +# define SHOW_BOOT_PROGRESS(arg)
2015 +#ifdef CONFIG_METROLOGIC_IO_INIT
2016 +void set_VQ_default_io(void);
2019 +extern void Configure_Interface_IO(void);
2020 +extern void Configure_RTS_Pin(void);
2021 +extern int get_pfx_level(int pf_num);
2023 +#if (CONFIG_METROLOGIC_VQ2D_REV > 1)
2028 +#define VQ2D_RTS_PIN 6
2029 + int fio_dir = *pFIO_DIR;
2030 + int fio_ilen = *pFIO_INEN;
2033 + *pFIO_DIR &= ~(PF6);
2034 + *pFIO_INEN |= PF6;
2036 + pf6_level = get_pfx_level(VQ2D_RTS_PIN);
2038 + *pFIO_DIR = fio_dir;
2039 + *pFIO_INEN = fio_ilen;
2041 + if (pf6_level == 0)
2043 + return (241 + 255) / 2;
2047 + return (113 + 127) / 2;
2052 +Configure_VQ2D_Interface_IO(int interface_board)
2054 + if (interface_board == RS232_BOARD)
2056 +#define PWR_DWN_PIN 9
2057 +#define PWR_ON_PIN 5
2058 + Configure_RTS_Pin();
2061 + *pFIO_INEN &= ~PF9;
2062 + *pFIO_FLAG_D |= PF5;
2063 + *pFIO_FLAG_D &= ~PF9; /* PWR_DWN will be turned off at img.ko */
2067 +#define SLAVE_BUSY_PIN 9
2069 + *pFIO_DIR &= ~(PF9);
2072 + /* power down pin handled by silabs */
2075 +#endif /* #if (CONFIG_METROLOGIC_VQ2D_REV > 1) */
2077 +int checkboard(void)
2079 + printf("CPU: ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28);
2080 + printf("Board: Metrologic VuQuest2D decode board\n");
2081 + printf(" Support: http://www.metrologic.com/\n");
2085 +long int initdram(int board_type)
2087 + DECLARE_GLOBAL_DATA_PTR;
2089 + printf("SDRAM attributes:\n");
2091 + (" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
2092 + "CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11),
2093 + (SDRAM_tRAS >> 6), (SDRAM_tWR >> 19), (SDRAM_CL >> 2));
2094 + printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
2095 + printf("Bank size = %d MB\n", 128);
2097 + gd->bd->bi_memstart = CFG_SDRAM_BASE;
2098 + gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
2099 + return (gd->bd->bi_memsize);
2102 +void swap_to(int device_id)
2104 +#ifdef CONFIG_METROLOGIC_IO_INIT
2105 + if (device_id == FLASH)
2107 + bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF2);
2109 + bfin_write_FIO_FLAG_S(PF2);
2113 + bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0);
2115 + bfin_write_FIO_FLAG_C(PF1);
2116 + if (device_id == ETHERNET)
2117 + bfin_write_FIO_FLAG_S(PF0);
2118 + else if (device_id == FLASH)
2119 + bfin_write_FIO_FLAG_C(PF0);
2121 + printf("Unknown device to switch\n");
2126 +#if defined(CONFIG_MISC_INIT_R)
2127 +/* miscellaneous platform dependent initialisations */
2128 +int misc_init_r(void)
2133 + /* Check whether CF card is inserted */
2134 + *pFIO_EDGE = FIO_EDGE_CF_BITS;
2135 + *pFIO_POLAR = FIO_POLAR_CF_BITS;
2136 + for (i = 0; i < 0x300; i++)
2139 + if ((*pFIO_FLAG_S) & CF_STAT_BITS) {
2145 + *pFIO_EDGE = FIO_EDGE_BITS;
2146 + *pFIO_POLAR = FIO_POLAR_BITS;
2149 + printf("Booting from COMPACT flash\n");
2151 + for (i = 0; i < 0x1000; i++)
2153 + for (i = 0; i < 0x1000; i++)
2155 + for (i = 0; i < 0x1000; i++)
2161 + setenv("bootargs", "");
2163 + "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
2165 + printf("Booting from FLASH\n");
2171 +#ifdef CONFIG_STAMP_CF
2173 +void cf_outb(unsigned char val, volatile unsigned char *addr)
2176 + * Set PF1 PF0 respectively to 0 1 to divert address
2177 + * to the expansion memory banks
2179 + *pFIO_FLAG_S = CF_PF0;
2180 + *pFIO_FLAG_C = CF_PF1;
2186 + /* Setback PF1 PF0 to 0 0 to address external
2188 + *(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0;
2192 +unsigned char cf_inb(volatile unsigned char *addr)
2194 + volatile unsigned char c;
2196 + *pFIO_FLAG_S = CF_PF0;
2197 + *pFIO_FLAG_C = CF_PF1;
2203 + *pFIO_FLAG_C = CF_PF1_PF0;
2209 +void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
2213 + *pFIO_FLAG_S = CF_PF0;
2214 + *pFIO_FLAG_C = CF_PF1;
2217 + for (i = 0; i < words; i++) {
2218 + *(sect_buf + i) = *(addr);
2222 + *pFIO_FLAG_C = CF_PF1_PF0;
2226 +void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
2230 + *pFIO_FLAG_S = CF_PF0;
2231 + *pFIO_FLAG_C = CF_PF1;
2234 + for (i = 0; i < words; i++) {
2235 + *(addr) = *(sect_buf + i);
2239 + *pFIO_FLAG_C = CF_PF1_PF0;
2244 +#ifdef CONFIG_METROLOGIC_IO_INIT
2246 +void set_VQ_default_io(void)
2249 + 0 - (Out?) I2C Clock
2250 + 1 - (In?) I2C Data
2251 + 2 - (Out) SPI chip select
2252 + 3 - (In?) nWake / PPI_FS3
2253 + 4 - (Out) Target Pin
2254 + 5 - (Out) nGoodRead
2257 + 8 - (Out) Minflash / IllumOn
2258 + 9 - (Out?) nPowerDown (RS232) / (In) Slave_Busy (USB)
2259 + 10 - (Out) CamSync
2260 + 11 - (In) nTrigger (Input to decode)
2262 + 12 - (In) PPI Data
2263 + 13 - (In) PPI Data
2264 + 14 - (In) PPI Data
2265 + 15 - (In) PPI Data
2273 +#if (CONFIG_METROLOGIC_VQ2D_REV > 1)
2274 + *pFIO_DIR |= PF0|PF1|PF2|PF4|PF5|PF8|PF10;
2275 + *pFIO_DIR &= ~(PF3 | PF6|PF9 | PF12|PF13|PF14|PF15);
2277 + *pFIO_DIR |= PF0|PF1|PF2|PF4|PF5|PF8|PF9|PF10;
2278 + *pFIO_DIR &= ~(PF3 | PF12|PF13|PF14|PF15);
2285 +#if (CONFIG_METROLOGIC_VQ2D_REV > 1)
2286 + *pFIO_INEN &= ~(PF0|PF1|PF2 | PF4|PF5|PF8|PF10 | PF12|PF13|PF14|PF15);
2287 + *pFIO_INEN |= PF3 | PF6 | PF7 | PF9 | PF11;
2289 + *pFIO_INEN &= ~(PF0|PF1|PF2 | PF4|PF5|PF6|PF8|PF9|PF10);
2290 + *pFIO_INEN |= PF3 | PF7 | PF11;
2303 + *pFIO_FLAG_D &= ~(PF0|PF1 | PF4|PF8|PF10);
2304 +#if (CONFIG_METROLOGIC_VQ2D_REV > 1)
2305 + *pFIO_FLAG_D |= PF2;
2306 + *pFIO_FLAG_D &= ~PF5;
2308 + *pFIO_FLAG_D |= PF2|PF5|PF9;
2312 + __builtin_bfin_ssync();
2315 +int metrologic_io_init(void)
2317 + set_VQ_default_io();
2319 + Configure_Interface_IO();
2329 +#endif /* CONFIG_METROLOGIC_IO_INIT */
2331 +void stamp_led_set(int LED1, int LED2, int LED3)
2333 +#ifndef CONFIG_METROLOGIC_IO_INIT
2334 + *pFIO_INEN &= ~(PF2 | PF3 | PF4);
2335 + *pFIO_DIR |= (PF2 | PF3 | PF4);
2337 + if (LED1 == STATUS_LED_OFF)
2338 + *pFIO_FLAG_S = PF2;
2340 + *pFIO_FLAG_C = PF2;
2341 + if (LED2 == STATUS_LED_OFF)
2342 + *pFIO_FLAG_S = PF3;
2344 + *pFIO_FLAG_C = PF3;
2345 + if (LED3 == STATUS_LED_OFF)
2346 + *pFIO_FLAG_S = PF4;
2348 + *pFIO_FLAG_C = PF4;
2353 +void show_boot_progress(int status)
2357 + stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
2360 + stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
2363 + stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
2366 + stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
2370 + stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
2374 + stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
2383 + stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_OFF);
2386 + stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
2390 diff --git a/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.h b/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.h
2391 new file mode 100644
2392 index 0000000..96f7aa7
2394 +++ b/u-boot-1.1.6/board/VuQuest2D/VuQuest2D.h
2397 + * U-boot - stamp.h
2399 + * Copyright (c) 2005-2007 Analog Devices Inc.
2401 + * (C) Copyright 2000-2004
2402 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
2404 + * See file CREDITS for list of people who contributed to this
2407 + * This program is free software; you can redistribute it and/or
2408 + * modify it under the terms of the GNU General Public License as
2409 + * published by the Free Software Foundation; either version 2 of
2410 + * the License, or (at your option) any later version.
2412 + * This program is distributed in the hope that it will be useful,
2413 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2414 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2415 + * GNU General Public License for more details.
2417 + * You should have received a copy of the GNU General Public License
2418 + * along with this program; if not, write to the Free Software
2419 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
2420 + * MA 02110-1301 USA
2423 +#ifndef __VUQUEST2D_H__
2424 +#define __VUQUEST2D_H__
2426 +extern void init_Flags(void);
2428 +extern volatile unsigned long *ambctl0;
2429 +extern volatile unsigned long *ambctl1;
2430 +extern volatile unsigned long *amgctl;
2432 +/* Definitions used in Compact Flash Boot support */
2433 +#define FIO_EDGE_CF_BITS 0x0000
2434 +#define FIO_POLAR_CF_BITS 0x0000
2435 +#define FIO_EDGE_BITS 0x1E0
2436 +#define FIO_POLAR_BITS 0x160
2438 +/* Compact flash status bits in status register */
2439 +#define CF_STAT_BITS 0x00000060
2441 +/* CF Flags used to switch between expansion and external
2444 +#define CF_PF0 0x0001
2445 +#define CF_PF1 0x0002
2446 +#define CF_PF1_PF0 0x0003
2449 diff --git a/u-boot-1.1.6/board/VuQuest2D/config.mk b/u-boot-1.1.6/board/VuQuest2D/config.mk
2450 new file mode 100644
2451 index 0000000..2afee57
2453 +++ b/u-boot-1.1.6/board/VuQuest2D/config.mk
2456 +# Copyright (c) 2005-2008 Analog Device Inc.
2458 +# (C) Copyright 2001
2459 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
2461 +# Licensed under the GPL-2 or later.
2464 +# This is not actually used for Blackfin boards so do not change it
2465 +#TEXT_BASE = do-not-use-me
2467 +# Set some default LDR flags based on boot mode.
2468 +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
2469 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
2470 diff --git a/u-boot-1.1.6/board/VuQuest2D/spi.c b/u-boot-1.1.6/board/VuQuest2D/spi.c
2471 new file mode 100644
2472 index 0000000..908d4e1
2474 +++ b/u-boot-1.1.6/board/VuQuest2D/spi.c
2476 +/****************************************************************************
2477 + * SPI flash driver for M25P64
2478 + ****************************************************************************/
2479 +#include <common.h>
2480 +#include <linux/ctype.h>
2481 +#include <asm/mach-common/bits/spi.h>
2483 +#if defined(CONFIG_SPI)
2485 +//Application definitions
2487 +#define NUM_SECTORS 128 /* number of sectors */
2488 +#define SECTOR_SIZE 0x10000
2489 +#define NOP_NUM 1000
2491 +#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL) //Settings to the SPI_CTL
2492 +#define TIMOD01 (0x01) //stes the SPI to work with core instructions
2495 +#define SPI_WREN (0x06) //Set Write Enable Latch
2496 +#define SPI_WRDI (0x04) //Reset Write Enable Latch
2497 +#define SPI_RDSR (0x05) //Read Status Register
2498 +#define SPI_WRSR (0x01) //Write Status Register
2499 +#define SPI_READ (0x03) //Read data from memory
2500 +#define SPI_FAST_READ (0x0B) //Read data from memory
2501 +#define SPI_PP (0x02) //Program Data into memory
2502 +#define SPI_SE (0xD8) //Erase one sector in memory
2503 +#define SPI_BE (0xC7) //Erase all memory
2504 +#define WIP (0x1) //Check the write in progress bit of the SPI status register
2505 +#define WEL (0x2) //Check the write enable bit of the SPI status register
2507 +#define TIMEOUT 350000000
2518 +void spi_init_f (void);
2519 +void spi_init_r (void);
2520 +ssize_t spi_read (uchar *, int, uchar *, int);
2521 +ssize_t spi_write (uchar *, int, uchar *, int);
2523 +char ReadStatusRegister(void);
2524 +void Wait_For_SPIF(void);
2525 +void SetupSPI( const int spi_setting );
2526 +void SPI_OFF(void);
2527 +void SendSingleCommand( const int iCommand );
2529 +ERROR_CODE GetSectorNumber( unsigned long ulOffset, int *pnSector );
2530 +ERROR_CODE EraseBlock( int nBlock );
2531 +ERROR_CODE ReadData( unsigned long ulStart, long lCount,int *pnData );
2532 +ERROR_CODE WriteData( unsigned long ulStart, long lCount, int *pnData );
2533 +ERROR_CODE Wait_For_Status( char Statusbit );
2534 +ERROR_CODE Wait_For_WEL(void);
2536 +/* -------------------
2538 + * ------------------- */
2540 +/* **************************************************************************
2542 + * Function: spi_init_f
2544 + * Description: Init SPI-Controller (ROM part)
2548 + * *********************************************************************** */
2549 +void spi_init_f (void)
2553 +/* **************************************************************************
2555 + * Function: spi_init_r
2557 + * Description: Init SPI-Controller (RAM part) -
2558 + * The malloc engine is ready and we can move our buffers to
2563 + * *********************************************************************** */
2564 +void spi_init_r (void)
2569 +/****************************************************************************
2570 + * Function: spi_write
2571 + **************************************************************************** */
2572 +ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
2574 + unsigned long offset;
2575 + int start_block,end_block;
2576 + int start_byte,end_byte;
2577 + ERROR_CODE result = NO_ERR;
2578 + uchar temp[SECTOR_SIZE];
2581 + offset = addr[0]<<16 | addr[1] <<8 | addr[2];
2582 + /* Get the start block number */
2583 + GetSectorNumber(offset, &start_block);
2584 + /* Get the end block number */
2585 + GetSectorNumber(offset + len, &end_block);
2587 + for(num = start_block;num <= end_block;num ++){
2588 + ReadData(num*SECTOR_SIZE,SECTOR_SIZE,(int *)temp);
2589 + start_byte = num*SECTOR_SIZE;
2590 + end_byte = (num+1) * SECTOR_SIZE -1;
2591 + if(start_byte < offset) start_byte = offset;
2592 + if( end_byte > (offset+len)) end_byte = (offset+len-1);
2593 + for(i=start_byte;i<=end_byte;i++)
2594 + temp[i-num*SECTOR_SIZE] = buffer[i - offset];
2596 + result = WriteData(num*SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
2597 + if(result != NO_ERR)
2604 +/****************************************************************************
2605 + * Function: spi_read
2606 + **************************************************************************** */
2607 +ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
2609 + unsigned long offset;
2610 + offset = addr[0]<<16 | addr[1] <<8 | addr[2];
2611 + ReadData ( offset, len, (int *)buffer );
2615 +void SendSingleCommand( const int iCommand )
2617 + unsigned short dummy;
2619 + /*turns on the SPI in single write mode*/
2620 + SetupSPI( (COMMON_SPI_SETTINGS|TIMOD01) );
2622 + /*sends the actual command to the SPI TX register*/
2623 + *pSPI_TDBR = iCommand;
2624 + __builtin_bfin_ssync();
2626 + /*The SPI status register will be polled to check the SPIF bit*/
2629 + dummy = *pSPI_RDBR;
2631 + /*The SPI will be turned off*/
2636 +void SetupSPI( const int spi_setting )
2639 + if(icache_status()||dcache_status())
2640 + udelay(CONFIG_CCLK_HZ/50000000);
2641 + /*sets up the PF2 to be the slave select of the SPI */
2642 + *pSPI_FLG = 0xFB04;
2643 + *pSPI_BAUD = CONFIG_SPI_BAUD;
2644 + *pSPI_CTL = spi_setting;
2645 + __builtin_bfin_ssync();
2651 + *pSPI_CTL = 0x0400; /* disable SPI*/
2654 + __builtin_bfin_ssync();
2655 + udelay(CONFIG_CCLK_HZ/50000000);
2659 +void Wait_For_SPIF(void)
2661 + unsigned short dummyread;
2662 + while( (*pSPI_STAT&TXS));
2663 + while(!(*pSPI_STAT&SPIF));
2664 + while(!(*pSPI_STAT&RXS));
2665 + dummyread = *pSPI_RDBR; // Read dummy to empty the receive register
2669 +ERROR_CODE Wait_For_WEL(void)
2672 + char status_register = 0;
2673 + ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash*/
2675 + for(i = 0; i < TIMEOUT; i++)
2677 + status_register = ReadStatusRegister();
2678 + if( (status_register & WEL) )
2680 + ErrorCode = NO_ERR; /* tells us if there was an error erasing flash*/
2683 + ErrorCode = POLL_TIMEOUT; /* Time out error*/
2689 +ERROR_CODE Wait_For_Status( char Statusbit )
2692 + char status_register = 0xFF;
2693 + ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
2695 + for(i = 0; i < TIMEOUT; i++)
2697 + status_register = ReadStatusRegister();
2698 + if( !(status_register & Statusbit) )
2700 + ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
2703 + ErrorCode = POLL_TIMEOUT; /* Time out error */
2711 +char ReadStatusRegister(void)
2713 + char status_register = 0;
2715 + SetupSPI( (COMMON_SPI_SETTINGS|TIMOD01) ); /* Turn on the SPI */
2717 + *pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */
2718 + __builtin_bfin_ssync();
2719 + Wait_For_SPIF(); /*wait until the instruction has been sent*/
2720 + *pSPI_TDBR = 0; /*send dummy to receive the status register*/
2721 + __builtin_bfin_ssync();
2722 + Wait_For_SPIF(); /*wait until the data has been sent*/
2723 + status_register = *pSPI_RDBR; /*read the status register*/
2725 + SPI_OFF(); /* Turn off the SPI */
2727 + return status_register;
2730 +ERROR_CODE GetSectorNumber( unsigned long ulOffset, int *pnSector )
2733 + ERROR_CODE ErrorCode = NO_ERR;
2735 + if(ulOffset > (NUM_SECTORS*0x10000 -1)){
2736 + ErrorCode = INVALID_SECTOR;
2740 + nSector = (int)ulOffset/0x10000;
2741 + *pnSector = nSector;
2747 +ERROR_CODE EraseBlock( int nBlock )
2749 + unsigned long ulSectorOff = 0x0, ShiftValue;
2750 + ERROR_CODE ErrorCode = NO_ERR;
2753 + // if the block is invalid just return
2754 + if ( (nBlock < 0) || (nBlock > NUM_SECTORS) )
2756 + ErrorCode = INVALID_BLOCK; // tells us if there was an error erasing flash
2760 + // figure out the offset of the block in flash
2761 + if ( (nBlock >= 0) && (nBlock < NUM_SECTORS) )
2763 + ulSectorOff = (nBlock * SECTOR_SIZE);
2768 + ErrorCode = INVALID_BLOCK; // tells us if there was an error erasing flash
2772 + // A write enable instruction must previously have been executed
2773 + SendSingleCommand(SPI_WREN);
2775 + //The status register will be polled to check the write enable latch "WREN"
2776 + ErrorCode = Wait_For_WEL();
2778 + if( POLL_TIMEOUT == ErrorCode )
2780 + printf("SPI Erase block error\n");
2786 + //Turn on the SPI to send single commands
2787 + SetupSPI( (COMMON_SPI_SETTINGS|TIMOD01) );
2789 + // Send the erase block command to the flash followed by the 24 address
2790 + // to point to the start of a sector.
2791 + *pSPI_TDBR = SPI_SE;
2792 + __builtin_bfin_ssync();
2794 + ShiftValue = (ulSectorOff >> 16); // Send the highest byte of the 24 bit address at first
2795 + *pSPI_TDBR = ShiftValue;
2796 + __builtin_bfin_ssync();
2797 + Wait_For_SPIF(); // Wait until the instruction has been sent
2798 + ShiftValue = (ulSectorOff >> 8); // Send the middle byte of the 24 bit address at second
2799 + *pSPI_TDBR = ShiftValue;
2800 + __builtin_bfin_ssync();
2801 + Wait_For_SPIF(); // Wait until the instruction has been sent
2802 + *pSPI_TDBR = ulSectorOff; // Send the lowest byte of the 24 bit address finally
2803 + __builtin_bfin_ssync();
2804 + Wait_For_SPIF(); // Wait until the instruction has been sent
2806 + //Turns off the SPI
2809 + // Poll the status register to check the Write in Progress bit
2810 + // Sector erase takes time
2811 + ErrorCode = Wait_For_Status(WIP);
2813 + // block erase should be complete
2817 +/*****************************************************************************
2818 +* ERROR_CODE ReadData()
2820 +* Read a value from flash for verify purpose
2822 +* Inputs: unsigned long ulStart - holds the SPI start address
2823 +* int pnData - pointer to store value read from flash
2824 +* long lCount - number of elements to read
2825 +***************************************************************************** */
2826 +ERROR_CODE ReadData( unsigned long ulStart, long lCount,int *pnData )
2828 + unsigned long ShiftValue;
2829 + char *cnData,ReadValue;
2832 + cnData = (char *)pnData; /* Pointer cast to be able to increment byte wise */
2834 + // Start SPI interface
2835 + SetupSPI( (COMMON_SPI_SETTINGS|TIMOD01) );
2837 +#ifdef CONFIG_SERIAL_BF537_USE_FAST_READ
2838 + *pSPI_TDBR = SPI_FAST_READ; // Send the read command to SPI device
2840 + *pSPI_TDBR = SPI_READ; // Send the read command to SPI device
2842 + __builtin_bfin_ssync();
2843 + Wait_For_SPIF(); // Wait until the instruction has been sent
2844 + ShiftValue = (ulStart >> 16); // Send the highest byte of the 24 bit address at first
2845 + *pSPI_TDBR = ShiftValue; // Send the byte to the SPI device
2846 + __builtin_bfin_ssync();
2847 + Wait_For_SPIF(); // Wait until the instruction has been sent
2848 + ShiftValue = (ulStart >> 8); // Send the middle byte of the 24 bit address at second
2849 + *pSPI_TDBR = ShiftValue; // Send the byte to the SPI device
2850 + __builtin_bfin_ssync();
2851 + Wait_For_SPIF(); // Wait until the instruction has been sent
2852 + *pSPI_TDBR = ulStart; // Send the lowest byte of the 24 bit address finally
2853 + __builtin_bfin_ssync();
2854 + Wait_For_SPIF(); // Wait until the instruction has been sent
2856 +#ifdef CONFIG_SERIAL_BF537_USE_FAST_READ
2857 + *pSPI_TDBR = 0; // Send dummy for FAST_READ
2858 + __builtin_bfin_ssync();
2859 + Wait_For_SPIF(); // Wait until the instruction has been sent
2862 + // After the SPI device address has been placed on the MOSI pin the data can be
2863 + // received on the MISO pin.
2864 + for (i=0; i<lCount; i++)
2866 + *pSPI_TDBR = 0; //send dummy
2867 + __builtin_bfin_ssync();
2868 + while(!(*pSPI_STAT&RXS));
2869 + *cnData++ = *pSPI_RDBR; //read
2871 + if((i>=SECTOR_SIZE)&&(i%SECTOR_SIZE == 0))
2875 + SPI_OFF(); // Turn off the SPI
2880 +ERROR_CODE WriteFlash ( unsigned long ulStartAddr, long lTransferCount, int *iDataSource, long *lWriteCount )
2883 + unsigned long ulWAddr;
2884 + long lWTransferCount = 0;
2887 + char *temp = (char *)iDataSource;
2888 + ERROR_CODE ErrorCode = NO_ERR; // tells us if there was an error erasing flash
2890 + // First, a Write Enable Command must be sent to the SPI.
2891 + SendSingleCommand(SPI_WREN);
2893 + // Second, the SPI Status Register will be tested whether the
2894 + // Write Enable Bit has been set.
2895 + ErrorCode = Wait_For_WEL();
2896 + if( POLL_TIMEOUT == ErrorCode )
2898 + printf("SPI Write Time Out\n");
2902 + // Third, the 24 bit address will be shifted out the SPI MOSI bytewise.
2903 + SetupSPI( (COMMON_SPI_SETTINGS|TIMOD01) ); // Turns the SPI on
2904 + *pSPI_TDBR = SPI_PP;
2905 + __builtin_bfin_ssync();
2906 + Wait_For_SPIF(); //wait until the instruction has been sent
2907 + ulWAddr = (ulStartAddr >> 16);
2908 + *pSPI_TDBR = ulWAddr;
2909 + __builtin_bfin_ssync();
2910 + Wait_For_SPIF(); //wait until the instruction has been sent
2911 + ulWAddr = (ulStartAddr >> 8);
2912 + *pSPI_TDBR = ulWAddr;
2913 + __builtin_bfin_ssync();
2914 + Wait_For_SPIF(); //wait until the instruction has been sent
2915 + ulWAddr = ulStartAddr;
2916 + *pSPI_TDBR = ulWAddr;
2917 + __builtin_bfin_ssync();
2918 + Wait_For_SPIF(); //wait until the instruction has been sent
2919 + // Fourth, maximum number of 256 bytes will be taken from the Buffer
2920 + // and sent to the SPI device.
2921 + for (i=0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++)
2924 + *pSPI_TDBR = iData;
2925 + __builtin_bfin_ssync();
2926 + Wait_For_SPIF(); //wait until the instruction has been sent
2930 + SPI_OFF(); // Turns the SPI off
2932 + // Sixth, the SPI Write in Progress Bit must be toggled to ensure the
2933 + // programming is done before start of next transfer.
2934 + ErrorCode = Wait_For_Status(WIP);
2936 + if( POLL_TIMEOUT == ErrorCode )
2938 + printf("SPI Program Time out!\n");
2943 + *lWriteCount = lWTransferCount;
2949 +ERROR_CODE WriteData( unsigned long ulStart, long lCount, int *pnData )
2952 + unsigned long ulWStart = ulStart;
2953 + long lWCount = lCount, lWriteCount;
2954 + long *pnWriteCount = &lWriteCount;
2956 + ERROR_CODE ErrorCode = NO_ERR;
2958 + while (lWCount != 0)
2960 + ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
2962 + // After each function call of WriteFlash the counter must be adjusted
2963 + lWCount -= *pnWriteCount;
2965 + // Also, both address pointers must be recalculated.
2966 + ulWStart += *pnWriteCount;
2967 + pnData += *pnWriteCount/4;
2970 + // return the appropriate error code
2975 + * Spit out some useful information about the SPI eeprom
2977 +int eeprom_info(void)
2987 + if (spi_detect_part())
2990 + printf("SPI Device: %s 0x%02X (%s) 0x%02X 0x%02X\n"
2991 + "Parameters: num sectors = %i, sector size = %i, write size = %i\n"
2992 + "Flash Size: %i mbit (%i mbyte)\n"
2993 + "Status: 0x%02X\n",
2994 + flash.flash->name, flash.manufacturer_id, flash.manufacturer->name,
2995 + flash.device_id1, flash.device_id2, flash.num_sectors,
2996 + flash.sector_size, flash.write_length,
2997 + (flash.num_sectors * flash.sector_size) >> 17,
2998 + (flash.num_sectors * flash.sector_size) >> 20,
2999 + read_status_register());
3008 +#endif /* CONFIG_SPI */
3009 diff --git a/u-boot-1.1.6/board/VuQuest2D/spi_flash.c b/u-boot-1.1.6/board/VuQuest2D/spi_flash.c
3010 new file mode 100644
3011 index 0000000..8784741
3013 +++ b/u-boot-1.1.6/board/VuQuest2D/spi_flash.c
3015 +/* Share the spi flash code */
3016 +#include "../bf537-stamp/spi_flash.c"
3017 diff --git a/u-boot-1.1.6/board/VuQuest2D/u-boot.lds.S b/u-boot-1.1.6/board/VuQuest2D/u-boot.lds.S
3018 new file mode 100644
3019 index 0000000..01780c5
3021 +++ b/u-boot-1.1.6/board/VuQuest2D/u-boot.lds.S
3024 + * U-boot - u-boot.lds.S
3026 + * Copyright (c) 2005-2008 Analog Device Inc.
3028 + * (C) Copyright 2000-2004
3029 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
3031 + * See file CREDITS for list of people who contributed to this
3034 + * This program is free software; you can redistribute it and/or
3035 + * modify it under the terms of the GNU General Public License as
3036 + * published by the Free Software Foundation; either version 2 of
3037 + * the License, or (at your option) any later version.
3039 + * This program is distributed in the hope that it will be useful,
3040 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3041 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3042 + * GNU General Public License for more details.
3044 + * You should have received a copy of the GNU General Public License
3045 + * along with this program; if not, write to the Free Software
3046 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3047 + * MA 02111-1307 USA
3050 +#include <config.h>
3051 +#include <asm/blackfin.h>
3054 +/* If we don't actually load anything into L1 data, this will avoid
3055 + * a syntax error. If we do actually load something into L1 data,
3056 + * we'll get a linker memory load error (which is what we'd want).
3057 + * This is here in the first place so we can quickly test building
3058 + * for different CPU's which may lack non-cache L1 data.
3060 +#ifndef L1_DATA_B_SRAM
3061 +# define L1_DATA_B_SRAM CFG_MONITOR_BASE
3062 +# define L1_DATA_B_SRAM_SIZE 0
3067 +/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
3070 + ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
3071 + l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
3072 + l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
3079 +#ifdef ENV_IS_EMBEDDED
3080 + /* WARNING - the following is hand-optimized to fit within
3081 + * the sector before the environment sector. If it throws
3082 + * an error during compilation remove an object here to get
3083 + * it linked after the configuration sector.
3086 + cpu/blackfin/start.o (.text)
3087 + cpu/blackfin/traps.o (.text)
3088 + cpu/blackfin/interrupt.o (.text)
3089 + cpu/blackfin/serial.o (.text)
3090 + common/dlmalloc.o (.text)
3091 + lib_generic/crc32.o (.text)
3093 + . = DEFINED(env_offset) ? env_offset : .;
3094 + common/environment.o (.text)
3103 + *(.rodata .rodata.*)
3122 + ___u_boot_cmd_start = .;
3124 + ___u_boot_cmd_end = .;
3135 + __stext_l1_lma = LOADADDR(.text_l1);
3146 + __sdata_l1_lma = LOADADDR(.data_l1);
3152 + *(.sbss) *(.scommon)
3159 diff --git a/u-boot-1.1.6/board/VuQuest2D/video.c b/u-boot-1.1.6/board/VuQuest2D/video.c
3160 new file mode 100644
3161 index 0000000..2d6f7a4
3163 +++ b/u-boot-1.1.6/board/VuQuest2D/video.c
3166 + * (C) Copyright 2000
3167 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
3168 + * (C) Copyright 2002
3169 + * Wolfgang Denk, wd@denx.de
3170 + * (C) Copyright 2006
3171 + * Aubrey Li, aubrey.li@analog.com
3173 + * See file CREDITS for list of people who contributed to this
3176 + * This program is free software; you can redistribute it and/or
3177 + * modify it under the terms of the GNU General Public License as
3178 + * published by the Free Software Foundation; either version 2 of
3179 + * the License, or (at your option) any later version.
3181 + * This program is distributed in the hope that it will be useful,
3182 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3183 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3184 + * GNU General Public License for more details.
3186 + * You should have received a copy of the GNU General Public License
3187 + * along with this program; if not, write to the Free Software
3188 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3189 + * MA 02111-1307 USA
3192 +#include <stdarg.h>
3193 +#include <common.h>
3194 +#include <config.h>
3195 +#include <malloc.h>
3196 +#include <asm/blackfin.h>
3197 +#include <asm/mach-common/bits/dma.h>
3199 +#include <linux/types.h>
3200 +#include <devices.h>
3202 +int gunzip(void *, int, unsigned char *, unsigned long *);
3204 +#ifdef CONFIG_VIDEO
3206 +#define DMA_SIZE16 2
3208 +#include <asm/mach-common/bits/ppi.h>
3210 +#define NTSC_FRAME_ADDR 0x06000000
3213 +/* NTSC OUTPUT SIZE 720 * 240 */
3215 +#define HORIZONTAL 4
3217 +int is_vblank_line(const int line)
3220 + * This array contains a single bit for each line in
3223 + if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
3229 +int NTSC_framebuffer_init(char *base_address)
3231 + const int NTSC_frames = 1;
3232 + const int NTSC_lines = 525;
3233 + char *dest = base_address;
3234 + int frame_num, line_num;
3236 + for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
3237 + for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
3238 + unsigned int code;
3242 + if (is_vblank_line(line_num))
3245 + if (line_num > 266 || line_num < 3)
3248 + /* Output EAV code */
3249 + code = SystemCodeMap[offset].EAV;
3250 + write_dest_byte((char)(code >> 24) & 0xff);
3251 + write_dest_byte((char)(code >> 16) & 0xff);
3252 + write_dest_byte((char)(code >> 8) & 0xff);
3253 + write_dest_byte((char)(code) & 0xff);
3255 + /* Output horizontal blanking */
3256 + for (i = 0; i < 67 * 2; ++i) {
3257 + write_dest_byte(0x80);
3258 + write_dest_byte(0x10);
3262 + code = SystemCodeMap[offset].SAV;
3263 + write_dest_byte((char)(code >> 24) & 0xff);
3264 + write_dest_byte((char)(code >> 16) & 0xff);
3265 + write_dest_byte((char)(code >> 8) & 0xff);
3266 + write_dest_byte((char)(code) & 0xff);
3268 + /* Output empty horizontal data */
3269 + for (i = 0; i < 360 * 2; ++i) {
3270 + write_dest_byte(0x80);
3271 + write_dest_byte(0x10);
3276 + return dest - base_address;
3279 +void fill_frame(char *Frame, int Value)
3289 + /* fill odd and even frames */
3290 + for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
3291 + OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
3292 + EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
3293 + for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
3294 + *OddPtr32 = Value;
3295 + *EvenPtr32 = Value;
3299 + for (m = 0; m < VERTICAL; m++) {
3300 + data = (int *)u_boot_logo.data;
3301 + for (OddLine = (22 + m), EvenLine = (285 + m);
3302 + OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
3303 + OddLine += VERTICAL, EvenLine += VERTICAL) {
3304 + OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
3306 + (int *)((Frame + ((EvenLine) * 1716)) + 276);
3307 + for (i = 0; i < u_boot_logo.width / 2; i++) {
3308 + /* enlarge one pixel to m x n */
3309 + for (n = 0; n < HORIZONTAL; n++) {
3310 + *OddPtr32++ = *data;
3311 + *EvenPtr32++ = *data;
3319 +static void video_init(char *NTSCFrame)
3321 + NTSCFrame = (char *)NTSC_FRAME_ADDR;
3322 + NTSC_framebuffer_init(NTSCFrame);
3323 + fill_frame(NTSCFrame, BLUE);
3325 + bfin_write_PPI_CONTROL(0x0082);
3326 + bfin_write_PPI_FRAME(0x020D);
3328 + bfin_write_DMA0_START_ADDR(NTSCFrame);
3329 + bfin_write_DMA0_X_COUNT(0x035A);
3330 + bfin_write_DMA0_X_MODIFY(0x0002);
3331 + bfin_write_DMA0_Y_COUNT(0x020D);
3332 + bfin_write_DMA0_Y_MODIFY(0x0002);
3333 + bfin_write_DMA0_CONFIG(0x1015);
3334 + bfin_write_PPI_CONTROL(0x0083);
3337 +int drv_video_init(void)
3339 + device_t videodev;
3341 + video_init((void *)NTSC_FRAME_ADDR);
3343 + memset(&videodev, 0, sizeof(videodev));
3344 + strcpy(videodev.name, "video");
3345 + videodev.ext = DEV_EXT_VIDEO;
3346 + videodev.flags = DEV_FLAGS_SYSTEM;
3348 + return device_register(&videodev);
3352 diff --git a/u-boot-1.1.6/board/VuQuest2D/video.h b/u-boot-1.1.6/board/VuQuest2D/video.h
3353 new file mode 100644
3354 index 0000000..d5a8bc8
3356 +++ b/u-boot-1.1.6/board/VuQuest2D/video.h
3358 +#include <video_logo.h>
3359 +#define write_dest_byte(val) {*dest++=val;}
3360 +#define BLACK (0x01800180) /* black pixel pattern */
3361 +#define BLUE (0x296E29F0) /* blue pixel pattern */
3362 +#define RED (0x51F0515A) /* red pixel pattern */
3363 +#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */
3364 +#define GREEN (0x91229136) /* green pixel pattern */
3365 +#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
3366 +#define YELLOW (0xD292D210) /* yellow pixel pattern */
3367 +#define WHITE (0xFE80FE80) /* white pixel pattern */
3377 +const SystemCodeType SystemCodeMap[4] = {
3378 + {0xFF000080, 0xFF00009D},
3379 + {0xFF0000AB, 0xFF0000B6},
3380 + {0xFF0000C7, 0xFF0000DA},
3381 + {0xFF0000EC, 0xFF0000F1}
3383 diff --git a/u-boot-1.1.6/common/Makefile b/u-boot-1.1.6/common/Makefile
3384 index f848123..c9cdabd 100644
3385 --- a/u-boot-1.1.6/common/Makefile
3386 +++ b/u-boot-1.1.6/common/Makefile
3387 @@ -51,7 +51,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \
3388 memsize.o miiphybb.o miiphyutil.o \
3389 s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
3390 usb.o usb_kbd.o usb_storage.o \
3391 - virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o
3392 + virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o interface_select.o metro_pf.o
3394 SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
3395 OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
3396 diff --git a/u-boot-1.1.6/common/cmd_bdinfo.c b/u-boot-1.1.6/common/cmd_bdinfo.c
3397 index bba7b75..3b1fcfc 100644
3398 --- a/u-boot-1.1.6/common/cmd_bdinfo.c
3399 +++ b/u-boot-1.1.6/common/cmd_bdinfo.c
3400 @@ -91,36 +91,38 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3401 print_str ("pevfreq", strmhz(buf, bd->bi_pevfreq));
3404 +#if (CONFIG_COMMANDS & CFG_CMD_NET)
3406 for (i=0; i<6; ++i) {
3407 printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
3410 -#if defined(CONFIG_HAS_ETH1)
3411 + #if defined(CONFIG_HAS_ETH1)
3412 puts ("\neth1addr =");
3413 for (i=0; i<6; ++i) {
3414 printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
3419 -#if defined(CONFIG_HAS_ETH2)
3420 + #if defined(CONFIG_HAS_ETH2)
3421 puts ("\neth2addr =");
3422 for (i=0; i<6; ++i) {
3423 printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
3428 -#if defined(CONFIG_HAS_ETH3)
3429 + #if defined(CONFIG_HAS_ETH3)
3430 puts ("\neth3addr =");
3431 for (i=0; i<6; ++i) {
3432 printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]);
3437 -#ifdef CONFIG_HERMES
3438 + #ifdef CONFIG_HERMES
3439 print_str ("ethspeed", strmhz(buf, bd->bi_ethspeed));
3442 puts ("\nIP addr = "); print_IPaddr (bd->bi_ip_addr);
3443 +#endif /* (CONFIG_COMMANDS & CFG_CMD_NET) */
3444 printf ("\nbaudrate = %6ld bps\n", bd->bi_baudrate );
3447 @@ -138,12 +140,13 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3448 print_num ("flashsize", (ulong)bd->bi_flashsize);
3449 print_num ("flashoffset", (ulong)bd->bi_flashoffset);
3451 +#if (CONFIG_COMMANDS & CFG_CMD_NET)
3453 for (i=0; i<6; ++i) {
3454 printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
3456 - puts ("\nip_addr = ");
3457 - print_IPaddr (bd->bi_ip_addr);
3458 + puts ("\nip_addr = "); print_IPaddr (bd->bi_ip_addr);
3460 printf ("\nbaudrate = %ld bps\n", bd->bi_baudrate);
3463 @@ -167,13 +170,12 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3464 print_num ("sram size", (ulong)bd->bi_sramsize);
3467 -#if defined(CFG_CMD_NET)
3468 +#if (CONFIG_COMMANDS & CFG_CMD_NET)
3470 for (i=0; i<6; ++i) {
3471 printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
3473 - puts ("\nip_addr = ");
3474 - print_IPaddr (bd->bi_ip_addr);
3475 + puts ("\nip_addr = "); print_IPaddr (bd->bi_ip_addr);
3478 printf ("\nbaudrate = %ld bps\n", bd->bi_baudrate);
3479 @@ -202,11 +204,12 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3480 print_num("flashsize", (ulong)bd->bi_flashsize);
3481 print_num("flashoffset", (ulong)bd->bi_flashoffset);
3483 +#if (CONFIG_COMMANDS & CFG_CMD_NET)
3485 for (i = 0; i < 6; ++i)
3486 printf("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
3487 - puts("\nip_addr = ");
3488 - print_IPaddr(bd->bi_ip_addr);
3489 + puts("\nip_addr = "); print_IPaddr(bd->bi_ip_addr);
3491 printf("\nbaudrate = %d bps\n", bd->bi_baudrate);
3494 @@ -226,12 +229,13 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3495 print_num ("flashsize", (ulong)bd->bi_flashsize);
3496 print_num ("flashoffset", (ulong)bd->bi_flashoffset);
3498 +#if (CONFIG_COMMANDS & CFG_CMD_NET)
3500 for (i=0; i<6; ++i) {
3501 printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
3503 - puts ("\nip_addr = ");
3504 - print_IPaddr (bd->bi_ip_addr);
3505 + puts ("\nip_addr = "); print_IPaddr (bd->bi_ip_addr);
3507 printf ("\nbaudrate = %d bps\n", bd->bi_baudrate);
3510 @@ -255,6 +259,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3511 print_num("-> size", bd->bi_dram[i].size);
3514 +#if (CONFIG_COMMANDS & CFG_CMD_NET)
3516 for (i=0; i<6; ++i) {
3517 printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
3518 @@ -262,6 +267,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3521 print_IPaddr (bd->bi_ip_addr);
3524 "baudrate = %d bps\n", bd->bi_baudrate);
3526 diff --git a/u-boot-1.1.6/common/cmd_bootm.c b/u-boot-1.1.6/common/cmd_bootm.c
3527 index e6fe472..8711ff4 100644
3528 --- a/u-boot-1.1.6/common/cmd_bootm.c
3529 +++ b/u-boot-1.1.6/common/cmd_bootm.c
3530 @@ -150,6 +150,13 @@ image_header_t header;
3532 ulong load_addr = CFG_LOAD_ADDR; /* Default Load Address */
3534 +#if defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
3536 +extern int Get_Interface_AtoD_Value(void);
3537 +extern void Send_Interface_AtoD_to_kernel(void);
3541 int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3544 @@ -415,6 +422,12 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3545 #ifdef CONFIG_SILENT_CONSOLE
3546 fixup_silent_linux();
3548 +#if defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
3549 + if (Get_Interface_AtoD_Value() >= 0)
3551 + Send_Interface_AtoD_to_kernel();
3554 do_bootm_linux (cmdtp, flag, argc, argv,
3555 addr, len_ptr, verify);
3557 diff --git a/u-boot-1.1.6/common/cmd_eeprom.c b/u-boot-1.1.6/common/cmd_eeprom.c
3558 index cb7963f..84d65aa 100644
3559 --- a/u-boot-1.1.6/common/cmd_eeprom.c
3560 +++ b/u-boot-1.1.6/common/cmd_eeprom.c
3562 #include <command.h>
3565 +#define DEBUG_BOOT_PERFORMANCE 1
3567 +#if (DEBUG_BOOT_PERFORMANCE)
3568 +#include <Metrologic_Hardware.h>
3569 +#include <metro_pf.h>
3573 #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) || defined(CFG_ENV_IS_IN_EEPROM)
3575 extern void eeprom_init (void);
3576 @@ -139,6 +147,10 @@ int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt
3581 +#if (DEBUG_BOOT_PERFORMANCE) && defined(__ADSPBF531__)
3582 + *pFIO_FLAG_D |= (PF4); /* Assert Aiming_On */
3584 /* Read data until done or would cross a page boundary.
3585 * We must write the address again when changing pages
3586 * because the next page may be in a different device.
3587 diff --git a/u-boot-1.1.6/common/cmd_load.c b/u-boot-1.1.6/common/cmd_load.c
3588 index f63b8e8..0c64bc9 100644
3589 --- a/u-boot-1.1.6/common/cmd_load.c
3590 +++ b/u-boot-1.1.6/common/cmd_load.c
3592 * Serial up- and download support
3595 +#include <watchdog.h>
3596 #include <command.h>
3597 #include <s_record.h>
3599 #include <exports.h>
3600 #include <xyzModem.h>
3601 +#include <asm/mach-common/bits/bootrom.h>
3602 +#include <Metrologic_Hardware.h>
3604 DECLARE_GLOBAL_DATA_PTR;
3606 @@ -84,9 +87,11 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3607 if (load_baudrate != current_baudrate) {
3608 printf ("## Switch baudrate to %d bps and press ENTER ...\n",
3610 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3612 gd->baudrate = load_baudrate;
3614 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3618 @@ -127,9 +132,11 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3619 if (load_baudrate != current_baudrate) {
3620 printf ("## Switch baudrate to %d bps and press ESC ...\n",
3622 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3624 gd->baudrate = current_baudrate;
3626 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3629 if (getc() == 0x1B) /* ESC */
3630 @@ -282,9 +289,11 @@ int do_save_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3631 if (save_baudrate != current_baudrate) {
3632 printf ("## Switch baudrate to %d bps and press ENTER ...\n",
3634 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3636 gd->baudrate = save_baudrate;
3638 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3642 @@ -311,9 +320,11 @@ int do_save_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3643 if (save_baudrate != current_baudrate) {
3644 printf ("## Switch baudrate to %d bps and press ESC ...\n",
3645 (int)current_baudrate);
3646 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3648 gd->baudrate = current_baudrate;
3650 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3653 if (getc() == 0x1B) /* ESC */
3654 @@ -466,9 +477,11 @@ int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3655 if (load_baudrate != current_baudrate) {
3656 printf ("## Switch baudrate to %d bps and press ENTER ...\n",
3658 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3660 gd->baudrate = load_baudrate;
3662 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3666 @@ -504,9 +517,11 @@ int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3667 if (load_baudrate != current_baudrate) {
3668 printf ("## Switch baudrate to %d bps and press ESC ...\n",
3670 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3672 gd->baudrate = current_baudrate;
3674 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
3677 if (getc() == 0x1B) /* ESC */
3678 @@ -1036,6 +1051,406 @@ static ulong load_serial_ymodem (ulong offset)
3682 +/**********************************************************************
3683 + *************** Added by Metrologic *********************************
3684 + **********************************************************************/
3686 +extern flash_info_t flash_info[]; /* info for FLASH chips */
3688 +int do_flash (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3690 +#ifdef CFG_NO_FLASH
3695 + ulong addr = load_addr;
3703 + goto __DO_FLASH_ERROR;
3706 + if ((s = getenv("filesize")) != NULL)
3708 + count = simple_strtoul(s, NULL, 16);
3712 + puts ("Unknown filesize! Download file first!\n");
3716 + if (strcmp(argv[1] ,"u-boot") == 0)
3719 + flash_info_t *info;
3720 + int protect_on = 0;
3724 + puts ("Unprotecting flash sectors... ");
3726 + for (bank=1; bank<=CFG_MAX_FLASH_BANKS; ++bank) {
3727 + info = &flash_info[bank-1];
3728 + if (info->flash_id == FLASH_UNKNOWN) {
3731 + printf ("%sProtect Flash Bank # %ld\n",
3732 + p ? "" : "Un-", bank);
3734 + for (i=0; i<info->sector_count; ++i) {
3735 +#if defined(CFG_FLASH_PROTECTION)
3736 + if (flash_real_protect(info, i, p))
3740 + info->protect[i] = p;
3741 +#endif /* CFG_FLASH_PROTECTION */
3747 + addr_first = (ulong)U_BOOT_START_ADDR;
3748 + addr_last = (ulong)CONFIG_START_ADDR - 1;
3750 + dest = U_BOOT_START_ADDR;
3753 + else if (strcmp(argv[1] ,"kernel") == 0)
3755 + addr_first = (ulong)KERNEL_START_ADDR;
3756 + addr_last = (ulong)FILSYS_START_ADDR - 1;
3758 + dest = KERNEL_START_ADDR;
3761 + else if (strcmp(argv[1] ,"filesystem") == 0)
3763 +#ifndef CFG_FLASH_SIZE
3764 + puts ("CFG_FLASH_SIZE must be defined to use this feature!\n");
3768 + addr_first = (ulong)FILSYS_START_ADDR;
3769 + addr_last = (ulong)FLASH_PARTITION_START + (ulong)CFG_FLASH_SIZE - 1;
3771 + dest = FILSYS_START_ADDR;
3777 + if (addr_last <= addr_first)
3779 + puts("Invalid CFG_FLASH_SIZE\n");
3783 + printf ("Erasing %s\n", argv[1]);
3785 + if (flash_sect_erase(addr_first, addr_last))
3787 + printf ("Error erasing region %d - %d\n", addr_first, addr_last);
3792 + printf ("Copy %s to Flash... ", argv[1]);
3794 + rc = flash_write ((uchar *)addr, dest, count);
3796 + flash_perror (rc);
3805 + printf ("Usage:\n%s\n", cmdtp->usage);
3810 +int do_eflash ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
3812 + const char *const fmt =
3813 + "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
3815 + ulong dev_addr = CFG_DEF_EEPROM_ADDR;
3816 + ulong addr = load_addr;
3824 + goto __DO_EFLASH_ERROR;
3827 + if ((s = getenv("filesize")) != NULL)
3829 + cnt = simple_strtoul(s, NULL, 16);
3833 + puts ("Unknown filesize! Download file first!\n");
3837 + if (strcmp(argv[1] ,"u-boot") == 0)
3839 + off = U_BOOT_START_OFFS;
3842 + else if (strcmp(argv[1] ,"kernel") == 0)
3844 + off = KERNEL_START_OFFS;
3847 + else if (strcmp(argv[1] ,"filesystem") == 0)
3849 + ulong addr_pad = load_addr - PADDING_BUFF_SIZE;
3850 + ulong bytes_to_erase = (ulong)CFG_FLASH_SIZE - 1 - FILSYS_START_OFFS;
3851 + ulong start_offset = FILSYS_START_OFFS;
3854 + if (load_addr < PADDING_BUFF_SIZE)
3856 + printf ("load_addr too small, need %d bytes room to erase filesystem\n", PADDING_BUFF_SIZE);
3860 + for (i = 0; i < PADDING_BUFF_SIZE; i++)
3862 + *((u_char *)addr_pad) = (u_char)PADDING_CHAR;
3866 + addr_pad = load_addr - PADDING_BUFF_SIZE;
3870 + for (i = 0; i < 12; i++)
3872 + *((u_char *)addr_pad) = *((u_char*)addr);
3879 + addr_pad = load_addr - PADDING_BUFF_SIZE;
3881 + puts ("Formatting file system partition... ");
3883 + while (bytes_to_erase > 0)
3887 + if ( bytes_to_erase > PADDING_BUFF_SIZE )
3889 + count = PADDING_BUFF_SIZE;
3893 + for (i = 0; i < 12; i++)
3895 + *((u_char *)addr_pad) = (u_char)PADDING_CHAR;
3898 + addr_pad = load_addr - PADDING_BUFF_SIZE;
3899 + count = bytes_to_erase;
3902 + if (eeprom_write (dev_addr, start_offset, (uchar *) addr_pad, count))
3904 + printf("Error erasing %d to %d\n", start_offset, start_offset + count);
3911 + start_offset += count;
3912 + bytes_to_erase -= count;
3916 + off = FILSYS_START_OFFS;
3922 + printf (fmt, dev_addr, "write", addr, off, cnt);
3923 + rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);
3930 + printf ("Usage:\n%s\n", cmdtp->usage);
3936 +int print_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
3938 + uint regval1, regval2, regval3, regval4;
3940 +#if (defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534) || \
3941 + defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) )
3943 + regval1 = *pPORTF_FER;
3944 + regval2 = *pPORTFIO_DIR;
3945 + regval3 = *pPORTFIO_INEN;
3946 + regval4 = *pPORTFIO;
3948 + printf ("PortF, FER 0x%04x, DIR 0x%04x, INEN 0x%04x, DATA 0x%04x\r\n",
3949 + regval1, regval2, regval3, regval4);
3951 + regval1 = *pPORTG_FER;
3952 + regval2 = *pPORTGIO_DIR;
3953 + regval3 = *pPORTGIO_INEN;
3954 + regval4 = *pPORTGIO;
3956 + printf ("PortG, FER 0x%04x, DIR 0x%04x, INEN 0x%04x, DATA 0x%04x\r\n",
3957 + regval1, regval2, regval3, regval4);
3959 + regval1 = *pPORTH_FER;
3960 + regval2 = *pPORTHIO_DIR;
3961 + regval3 = *pPORTHIO_INEN;
3962 + regval4 = *pPORTHIO;
3964 + printf ("PortH, FER 0x%04x, DIR 0x%04x, INEN 0x%04x, DATA 0x%04x\r\n",
3965 + regval1, regval2, regval3, regval4);
3967 +#elif (defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
3968 + defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) )
3970 + regval1 = *pFIO_DIR;
3971 + regval2 = *pFIO_EDGE;
3972 + regval3 = *pFIO_INEN;
3973 + regval4 = *pFIO_FLAG_D;
3976 + uint regval5 = *pFIO_POLAR;
3978 + printf ("PortF, DIR 0x%04x, EDGE 0x%04x, INEN 0x%04x, DATA 0x%04x, POLAR 0x%04x\r\n",
3979 + regval1, regval2, regval3, regval4, regval5);
3982 +#error "Unknown Blackfin platform..."
3985 + regval1 = *pVR_CTL;
3986 + printf("VR_CTL = 0x%04x\r\n", regval1);
3991 +extern void Configure_Interface_IO(void);
3992 +extern void DisplayInterfaceBoard(void);
3994 +#if defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
3996 +extern int Get_Interface_AtoD_Value(void);
3997 +extern void Send_Interface_AtoD_to_kernel(void);
3998 +int program_vrctl(int millivolt);
4002 +int interfaceboard_init (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
4004 + Configure_Interface_IO();
4005 + DisplayInterfaceBoard();
4006 +#if defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
4007 + if (Get_Interface_AtoD_Value() >= 0)
4009 + Send_Interface_AtoD_to_kernel();
4015 +int prog_vrctl (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
4017 + unsigned long voltage;
4021 + goto __PROG_VRCTL_ERROR;
4024 + voltage = simple_strtoul(argv[1], NULL, 10);
4026 + if (voltage < 850 || voltage > 1300)
4028 + goto __PROG_VRCTL_ERROR;
4033 + goto __PROG_VRCTL_ERROR;
4036 + program_vrctl(voltage);
4040 +__PROG_VRCTL_ERROR:
4041 + printf ("Usage:\n%s\n", cmdtp->usage);
4045 +int program_vrctl(int millivolt)
4048 + uint mask = 0xFF0F;
4050 +#if defined(CONFIG_DISABLE_CLKIN_OUTPUT)
4051 +#if (CONFIG_DISABLE_CLKIN_OUTPUT)
4058 + vlev = 6 + (millivolt - 850) / 50;
4060 + disable_interrupts();
4062 + if (millivolt < 850 || millivolt > 1300)
4063 + { /* Preserve the voltage setting but update the clkin-output */
4064 + *pVR_CTL = *pVR_CTL & (mask | 0x00f0);
4068 + *pVR_CTL = (*pVR_CTL & mask) | (vlev << 4);
4073 + enable_interrupts();
4078 +/**********************************************************************
4079 + *************** Metrologic *********************************
4080 + **********************************************************************/
4082 #endif /* CFG_CMD_LOADB */
4084 /* -------------------------------------------------------------------- */
4085 @@ -1103,6 +1518,47 @@ U_BOOT_CMD(
4086 " with offset 'off' and baudrate 'baud'\n"
4090 +/**********************************************************************
4091 + *************** Added by Metrologic *********************************
4092 + **********************************************************************/
4095 + flash, 2, 0, do_flash,
4096 + "flash - save binary file to parallel flash\n",
4097 + "[ u-boot | kernel | filesystem ]\n"
4098 + " - save binary file to parallel flash\n"
4102 + eflash, 2, 0, do_eflash,
4103 + "eflash - save binary file to EEPROM\n",
4104 + "[ u-boot | kernel | filesystem ]\n"
4105 + " - save binary file to EEPROM\n"
4109 + status, 2, 0, print_status,
4110 + "status - Prints the status of different registers\n",
4115 + ibinit, 2, 0, interfaceboard_init,
4116 + "ibinit - Detect Interface Board and initialize IO \n",
4121 + vrctl, 2, 0, prog_vrctl,
4122 + "vrctl - Programs new voltage (mV) to Bfin Core [850 .. 1300]\n",
4126 +/**********************************************************************
4127 + *************** Metrologic *********************************
4128 + **********************************************************************/
4130 #endif /* CFG_CMD_LOADB */
4132 /* -------------------------------------------------------------------- */
4133 diff --git a/u-boot-1.1.6/common/cmd_mem.c b/u-boot-1.1.6/common/cmd_mem.c
4134 index 3f1023c..154035e 100644
4135 --- a/u-boot-1.1.6/common/cmd_mem.c
4136 +++ b/u-boot-1.1.6/common/cmd_mem.c
4137 @@ -1028,6 +1028,95 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
4142 + * Runs memory test from CFG_MEMTEST_END to CFG_MEMTEST_END.
4145 +int FullRamTest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
4148 + int test_passed = 1;
4150 + vu_long *addr_to_fail;
4151 + vu_long *current_addr;
4153 + vu_long *start = (ulong *)CFG_MEMTEST_START;
4154 + vu_long *end = (ulong *)CFG_MEMTEST_END;
4156 + ulong pattern1 = 0x5a5a5a5a;
4157 + ulong pattern2 = 0xa5a5a5a5;
4163 + printf("Performing Full Ram Test from 0x%08x to 0x%08x:\n", CFG_MEMTEST_START, CFG_MEMTEST_END - 1);
4168 + addr_to_fail = (ulong *)CFG_MEMTEST_END + 0x1000;
4170 + else if (argc > 1)
4172 + addr_to_fail = (ulong *)simple_strtoul(argv[1], NULL, 16);
4175 + for(current_addr = CFG_MEMTEST_START; current_addr < CFG_MEMTEST_END; current_addr+=2)
4177 + if ( (((long)current_addr & 0x3ffff) == 0) && (argc > 2) )
4178 + { /* print progress */
4179 + printf("0x%08x\r", current_addr);
4184 + if (current_addr != addr_to_fail)
4185 + { /* Run memory test here */
4186 + *current_addr = pattern1;
4187 + *(current_addr + 1) = pattern2;
4189 + val1 = *current_addr;
4190 + val2 = *(current_addr + 1);
4192 + if ((val1 == pattern1) && (val2 == pattern2))
4200 + if (test_passed < 1 && argc > 2)
4202 + if (val1 != pattern1)
4204 + printf("Ram test failed at 0x%08x\n", current_addr);
4205 + printf("\rExpected 0x%08x but read 0x%08x \r\n", val1, pattern1);
4207 + if (val2 != pattern2)
4209 + printf("Ram test failed at 0x%08x\n", current_addr + 1);
4210 + printf("\rExpected 0x%08x but read 0x%08x \r\n", val2, pattern2);
4217 + printf("\nDone testing 0x%08x addresses!\n", testcnt);
4222 + printf("%d\r\n", test_passed);
4225 + return test_passed ;
4233 @@ -1314,6 +1403,13 @@ U_BOOT_CMD(
4234 " - simple RAM read/write test\n"
4238 + ramtest, 3, 1, FullRamTest,
4239 + "ramtest - RAM test covering all but the last MB of Memory\n",
4241 + " - RAM read/write test\n"
4244 #ifdef CONFIG_MX_CYCLIC
4246 mdc, 4, 1, do_mem_mdc,
4247 diff --git a/u-boot-1.1.6/common/interface_select.c b/u-boot-1.1.6/common/interface_select.c
4248 new file mode 100644
4249 index 0000000..d571105
4251 +++ b/u-boot-1.1.6/common/interface_select.c
4253 +#include <common.h>
4254 +#include <watchdog.h>
4255 +#include <config.h>
4256 +#include <asm/blackfin.h>
4258 +#include <Metrologic_Hardware.h>
4259 +#include <metro_pf.h>
4261 +/* All transfers are described by this data structure */
4263 + u16 addr; /* slave address */
4265 +#define I2C_M_STOP 0x2
4266 +#define I2C_M_RD 0x1
4267 + u16 len; /* msg length */
4268 + u8 *buf; /* pointer to msg data */
4271 +#define CLR_PIN(x) set_pfx_level(x, 0)
4272 +#define SET_PIN(x) set_pfx_level(x, 1)
4273 +#define GPDRX_OUT(x) set_pfx_dir(x, 1)
4274 +#define GPDRX_IN(x) set_pfx_dir(x, 0)
4277 +//extern int i2c_transfer(struct i2c_msg *msg);
4278 +extern int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
4279 +extern int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
4281 +BOARD_FEATURE board_desc[] = {
4282 + { KBW_BOARD, 17 , 31 },
4283 + { LASER_EMULATION_BOARD, 33 , 47 },
4284 + { IBM_BOARD, 49 , 63 },
4285 + { OCIA_BOARD, 65 , 79 },
4286 + { LS_USB_HID_BOARD, 81 , 95 },
4287 + { LS_USB_POS_BOARD, 97 , 111 },
4288 + { FS_USB_BOARD, 113, 127 },
4289 + { BLUETOOTH_BOARD, 129, 143 },
4290 + { MULTIFUN_IBM_USB_BOARD, 145, 159 },
4291 + { RS232_BOARD, 241, 255 },
4295 +static unsigned char NOVRAM_Array[NOVRAM_SIGNATURE_LEN + NOVRAMSIZE];
4296 +static int Detected_Interface_Board;
4297 +static int AtoD_Value;
4300 + * Function will return rd_len if successful
4303 +#if defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
4306 +Psoc_I2C_Xfer(unsigned char *wr_msg, int wr_len,
4307 + unsigned char *rd_msg, int rd_len,
4314 + struct i2c_msg msg;
4316 +#if defined(CONFIG_HARD_I2C)
4317 + i2c_clk = CFG_I2C_SPEED;
4318 +#elif defined(CONFIG_SOFT_I2C)
4319 + i2c_clk = CFG_I2C_SPEED;
4324 + num_polls = timeout_uSec * i2c_clk / (1000000 * rd_len * 10);
4326 + if (num_polls < 1)
4331 + i2c_init(i2c_clk, PSOC_CHIP_ADDR);
4333 +// PRINTD("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x, buf0=0x%x\n", chip, addr, alen, len, buffer[0]);
4335 + /* write out command */
4337 + for (i = 0; i < NUM_RETRIES_ON_XFER; i++)
4339 + msg.addr = PSOC_CHIP_ADDR;
4344 +// if (i2c_transfer(&msg)) return -1;
4345 + if (i2c_write(PSOC_CHIP_ADDR, 0, 0, wr_msg, wr_len))
4354 + udelay(wait_uSec);
4358 + for (j = 0; j < num_polls; j++)
4360 + msg.addr = PSOC_CHIP_ADDR;
4361 + msg.flags = I2C_M_RD;
4365 +// if (i2c_transfer(&msg)) return -1;
4366 + if (i2c_read(PSOC_CHIP_ADDR, 0, 0, rd_msg, rd_len))
4371 + /* Check for valid data here */
4373 + if (rd_msg[0] == 0x06)
4374 + { /* Data is valid */
4379 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
4382 + udelay(10 * 1000);
4383 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
4394 + unsigned char wr_msg[1], rd_msg[2];
4398 + if (Psoc_I2C_Xfer(wr_msg, 1, rd_msg, 2, PSOC_COMMAND_DELAY_USEC, PSOC_COMMAND_TIMEOUT_USEC) < 0)
4400 +#if defined(DEBUG_METRO_IO)
4401 + printf("Error reading I2C()\r\n");
4407 +#if defined(DEBUG_METRO_IO)
4408 + printf("I2C read completed()\r\n");
4410 + return (int)rd_msg[1];
4416 +ReadInterfaceType(void)
4420 +#if defined(DEBUG_METRO_IO)
4421 + printf("start ReadAtoD()\r\n");
4423 +#if (CONFIG_METROLOGIC_VQ2D_REV)
4424 + AtoD_Value = Read_VQ_AtoD();
4426 + AtoD_Value = ReadAtoD();
4428 +#if defined(DEBUG_METRO_IO)
4429 + printf("returned from ReadAtoD()\r\n");
4432 + if (AtoD_Value < 0 || AtoD_Value > 255)
4434 + return UNKNOWN_INTERFACE_BOARD;
4437 + for (i = 0; i < NUM_SUPPORTED_INTERFACE_BOARD; i++)
4439 + if ((AtoD_Value <= board_desc[i].AtoD_high) && (AtoD_Value >= board_desc[i].AtoD_low))
4441 + return board_desc[i].board_type;
4445 + return UNKNOWN_INTERFACE_BOARD;
4450 +//extern int Get_Interface_AtoD_Value(void);
4453 +Send_Interface_AtoD_to_kernel(void)
4455 + DECLARE_GLOBAL_DATA_PTR;
4456 + char buf[256], buf2[32], *start, *end;
4457 + char *cmdline = getenv ("bootargs");
4461 + if ((start = strstr (cmdline, "intsel=")) == NULL)
4463 + strcpy (buf, cmdline);
4464 + sprintf(buf2, " intsel=%d", Get_Interface_AtoD_Value());
4465 + strcat (buf, buf2);
4469 + setenv ("bootargs", buf);
4472 +#endif /* CONFIG_METROLOGIC_INTERFACE_DETECTION */
4477 + ulong dev_addr = CFG_DEF_EEPROM_ADDR;
4478 + ulong addr = (ulong)NOVRAM_Array;
4479 + ulong off = CONFIG_START_OFFS;
4480 + ulong cnt = NOVRAM_SIGNATURE_LEN + NOVRAMSIZE;
4483 + if (eeprom_read (dev_addr, off, (uchar *) addr, cnt))
4488 + for (i = 0; i < NOVRAM_SIGNATURE_LEN; i++)
4490 + if (NOVRAM_Array[i] != NOVRAM_SIGNATURE[i])
4500 +get_NOVRAM_Data(int addr)
4502 + if (addr < 0 || addr > NOVRAMSIZE)
4506 + return NOVRAM_Array[addr + NOVRAM_SIGNATURE_LEN];
4510 +Configure_RTS_Pin(void)
4512 +#if defined(RTS_PIN)
4513 +#if defined(CONFIG_RTS_DEFAULT_ASSERTED)
4514 + if ( !(get_NOVRAM_Data(158) & (1 << 6)) )
4515 + { /* Not support for Metrologic RTS / CTS */
4520 + if (get_NOVRAM_Data(245) & 1)
4521 + { /* RTS level inverted, asserts high */
4525 + { /* RTS level normal, asserts low */
4530 + if (get_NOVRAM_Data(245) & 1)
4531 + { /* RTS level inverted, idles low */
4535 + { /* RTS level normal, idles high */
4539 + GPDRX_OUT(RTS_PIN);
4544 +Configure_Interface_IO(void)
4546 + if (GetNovram() < 0)
4547 + { /* Error reading NOVRAM */
4550 + for (i = 0; i < NOVRAM_SIGNATURE_LEN + NOVRAMSIZE; i++)
4552 + NOVRAM_Array[i] = 0;
4556 +#if (CONFIG_METROLOGIC_VQ2D_REV)
4557 + int interface_board;
4559 + interface_board = Detected_Interface_Board = ReadInterfaceType();
4561 + Configure_VQ2D_Interface_IO(interface_board);
4563 + if (interface_board == RS232_BOARD)
4565 + Configure_RTS_Pin();
4568 +#elif defined(CONFIG_METROLOGIC_INTERFACE_DETECTION)
4569 + int interface_board;
4571 + interface_board = Detected_Interface_Board = ReadInterfaceType();
4573 +#if defined(DEBUG_METRO_IO)
4574 + printf("returned from ReadInterfaceType()\r\n");
4577 + if (interface_board == KBW_BOARD)
4579 +#ifdef CONFIG_SUPPORT_KBW
4580 + /* configure RTS as KBClock (output low, but inverted to high
4581 + * at the interface board) for the KBW. If in stand-alone mode, kb
4582 + * would still be funcitonal and responsible for handshaking until
4583 + * kbw driver is loaded */
4584 + CLR_PIN(KBCLOCK_PIN);
4585 + GPDRX_OUT(KBCLOCK_PIN);
4587 + CLR_PIN(KBW_GATE_PIN); /* enable feed thru */
4589 +#if defined(DEBUG_METRO_IO)
4590 + printf("configured KBW\r\n");
4593 + else if (interface_board == RS232_BOARD || interface_board == LS_USB_HID_BOARD ||
4594 + interface_board == LS_USB_POS_BOARD || interface_board == FS_USB_BOARD ||
4595 + interface_board == IBM_BOARD )
4596 + { /* read the novram and set up the RTS level */
4597 +#if defined(RTS_PIN)
4598 +#if defined(CONFIG_RTS_DEFAULT_ASSERTED)
4599 + if ( !(get_NOVRAM_Data(158) & (1 << 6)) )
4600 + { /* Not support for Metrologic RTS / CTS */
4605 + if (get_NOVRAM_Data(245) & 1)
4606 + { /* RTS level inverted, asserts high */
4610 + { /* RTS level normal, asserts low */
4615 + if (get_NOVRAM_Data(245) & 1)
4616 + { /* RTS level inverted, idles low */
4620 + { /* RTS level normal, idles high */
4625 + GPDRX_OUT(RTS_PIN);
4626 +#endif /* RTS_PIN */
4628 +#ifdef CONFIG_SUPPORT_IBM
4629 + if (interface_board == IBM_BOARD)
4631 + CLR_PIN(IBM_RS4680_RESET_PIN);
4632 +#if defined(DEBUG_METRO_IO)
4633 + printf("configured IBM\r\n");
4638 + else if (interface_board == MULTIFUN_IBM_USB_BOARD)
4640 +#ifdef CONFIG_SUPPORT_MULTIFUNC
4641 + /* set up the I/O for MULTIFUN_IBM_USB_BOARD */
4642 + CLR_PIN(IBM_RS4680_RESET_PIN);
4643 + /* RTS line is used as CTS to Interface signal, for now, signal that Focus is
4644 + * ready to receive data so that nothing is lock up.
4645 + * CAUTION!!! Must confirm this is the right handshaking protocol */
4647 + GPDRX_OUT(RTS_PIN);
4650 + else if (interface_board == BLUETOOTH_BOARD)
4652 +#ifdef CONFIG_SUPPORT_BLUETOOTH
4653 + // configure IO pins
4654 + GPDRX_OUT(BT_LDO_PIN);
4655 + GPDRX_OUT(BT_RESET_PIN);
4656 + GPDRX_OUT(BT_SWITCH_PIN);
4657 + GPDRX_OUT(BLUE_LED_PIN);
4658 + GPDRX_OUT(WHITE_LED_PIN);
4659 + GPDRX_OUT(YELLOW_LED_PIN);
4661 + GPDRX_IN(BT_CONN_PIN);
4662 + GPDRX_IN(BT_RDY_PIN);
4663 + GPDRX_IN(BT_DSR_PIN);
4664 + GPDRX_IN(TRIG_PIN);
4666 + SET_PIN(BT_LDO_PIN);
4667 + SET_PIN(BT_RESET_PIN);
4668 + SET_PIN(BT_SWITCH_PIN);
4670 + CLR_PIN(FOCUS_KBWEN_PIN);
4671 + GPDRX_OUT(FOCUS_KBWEN_PIN);
4675 + /* Now enable the KB_GATE, BTRTS, PC_CLK, PC_DATA signals */
4676 +#ifdef FOCUS_KBWEN_PIN
4677 + if (FOCUS_KBWEN_PIN >= 0 && FOCUS_KBWEN_PIN < 48)
4679 + CLR_PIN(FOCUS_KBWEN_PIN); /* Active low signal */
4680 + GPDRX_OUT(FOCUS_KBWEN_PIN);
4684 +#else /* CONFIG_METROLOGIC_INTERFACE_DETECTION */
4686 +#if defined(RTS_PIN)
4687 + if (get_NOVRAM_Data(245) & 1)
4688 + { /* RTS level inverted, idles low */
4692 + { /* RTS level normal, idles high */
4696 + GPDRX_OUT(RTS_PIN);
4698 +#endif /* RTS_PIN */
4700 +#endif /* CONFIG_METROLOGIC_INTERFACE_DETECTION */
4702 + __builtin_bfin_ssync();
4707 +DisplayInterfaceBoard(void)
4709 + printf(INTERFACE_TYPE_TITLE);
4712 + switch(Detected_Interface_Board)
4715 + printf(INTERFACE_RS232_TEXT);
4719 + printf(INTERFACE_KBW_TEXT);
4722 + case LASER_EMULATION_BOARD:
4723 + printf(INTERFACE_UNKNOWN_TEXT);
4727 + printf(INTERFACE_IBM_TEXT);
4731 + printf(INTERFACE_OCIA_TEXT);
4734 + case LS_USB_HID_BOARD:
4735 + printf(INTERFACE_LSUSBHID_TEXT);
4738 + case LS_USB_POS_BOARD:
4739 + printf(INTERFACE_LSUSBPOS_TEXT);
4742 + case FS_USB_BOARD:
4743 + printf(INTERFACE_FSUSB_TEXT);
4746 + case BLUETOOTH_BOARD:
4747 + printf(INTERFACE_BLUETOOTH_TEXT);
4750 + case MULTIFUN_IBM_USB_BOARD:
4751 + printf(INTERFACE_MULTIFUN_USB_IBM_TEXT);
4755 + printf(INTERFACE_UNKNOWN_TEXT);
4762 + printf("IntSel A/D = %d\r\n", AtoD_Value);
4764 + printf("Novram[155] = 0x%02x\r\n", get_NOVRAM_Data(155));
4768 +int Get_Interface_Board_Type(void)
4770 + return Detected_Interface_Board;
4774 +int Get_Interface_AtoD_Value(void)
4776 + return AtoD_Value;
4779 diff --git a/u-boot-1.1.6/common/main.c b/u-boot-1.1.6/common/main.c
4780 index 0659c5b..6acc222 100644
4781 --- a/u-boot-1.1.6/common/main.c
4782 +++ b/u-boot-1.1.6/common/main.c
4787 +#include <config.h>
4788 #include <watchdog.h>
4789 #include <command.h>
4790 #ifdef CONFIG_MODEM_SUPPORT
4791 #include <malloc.h> /* for free() prototype */
4793 +#include <Metrologic_Hardware.h>
4794 +#include <metro_pf.h>
4796 #ifdef CFG_HUSH_PARSER
4798 @@ -49,6 +52,14 @@ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* fo
4801 extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
4802 +extern int Get_Interface_Board_Type(void);
4803 +extern int get_pfx_level(int pf_num);
4804 +extern int set_pfx_level(int pf_num, int level);
4805 +extern void set_cmdline_active(int active);
4807 +#define SET_PIN(gpio_pin) { set_pfx_level(gpio_pin, 1); }
4808 +#define CLR_PIN(gpio_pin) { set_pfx_level(gpio_pin, 0); }
4809 +#define GET_PIN_LEVEL(gpio_pin) ( get_pfx_level(gpio_pin) )
4812 #define MAX_DELAY_STOP_STR 32
4813 @@ -84,16 +95,66 @@ int do_mdm_init = 0;
4814 extern void mdm_init(void); /* defined in board.c */
4817 +#ifdef CONFIG_SUPPORT_BLUETOOTH
4818 +static __inline__ int bluetooth_abortboot(void)
4822 + if(Get_Interface_Board_Type() == BLUETOOTH_BOARD)
4824 + int ct, prev_state, curr_state;
4825 + int lh_trans = 0; // number of low-to-high transitions on trigger pin
4826 + int hl_trans = 0; // number of high-to-low transitions on trigger pin
4828 + prev_state = GET_PIN_LEVEL(TRIG_PIN);
4830 + if (prev_state == 0) // enter this loop only if trigger is initially activated
4831 + // (trigger is active-low)
4833 + SET_PIN(YELLOW_LED_PIN);
4834 + CLR_PIN(WHITE_LED_PIN);
4835 + CLR_PIN(BLUE_LED_PIN);
4837 + // Sit in a loop for 2 seconds and check trigger pin every 5 ms
4838 + for(ct=0; ct<400; ct++)
4841 + curr_state = GET_PIN_LEVEL(TRIG_PIN);
4842 + if (curr_state == 1 && prev_state == 0)
4846 + else if (curr_state == 0 && prev_state == 1)
4850 + prev_state = curr_state;
4852 + if(lh_trans > 1 && hl_trans > 1) // double-click detected
4857 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
4865 /***************************************************************************
4866 * Watch for 'delay' seconds for autoboot stop or autoboot delay string.
4867 * returns: 0 - no key string, allow autoboot
4868 * 1 - got key string, abort
4871 #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
4872 # if defined(CONFIG_AUTOBOOT_KEYED)
4873 static __inline__ int abortboot(int bootdelay)
4877 uint64_t etime = endtick(bootdelay);
4880 @@ -150,6 +211,13 @@ static __inline__ int abortboot(int bootdelay)
4881 presskey_max = presskey_max > delaykey[i].len ?
4882 presskey_max : delaykey[i].len;
4884 +#if defined CONFIG_ZERO_BOOTDELAY_CHECK
4885 + if (bootdelay == 0 && delaykey[i].len == 1)
4892 printf("%s key:<%s>\n",
4893 delaykey[i].retry ? "delay" : "stop",
4894 @@ -157,10 +225,23 @@ static __inline__ int abortboot(int bootdelay)
4898 +#if defined CONFIG_ZERO_BOOTDELAY_CHECK
4905 + presskey [presskey_len ++] = getc();
4910 /* In order to keep up with incoming data, check timeout only
4913 - while (!abort && get_ticks() <= etime) {
4914 + while (try_once > 0 || (!abort && get_ticks() <= etime)) {
4916 for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) {
4917 if (delaykey[i].len > 0 &&
4918 presskey_len >= delaykey[i].len &&
4919 @@ -198,6 +279,13 @@ static __inline__ int abortboot(int bootdelay)
4920 puts ("key timeout\n");
4923 +#ifdef CONFIG_SUPPORT_BLUETOOTH
4926 + abort = bluetooth_abortboot();
4930 #ifdef CONFIG_SILENT_CONSOLE
4932 /* permanently enable normal console output */
4933 @@ -274,6 +362,13 @@ static __inline__ int abortboot(int bootdelay)
4937 +#ifdef CONFIG_SUPPORT_BLUETOOTH
4940 + abort = bluetooth_abortboot();
4944 #ifdef CONFIG_SILENT_CONSOLE
4946 /* permanently enable normal console output */
4947 @@ -443,7 +538,31 @@ void main_loop (void)
4952 +#ifdef CONFIG_SUPPORT_BLUETOOTH
4953 + if(Get_Interface_Board_Type() == BLUETOOTH_BOARD)
4955 + CLR_PIN(YELLOW_LED_PIN);
4956 + SET_PIN(WHITE_LED_PIN); // indicates to user that we have entered the bootloader
4958 + CLR_PIN(BT_RESET_PIN); // reset Bluetooth chip
4959 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
4961 + SET_PIN(BT_RESET_PIN);
4963 + if (gd->baudrate != 115200)
4965 + // Reinitialize serial to 115200 bps
4966 + gd->baudrate = 115200;
4970 + WATCHDOG_RESET(); /* Trigger watchdog, if needed */
4972 + set_cmdline_active(1);
4977 * Main Loop for Monitor Command Processing
4979 #ifdef CFG_HUSH_PARSER
4980 diff --git a/u-boot-1.1.6/common/metro_pf.c b/u-boot-1.1.6/common/metro_pf.c
4981 new file mode 100644
4982 index 0000000..de6421b
4984 +++ b/u-boot-1.1.6/common/metro_pf.c
4986 +#include <common.h>
4987 +#include <config.h>
4988 +#include <asm/blackfin.h>
4989 +#include <metro_pf.h>
4992 +#define PF_bit(pfx) ( 1 << (pfx & 0x0f) )
4996 +//#define CSYNC asm("csync;")
5000 +//#define SSYNC asm("ssync;")
5003 +int Metro_set_pfx_dir(int pf_num, int dir, int initial_val);
5004 +int Metro_get_pfx_dir(int pf_num);
5006 +#if (defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) || \
5007 + defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) )
5011 +Metro_set_portF_pfx_dir(int pf_num, int dir, int initial_val)
5013 + unsigned short mask = PF_bit(pf_num);
5015 + *pPORTFIO_MASKA_CLEAR = mask;
5016 + *pPORTFIO_MASKB_CLEAR = mask;
5017 + *pPORTF_FER &= ~mask;
5021 + *pPORTFIO_INEN &= ~mask;
5022 + if (initial_val > 0)
5023 + *pPORTFIO_SET = mask;
5024 + else if (initial_val == 0)
5025 + *pPORTFIO_CLEAR = mask;
5026 + *pPORTFIO_DIR |= mask;
5027 + *pPORTFIO_POLAR &= ~mask;
5028 + *pPORTFIO_EDGE &= ~mask;
5029 + *pPORTFIO_BOTH &= ~mask;
5033 + *pPORTFIO_DIR &= ~mask;
5034 + *pPORTFIO_POLAR &= ~mask;
5035 + *pPORTFIO_EDGE &= ~mask;
5036 + *pPORTFIO_BOTH &= ~mask;
5037 + *pPORTFIO_INEN |= mask;
5043 +Metro_set_portG_pfx_dir(int pf_num, int dir, int initial_val)
5045 + unsigned short mask = PF_bit(pf_num);
5047 + *pPORTGIO_MASKA_CLEAR = mask;
5048 + *pPORTGIO_MASKB_CLEAR = mask;
5049 + *pPORTG_FER &= ~mask;
5053 + *pPORTGIO_INEN &= ~mask;
5054 + if (initial_val > 0)
5055 + *pPORTGIO_SET = mask;
5056 + else if (initial_val == 0)
5057 + *pPORTGIO_CLEAR = mask;
5058 + *pPORTGIO_DIR |= mask;
5059 + *pPORTGIO_POLAR &= ~mask;
5060 + *pPORTGIO_EDGE &= ~mask;
5061 + *pPORTGIO_BOTH &= ~mask;
5065 + *pPORTGIO_DIR &= ~mask;
5066 + *pPORTGIO_POLAR &= ~mask;
5067 + *pPORTGIO_EDGE &= ~mask;
5068 + *pPORTGIO_BOTH &= ~mask;
5069 + *pPORTGIO_INEN |= mask;
5075 +Metro_set_portH_pfx_dir(int pf_num, int dir, int initial_val)
5077 + unsigned short mask = PF_bit(pf_num);
5079 + *pPORTHIO_MASKA_CLEAR = mask;
5080 + *pPORTHIO_MASKB_CLEAR = mask;
5081 + *pPORTH_FER &= ~mask;
5085 + *pPORTHIO_INEN &= ~mask;
5086 + if (initial_val > 0)
5087 + *pPORTHIO_SET = mask;
5088 + else if (initial_val == 0)
5089 + *pPORTHIO_CLEAR = mask;
5090 + *pPORTHIO_DIR |= mask;
5091 + *pPORTHIO_POLAR &= ~mask;
5092 + *pPORTHIO_EDGE &= ~mask;
5093 + *pPORTHIO_BOTH &= ~mask;
5097 + *pPORTHIO_DIR &= ~mask;
5098 + *pPORTHIO_POLAR &= ~mask;
5099 + *pPORTHIO_EDGE &= ~mask;
5100 + *pPORTHIO_BOTH &= ~mask;
5101 + *pPORTHIO_INEN |= mask;
5107 +Metro_set_pfx_dir(int pf_num, int dir, int initial_val)
5109 + unsigned long flags;
5111 + if (pf_num < 0 || pf_num >= 48 || dir < 0 || dir > 1)
5116 + local_irq_save(flags);
5119 + Metro_set_portF_pfx_dir(pf_num, dir, initial_val);
5121 + else if (pf_num < 32)
5123 + Metro_set_portG_pfx_dir(pf_num, dir, initial_val);
5127 + Metro_set_portH_pfx_dir(pf_num, dir, initial_val);
5129 + local_irq_restore(flags);
5134 +#elif (defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) || \
5135 + defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) )
5138 +Metro_set_pfx_dir(int pf_num, int dir, int initial_val)
5140 + unsigned long flags;
5141 + unsigned short mask;
5143 + if (pf_num < 0 || pf_num >= 16 || dir < 0 || dir > 1)
5148 + mask = PF_bit(pf_num);
5149 + local_irq_save(flags);
5151 + *pFIO_MASKA_C = mask;
5152 + *pFIO_MASKB_C = mask;
5156 + *pFIO_INEN &= ~mask;
5157 + if (initial_val > 0)
5158 + *pFIO_FLAG_S = mask;
5159 + else if (initial_val == 0)
5160 + *pFIO_FLAG_C = mask;
5161 + *pFIO_DIR |= mask;
5162 + *pFIO_POLAR &= ~mask;
5163 + *pFIO_EDGE &= ~mask;
5164 + *pFIO_BOTH &= ~mask;
5168 + *pFIO_DIR &= ~mask;
5169 + *pFIO_POLAR &= ~mask;
5170 + *pFIO_EDGE &= ~mask;
5171 + *pFIO_BOTH &= ~mask;
5172 + *pFIO_INEN |= mask;
5176 + local_irq_restore(flags);
5181 +#error "undefined platform!!!"
5185 +#if (defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) || \
5186 + defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) )
5195 +Metro_get_pfx_dir(int pf_num)
5197 + unsigned short mask = PF_bit(pf_num);
5199 + if (pf_num < 0 || pf_num >= 48)
5206 + if (*pPORTF_FER & mask)
5209 + return (*pPORTFIO_DIR & mask ? 1 : 0);
5211 + else if (pf_num < 32)
5213 + if (*pPORTG_FER & mask)
5216 + return (*pPORTGIO_DIR & mask ? 1 : 0);
5220 + if (*pPORTH_FER & mask)
5223 + return (*pPORTHIO_DIR & mask ? 1 : 0);
5227 +#elif (defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) || \
5228 + defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) )
5238 +Metro_get_pfx_dir(int pf_num)
5240 + if (pf_num < 0 || pf_num >= 16)
5244 + return (*pFIO_DIR & PF_bit(pf_num) ? 1 : 0);
5250 +set_pfx_dir(int pf_num, int dir)
5252 + return Metro_set_pfx_dir(pf_num, dir, -1);
5256 +get_pfx_dir(int pf_num)
5258 + return Metro_get_pfx_dir(pf_num);
5262 +get_pfx_level(int pf_num)
5264 +#if (defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) || \
5265 + defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) )
5266 + if (pf_num < 0 || pf_num >= 48)
5270 +#elif (defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) || \
5271 + defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) )
5273 + if (pf_num < 0 || pf_num >= 16)
5279 + return Metro_get_pfx_level(pf_num);
5283 +set_pfx_level(int pf_num, int level)
5285 +#if (defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) || \
5286 + defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) )
5288 + if (pf_num < 0 || pf_num >= 48 || level < 0 || level > 1)
5292 +#elif (defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) || \
5293 + defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) )
5295 + if (pf_num < 0 || pf_num >= 16 || level < 0 || level > 1)
5301 + Metro_set_pfx_level(pf_num, level);
5304 diff --git a/u-boot-1.1.6/cpu/blackfin/i2c.c b/u-boot-1.1.6/cpu/blackfin/i2c.c
5305 index 0524680..8eaf509 100644
5306 --- a/u-boot-1.1.6/cpu/blackfin/i2c.c
5307 +++ b/u-boot-1.1.6/cpu/blackfin/i2c.c
5310 #include <asm/blackfin.h>
5311 #include <asm/mach-common/bits/twi.h>
5312 +#if defined DEBUG_I2C
5314 #define debugi(fmt, args...) \
5317 bfin_read_TWI_MASTER_STAT(), bfin_read_TWI_FIFO_STAT(), bfin_read_TWI_INT_STAT(), \
5318 __func__, __LINE__, ## args)
5321 +#define debugi(fmt, args...)
5325 #define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val)
5326 #define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val)
5327 @@ -126,14 +131,18 @@ static int wait_for_completion(struct i2c_msg *msg)
5329 * @return: 0 if things worked, non-0 if things failed
5331 -static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags)
5332 +int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags)
5335 uchar addr_buffer[] = {
5340 - struct i2c_msg msg = {
5342 + uchar addr_buffer[3 + 256];
5344 + struct i2c_msg msg = {
5345 .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
5348 @@ -141,8 +150,29 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len,
5353 - memset(buffer, 0xff, len);
5356 + addr_buffer[0] = (addr >> 0);
5357 + addr_buffer[0] = (addr >> 8);
5358 + addr_buffer[0] = (addr >> 16);
5360 + if (flags == 0) /* write operation */
5367 + msg.alen = alen + len;
5370 + for (i = 0; i < len; i++)
5372 + addr_buffer[alen + i] = buffer[i];
5376 +//??? memset(buffer, 0xff, len);
5377 debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ",
5378 chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr"));
5380 diff --git a/u-boot-1.1.6/cpu/blackfin/serial.c b/u-boot-1.1.6/cpu/blackfin/serial.c
5381 index f7b935d..1e5ebda 100644
5382 --- a/u-boot-1.1.6/cpu/blackfin/serial.c
5383 +++ b/u-boot-1.1.6/cpu/blackfin/serial.c
5388 +#include <config.h>
5389 #include <watchdog.h>
5390 #include <asm/blackfin.h>
5391 #include <asm/mach-common/bits/uart.h>
5397 +#include <Metrologic_Hardware.h>
5398 +#include <metro_pf.h>
5400 +extern int Get_Interface_Board_Type(void);
5401 +extern int get_pfx_level(int pf_num);
5402 +extern int set_pfx_level(int pf_num, int level);
5404 +#define SET_PIN(gpio_pin) { set_pfx_level(gpio_pin, 1); }
5405 +#define CLR_PIN(gpio_pin) { set_pfx_level(gpio_pin, 0); }
5406 +#define GET_PIN_LEVEL(gpio_pin) ( get_pfx_level(gpio_pin) )
5408 +#ifdef CONFIG_SUPPORT_BLUETOOTH
5409 +static int bt_state = 0;
5411 +static int cmdline_active = 0;
5413 +void set_cmdline_active(int active)
5415 + cmdline_active = active;
5418 #ifdef CONFIG_DEBUG_SERIAL
5419 uint16_t cached_lsr[256];
5420 uint16_t cached_rbr[256];
5421 @@ -114,6 +137,14 @@ int serial_init(void)
5423 void serial_putc(const char c)
5425 +#ifdef CONFIG_SUPPORT_BLUETOOTH
5426 + if (Get_Interface_Board_Type() == BLUETOOTH_BOARD && bt_state == 0)
5433 /* send a \r for compatibility */
5436 @@ -138,16 +169,67 @@ void serial_putc(const char c)
5437 int serial_tstc(void)
5440 +#ifdef CONFIG_SUPPORT_BLUETOOTH
5443 + int board_type = Get_Interface_Board_Type();
5445 + if(board_type == BLUETOOTH_BOARD && cmdline_active == 1)
5447 + bt_pin_level = GET_PIN_LEVEL(BT_CONN_PIN);
5448 + if (bt_state == 0 && bt_pin_level == 1)
5451 + SET_PIN(BLUE_LED_PIN);
5455 + if (bt_state == 1 && bt_pin_level == 0)
5458 + CLR_PIN(BLUE_LED_PIN);
5466 return (uart_lsr_read() & DR) ? 1 : 0;
5469 int serial_getc(void)
5471 uint16_t uart_rbr_val;
5472 +#ifdef CONFIG_SUPPORT_BLUETOOTH
5473 + int board_type = Get_Interface_Board_Type();
5478 /* wait for data ! */
5479 while (!serial_tstc())
5481 +#ifdef CONFIG_SUPPORT_BLUETOOTH
5482 + if(board_type == BLUETOOTH_BOARD && cmdline_active == 1)
5484 + bt_pin_level = GET_PIN_LEVEL(BT_CONN_PIN);
5485 + if (bt_state == 0 && bt_pin_level == 1)
5488 + SET_PIN(BLUE_LED_PIN);
5491 + if (bt_state == 1 && bt_pin_level == 0)
5494 + CLR_PIN(BLUE_LED_PIN);
5502 /* grab the new byte */
5503 uart_rbr_val = *pUART_RBR;
5504 diff --git a/u-boot-1.1.6/examples/Makefile b/u-boot-1.1.6/examples/Makefile
5505 index 75753a2..85df974 100644
5506 --- a/u-boot-1.1.6/examples/Makefile
5507 +++ b/u-boot-1.1.6/examples/Makefile
5508 @@ -89,9 +89,23 @@ BIN += sched.bin
5511 ifeq ($(ARCH),blackfin)
5513 +ifneq ($(BOARD),bf537-stamp)
5514 +ifneq ($(BOARD),bf533-stamp)
5515 +ifneq ($(BOARD),Focus)
5516 +ifneq ($(BOARD),Orbit3)
5517 +ifneq ($(BOARD),VuQuest2D)
5519 ELF += smc91111_eeprom smsc9118_eeprom
5520 SREC += smc91111_eeprom.srec smsc9118_eeprom.srec
5521 BIN += smc91111_eeprom.bin smsc9118_eeprom.bin
5526 +endif # bf533-stamp
5527 +endif # bf537-stamp
5531 # The following example is pretty 8xx specific...
5532 diff --git a/u-boot-1.1.6/include/Metrologic_Hardware.h b/u-boot-1.1.6/include/Metrologic_Hardware.h
5533 new file mode 100644
5534 index 0000000..19506af
5536 +++ b/u-boot-1.1.6/include/Metrologic_Hardware.h
5538 +#ifndef METROLOGIC_HARDWARE_H
5539 +#define METROLOGIC_HARDWARE_H
5541 +#define PADDING_CHAR 0xff
5542 +#define SPI_SECTOR_SIZE 0x10000
5543 +#define PADDING_BUFF_SIZE SPI_SECTOR_SIZE
5545 +#define U_BOOT_START_OFFS 0x000000
5546 +#define CONFIG_START_OFFS 0x040000
5547 +#define KERNEL_START_OFFS 0x060000
5548 +#define FILSYS_START_OFFS 0x100000
5550 +#define FLASH_PARTITION_START 0x20000000
5552 +#define U_BOOT_START_ADDR ( U_BOOT_START_OFFS + FLASH_PARTITION_START)
5553 +#define CONFIG_START_ADDR ( CONFIG_START_OFFS + FLASH_PARTITION_START)
5554 +#define KERNEL_START_ADDR ( KERNEL_START_OFFS + FLASH_PARTITION_START)
5555 +#define FILSYS_START_ADDR ( FILSYS_START_OFFS + FLASH_PARTITION_START)
5557 +#define NOVRAM_SIGNATURE "MTLG FOCUS TK 04"
5558 +#define NOVRAM_SIGNATURE_LEN 16
5559 +#define NOVRAMSIZE 512
5562 +#define NUM_RETRIES_ON_XFER 3
5563 +#define PSOC_COMMAND_DELAY_USEC 100
5564 +#define PSOC_COMMAND_TIMEOUT_USEC 1000
5566 +#define PSOC_CHIP_ADDR 0x71
5569 +#define INTERFACE_TYPE_TITLE "Interface Board:"
5570 +#define INTERFACE_RS232_TEXT "RS232"
5571 +#define INTERFACE_KBW_TEXT "Keyboard Wedge"
5572 +#define INTERFACE_IBM_TEXT "IBM"
5573 +#define INTERFACE_OCIA_TEXT "OCIA"
5574 +#define INTERFACE_LSUSBHID_TEXT "USB-HID"
5575 +#define INTERFACE_LSUSBPOS_TEXT "USB-POS"
5576 +#define INTERFACE_FSUSB_TEXT "FS-USB"
5577 +#define INTERFACE_BLUETOOTH_TEXT "BlueTooth"
5578 +#define INTERFACE_MULTIFUN_USB_IBM_TEXT "MultiFunction"
5579 +#define INTERFACE_UNKNOWN_TEXT "Unknown"
5581 +#define UNKNOWN_INTERFACE_BOARD 999
5586 + LASER_EMULATION_BOARD,
5593 + MULTIFUN_IBM_USB_BOARD,
5594 + NUM_SUPPORTED_INTERFACE_BOARD
5603 +extern BOARD_FEATURE board_desc[];
5606 +#endif /* METROLOGIC_HARDWARE_H */
5607 diff --git a/u-boot-1.1.6/include/asm-blackfin/blackfin-config-post.h b/u-boot-1.1.6/include/asm-blackfin/blackfin-config-post.h
5608 index 0ad4715..ec5bc5d 100644
5609 --- a/u-boot-1.1.6/include/asm-blackfin/blackfin-config-post.h
5610 +++ b/u-boot-1.1.6/include/asm-blackfin/blackfin-config-post.h
5612 #ifndef __ASM_BLACKFIN_CONFIG_POST_H__
5613 #define __ASM_BLACKFIN_CONFIG_POST_H__
5615 -/* Sanity check CONFIG_BFIN_CPU */
5616 -#ifndef CONFIG_BFIN_CPU
5617 -# error CONFIG_BFIN_CPU: your board config needs to define this
5620 -/* Make sure the structure is properly aligned */
5621 -#if ((CFG_GBL_DATA_ADDR & -4) != CFG_GBL_DATA_ADDR)
5622 -# error CFG_GBL_DATA_ADDR: must be 4 byte aligned
5625 -/* Set default CONFIG_VCO_HZ if need be */
5626 -#if !defined(CONFIG_VCO_HZ)
5627 -# if (CONFIG_CLKIN_HALF == 0)
5628 -# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
5630 -# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2)
5634 -/* Set default CONFIG_CCLK_HZ if need be */
5635 -#if !defined(CONFIG_CCLK_HZ)
5636 -# if (CONFIG_PLL_BYPASS == 0)
5637 -# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV)
5639 -# define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
5643 -/* Set default CONFIG_SCLK_HZ if need be */
5644 -#if !defined(CONFIG_SCLK_HZ)
5645 -# if (CONFIG_PLL_BYPASS == 0)
5646 -# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV)
5648 -# define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
5652 -/* Since we use these to program PLL registers directly,
5653 - * make sure the values are sane and won't screw us up.
5655 -#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT
5656 -# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63)
5658 -#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF
5659 -# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1
5661 -#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS
5662 -# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1
5664 +#include <asm/blackfin_clocks.h>
5666 /* Using L1 scratch pad makes sense for everyone by default. */
5667 #ifndef CMD_LINE_ADDR
5668 diff --git a/u-boot-1.1.6/include/asm-blackfin/blackfin_clocks.h b/u-boot-1.1.6/include/asm-blackfin/blackfin_clocks.h
5669 new file mode 100644
5670 index 0000000..67c7709
5672 +++ b/u-boot-1.1.6/include/asm-blackfin/blackfin_clocks.h
5674 +#ifndef __ASM_BLACKFIN_CLOCKS_H__
5675 +#define __ASM_BLACKFIN_CLOCKS_H__
5677 +/* Sanity check CONFIG_BFIN_CPU */
5678 +#ifndef CONFIG_BFIN_CPU
5679 +# error CONFIG_BFIN_CPU: your board config needs to define this
5682 +/* Set default CONFIG_CCLK_HZ if need be */
5683 +#if !defined(CONFIG_CCLK_HZ)
5684 +# if (CONFIG_PLL_BYPASS == 0)
5685 +# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV)
5687 +# define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
5691 +/* Set default CONFIG_SCLK_HZ if need be */
5692 +#if !defined(CONFIG_SCLK_HZ)
5693 +# if (CONFIG_PLL_BYPASS == 0)
5694 +# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV)
5696 +# define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
5700 +/* Since we use these to program PLL registers directly,
5701 + * make sure the values are sane and won't screw us up.
5703 +#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT
5704 +# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63)
5706 +#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF
5707 +# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1
5709 +#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS
5710 +# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1
5713 +/* Make sure the structure is properly aligned */
5714 +#if ((CFG_GBL_DATA_ADDR & -4) != CFG_GBL_DATA_ADDR)
5715 +# error CFG_GBL_DATA_ADDR: must be 4 byte aligned
5718 +/* Set default CONFIG_VCO_HZ if need be */
5719 +#if !defined(CONFIG_VCO_HZ)
5720 +# if (CONFIG_CLKIN_HALF == 0)
5721 +# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
5723 +# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2)
5727 +#endif /* __ASM_BLACKFIN_CLOCKS_H__ */
5730 diff --git a/u-boot-1.1.6/include/asm-blackfin/mem_init.h b/u-boot-1.1.6/include/asm-blackfin/mem_init.h
5731 new file mode 100644
5732 index 0000000..e413aae
5734 +++ b/u-boot-1.1.6/include/asm-blackfin/mem_init.h
5736 +#ifndef __ASM_MEM_INIT_H__
5737 +#define __ASM_MEM_INIT_H__
5739 + * U-boot - mem_init.h Header file for memory initialization
5741 + * Copyright (c) 2005 blackfin.uclinux.org
5743 + * See file CREDITS for list of people who contributed to this
5746 + * This program is free software; you can redistribute it and/or
5747 + * modify it under the terms of the GNU General Public License as
5748 + * published by the Free Software Foundation; either version 2 of
5749 + * the License, or (at your option) any later version.
5751 + * This program is distributed in the hope that it will be useful,
5752 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5753 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5754 + * GNU General Public License for more details.
5756 + * You should have received a copy of the GNU General Public License
5757 + * along with this program; if not, write to the Free Software
5758 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
5759 + * MA 02111-1307 USA
5761 +#include <asm/blackfin_clocks.h>
5763 +#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \
5764 + CONFIG_MEM_MT48LC64M4A2FB_7E || \
5765 + CONFIG_MEM_MT48LC16M8A2TG_75 || \
5766 + CONFIG_MEM_MT48LC8M16A2TG_7E || \
5767 + CONFIG_MEM_MT48LC8M32B2B5_7 || \
5768 + CONFIG_MEM_MT48LC32M8A2_75 || \
5769 + CONFIG_MEM_IS42S16160B_7 \
5772 + #if ( CONFIG_SCLK_HZ > 119402985 )
5773 + #define SDRAM_tRP TRP_2
5774 + #define SDRAM_tRP_num 2
5775 + #define SDRAM_tRAS TRAS_7
5776 + #define SDRAM_tRAS_num 7
5777 + #define SDRAM_tRCD TRCD_2
5778 + #define SDRAM_tWR TWR_2
5780 + #if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 )
5781 + #define SDRAM_tRP TRP_2
5782 + #define SDRAM_tRP_num 2
5783 + #define SDRAM_tRAS TRAS_6
5784 + #define SDRAM_tRAS_num 6
5785 + #define SDRAM_tRCD TRCD_2
5786 + #define SDRAM_tWR TWR_2
5788 + #if ( CONFIG_SCLK_HZ > 89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 )
5789 + #define SDRAM_tRP TRP_2
5790 + #define SDRAM_tRP_num 2
5791 + #define SDRAM_tRAS TRAS_5
5792 + #define SDRAM_tRAS_num 5
5793 + #define SDRAM_tRCD TRCD_2
5794 + #define SDRAM_tWR TWR_2
5796 + #if ( CONFIG_SCLK_HZ > 74626866 ) && ( CONFIG_SCLK_HZ <= 89552239 )
5797 + #define SDRAM_tRP TRP_2
5798 + #define SDRAM_tRP_num 2
5799 + #define SDRAM_tRAS TRAS_4
5800 + #define SDRAM_tRAS_num 4
5801 + #define SDRAM_tRCD TRCD_2
5802 + #define SDRAM_tWR TWR_2
5804 + #if ( CONFIG_SCLK_HZ > 66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 )
5805 + #define SDRAM_tRP TRP_2
5806 + #define SDRAM_tRP_num 2
5807 + #define SDRAM_tRAS TRAS_3
5808 + #define SDRAM_tRAS_num 3
5809 + #define SDRAM_tRCD TRCD_2
5810 + #define SDRAM_tWR TWR_2
5812 + #if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
5813 + #define SDRAM_tRP TRP_1
5814 + #define SDRAM_tRP_num 1
5815 + #define SDRAM_tRAS TRAS_3
5816 + #define SDRAM_tRAS_num 3
5817 + #define SDRAM_tRCD TRCD_1
5818 + #define SDRAM_tWR TWR_2
5820 + #if ( CONFIG_SCLK_HZ > 44776119 ) && ( CONFIG_SCLK_HZ <= 59701493 )
5821 + #define SDRAM_tRP TRP_1
5822 + #define SDRAM_tRP_num 1
5823 + #define SDRAM_tRAS TRAS_3
5824 + #define SDRAM_tRAS_num 3
5825 + #define SDRAM_tRCD TRCD_1
5826 + #define SDRAM_tWR TWR_2
5828 + #if ( CONFIG_SCLK_HZ > 29850746 ) && ( CONFIG_SCLK_HZ <= 44776119 )
5829 + #define SDRAM_tRP TRP_1
5830 + #define SDRAM_tRP_num 1
5831 + #define SDRAM_tRAS TRAS_2
5832 + #define SDRAM_tRAS_num 2
5833 + #define SDRAM_tRCD TRCD_1
5834 + #define SDRAM_tWR TWR_2
5836 + #if ( CONFIG_SCLK_HZ <= 29850746 )
5837 + #define SDRAM_tRP TRP_1
5838 + #define SDRAM_tRP_num 1
5839 + #define SDRAM_tRAS TRAS_1
5840 + #define SDRAM_tRAS_num 1
5841 + #define SDRAM_tRCD TRCD_1
5842 + #define SDRAM_tWR TWR_2
5846 +#if (CONFIG_MEM_IS42S16160B_7)
5847 + /*SDRAM INFORMATION: */
5848 + #define SDRAM_Tref 64 /* Refresh period in milliseconds */
5849 + #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
5850 + #define SDRAM_CL CL_2
5853 +#if (CONFIG_MEM_MT48LC16M16A2TG_75)
5854 + /*SDRAM INFORMATION: */
5855 + #define SDRAM_Tref 64 /* Refresh period in milliseconds */
5856 + #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
5857 + #define SDRAM_CL CL_3
5860 +#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
5861 + /*SDRAM INFORMATION: */
5862 + #define SDRAM_Tref 64 /* Refresh period in milliseconds */
5863 + #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
5864 + #define SDRAM_CL CL_2
5867 +#if (CONFIG_MEM_MT48LC16M8A2TG_75)
5868 + /*SDRAM INFORMATION: */
5869 + #define SDRAM_Tref 64 /* Refresh period in milliseconds */
5870 + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
5871 + #define SDRAM_CL CL_3
5874 +#if (CONFIG_MEM_MT48LC32M8A2_75)
5875 + /*SDRAM INFORMATION: */
5876 +#define SDRAM_Tref 64 /* Refresh period in milliseconds */
5877 +#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
5878 +#define SDRAM_CL CL_3
5881 +#if (CONFIG_MEM_MT48LC8M16A2TG_7E)
5882 + /*SDRAM INFORMATION: */
5883 + #define SDRAM_Tref 64 /* Refresh period in milliseconds */
5884 + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
5885 + #define SDRAM_CL CL_2
5888 +#if (CONFIG_MEM_MT48LC8M32B2B5_7)
5889 + /*SDRAM INFORMATION: */
5890 + #define SDRAM_Tref 64 /* Refresh period in milliseconds */
5891 + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
5892 + #define SDRAM_CL CL_3
5895 +#if ( CONFIG_MEM_SIZE == 128 )
5896 + #define SDRAM_SIZE EBSZ_128
5898 +#if ( CONFIG_MEM_SIZE == 64 )
5899 + #define SDRAM_SIZE EBSZ_64
5901 +#if ( CONFIG_MEM_SIZE == 32 )
5902 + #define SDRAM_SIZE EBSZ_32
5904 +#if ( CONFIG_MEM_SIZE == 16 )
5905 + #define SDRAM_SIZE EBSZ_16
5907 +#if ( CONFIG_MEM_ADD_WDTH == 11 )
5908 + #define SDRAM_WIDTH EBCAW_11
5910 +#if ( CONFIG_MEM_ADD_WDTH == 10 )
5911 + #define SDRAM_WIDTH EBCAW_10
5913 +#if ( CONFIG_MEM_ADD_WDTH == 9 )
5914 + #define SDRAM_WIDTH EBCAW_9
5916 +#if ( CONFIG_MEM_ADD_WDTH == 8 )
5917 + #define SDRAM_WIDTH EBCAW_8
5920 +#define mem_SDBCTL SDRAM_WIDTH | SDRAM_SIZE | EBE
5922 +/* Equation from section 17 (p17-46) of BF533 HRM */
5923 +#define mem_SDRRC ((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
5925 +/* Enable SCLK Out */
5926 +#define mem_SDGCTL ( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS )
5928 +#define flash_EBIU_AMBCTL_WAT ( ( CONFIG_FLASH_SPEED_BWAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
5929 +#define flash_EBIU_AMBCTL_RAT ( ( CONFIG_FLASH_SPEED_BRAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
5930 +#define flash_EBIU_AMBCTL_HT ( ( CONFIG_FLASH_SPEED_BHT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) )
5931 +#define flash_EBIU_AMBCTL_ST ( ( CONFIG_FLASH_SPEED_BST * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
5932 +#define flash_EBIU_AMBCTL_TT ( ( CONFIG_FLASH_SPEED_BTT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
5934 +#if (flash_EBIU_AMBCTL_TT > 3 )
5935 + #define flash_EBIU_AMBCTL0_TT B0TT_4
5937 +#if (flash_EBIU_AMBCTL_TT == 3 )
5938 + #define flash_EBIU_AMBCTL0_TT B0TT_3
5940 +#if (flash_EBIU_AMBCTL_TT == 2 )
5941 + #define flash_EBIU_AMBCTL0_TT B0TT_2
5943 +#if (flash_EBIU_AMBCTL_TT < 2 )
5944 + #define flash_EBIU_AMBCTL0_TT B0TT_1
5947 +#if (flash_EBIU_AMBCTL_ST > 3 )
5948 + #define flash_EBIU_AMBCTL0_ST B0ST_4
5950 +#if (flash_EBIU_AMBCTL_ST == 3 )
5951 + #define flash_EBIU_AMBCTL0_ST B0ST_3
5953 +#if (flash_EBIU_AMBCTL_ST == 2 )
5954 + #define flash_EBIU_AMBCTL0_ST B0ST_2
5956 +#if (flash_EBIU_AMBCTL_ST < 2 )
5957 + #define flash_EBIU_AMBCTL0_ST B0ST_1
5960 +#if (flash_EBIU_AMBCTL_HT > 2 )
5961 + #define flash_EBIU_AMBCTL0_HT B0HT_3
5963 +#if (flash_EBIU_AMBCTL_HT == 2 )
5964 + #define flash_EBIU_AMBCTL0_HT B0HT_2
5966 +#if (flash_EBIU_AMBCTL_HT == 1 )
5967 + #define flash_EBIU_AMBCTL0_HT B0HT_1
5969 +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
5970 + #define flash_EBIU_AMBCTL0_HT B0HT_0
5972 +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
5973 + #define flash_EBIU_AMBCTL0_HT B0HT_1
5976 +#if (flash_EBIU_AMBCTL_WAT > 14)
5977 + #define flash_EBIU_AMBCTL0_WAT B0WAT_15
5979 +#if (flash_EBIU_AMBCTL_WAT == 14)
5980 + #define flash_EBIU_AMBCTL0_WAT B0WAT_14
5982 +#if (flash_EBIU_AMBCTL_WAT == 13)
5983 + #define flash_EBIU_AMBCTL0_WAT B0WAT_13
5985 +#if (flash_EBIU_AMBCTL_WAT == 12)
5986 + #define flash_EBIU_AMBCTL0_WAT B0WAT_12
5988 +#if (flash_EBIU_AMBCTL_WAT == 11)
5989 + #define flash_EBIU_AMBCTL0_WAT B0WAT_11
5991 +#if (flash_EBIU_AMBCTL_WAT == 10)
5992 + #define flash_EBIU_AMBCTL0_WAT B0WAT_10
5994 +#if (flash_EBIU_AMBCTL_WAT == 9)
5995 + #define flash_EBIU_AMBCTL0_WAT B0WAT_9
5997 +#if (flash_EBIU_AMBCTL_WAT == 8)
5998 + #define flash_EBIU_AMBCTL0_WAT B0WAT_8
6000 +#if (flash_EBIU_AMBCTL_WAT == 7)
6001 + #define flash_EBIU_AMBCTL0_WAT B0WAT_7
6003 +#if (flash_EBIU_AMBCTL_WAT == 6)
6004 + #define flash_EBIU_AMBCTL0_WAT B0WAT_6
6006 +#if (flash_EBIU_AMBCTL_WAT == 5)
6007 + #define flash_EBIU_AMBCTL0_WAT B0WAT_5
6009 +#if (flash_EBIU_AMBCTL_WAT == 4)
6010 + #define flash_EBIU_AMBCTL0_WAT B0WAT_4
6012 +#if (flash_EBIU_AMBCTL_WAT == 3)
6013 + #define flash_EBIU_AMBCTL0_WAT B0WAT_3
6015 +#if (flash_EBIU_AMBCTL_WAT == 2)
6016 + #define flash_EBIU_AMBCTL0_WAT B0WAT_2
6018 +#if (flash_EBIU_AMBCTL_WAT == 1)
6019 + #define flash_EBIU_AMBCTL0_WAT B0WAT_1
6022 +#if (flash_EBIU_AMBCTL_RAT > 14)
6023 + #define flash_EBIU_AMBCTL0_RAT B0RAT_15
6025 +#if (flash_EBIU_AMBCTL_RAT == 14)
6026 + #define flash_EBIU_AMBCTL0_RAT B0RAT_14
6028 +#if (flash_EBIU_AMBCTL_RAT == 13)
6029 + #define flash_EBIU_AMBCTL0_RAT B0RAT_13
6031 +#if (flash_EBIU_AMBCTL_RAT == 12)
6032 + #define flash_EBIU_AMBCTL0_RAT B0RAT_12
6034 +#if (flash_EBIU_AMBCTL_RAT == 11)
6035 + #define flash_EBIU_AMBCTL0_RAT B0RAT_11
6037 +#if (flash_EBIU_AMBCTL_RAT == 10)
6038 + #define flash_EBIU_AMBCTL0_RAT B0RAT_10
6040 +#if (flash_EBIU_AMBCTL_RAT == 9)
6041 + #define flash_EBIU_AMBCTL0_RAT B0RAT_9
6043 +#if (flash_EBIU_AMBCTL_RAT == 8)
6044 + #define flash_EBIU_AMBCTL0_RAT B0RAT_8
6046 +#if (flash_EBIU_AMBCTL_RAT == 7)
6047 + #define flash_EBIU_AMBCTL0_RAT B0RAT_7
6049 +#if (flash_EBIU_AMBCTL_RAT == 6)
6050 + #define flash_EBIU_AMBCTL0_RAT B0RAT_6
6052 +#if (flash_EBIU_AMBCTL_RAT == 5)
6053 + #define flash_EBIU_AMBCTL0_RAT B0RAT_5
6055 +#if (flash_EBIU_AMBCTL_RAT == 4)
6056 + #define flash_EBIU_AMBCTL0_RAT B0RAT_4
6058 +#if (flash_EBIU_AMBCTL_RAT == 3)
6059 + #define flash_EBIU_AMBCTL0_RAT B0RAT_3
6061 +#if (flash_EBIU_AMBCTL_RAT == 2)
6062 + #define flash_EBIU_AMBCTL0_RAT B0RAT_2
6064 +#if (flash_EBIU_AMBCTL_RAT == 1)
6065 + #define flash_EBIU_AMBCTL0_RAT B0RAT_1
6069 +//#define flash_EBIU_AMBCTL0 flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN
6070 +#define CONFIG_FLASH_SPEED_RDYEN 0
6071 +#define flash_EBIU_AMBCTL0 flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN
6074 diff --git a/u-boot-1.1.6/include/configs/Focus.h b/u-boot-1.1.6/include/configs/Focus.h
6075 new file mode 100644
6076 index 0000000..e56c362
6078 +++ b/u-boot-1.1.6/include/configs/Focus.h
6081 + * U-boot - Configuration file for BF537 STAMP board
6084 +#ifndef __CONFIG_FOCUS_H__
6085 +#define __CONFIG_FOCUS_H__
6087 +#include <asm/blackfin-config-pre.h>
6090 +#ifndef __ADSPBF534__
6091 +#define __ADSPBF534__
6093 +#define METROLOGIC_PLATFORM "Focus"
6094 +#define SUPPORT_NETWORKING 0
6095 +#define CONFIG_SILENT_CONSOLE 1
6096 +#define CONFIG_BAUDRATE 115200
6097 +#define CONFIG_LOADADDR 0x800000
6099 +//#define METROLOGIC_FLASH_BOOT_ENV_PARAM "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
6101 +#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
6102 + "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
6104 +#define CFG_PROMPT "bootldr> "
6105 +#define CONFIG_ZERO_BOOTDELAY_CHECK
6106 +#define CONFIG_AUTOBOOT_KEYED 1
6107 +#define CONFIG_AUTOBOOT_STOP_STR "\033"
6108 +#define CONFIG_MEM_MT48LC16M16A2TG_75 1
6109 +//#define CONFIG_MEM_IS42S16160B_7 1
6111 +//#define CONFIG_DEBUG_EARLY_SERIAL 1
6112 +//#define DEBUG_BOOTKEYS 1
6114 +//#define DEBUG_METRO_IO 1
6115 +//#define DEBUG_I2C 1
6117 +// We don't have a parallel flash chip there
6118 +#define CFG_NO_FLASH
6122 + * Processor Settings
6124 +#define CONFIG_BFIN_CPU bf534-0.2
6125 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
6130 + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
6131 + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
6133 +/* CONFIG_CLKIN_HZ is any value in Hz */
6134 +#define CONFIG_CLKIN_HZ 25000000
6135 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
6136 +/* 1 = CLKIN / 2 */
6137 +#define CONFIG_CLKIN_HALF 0
6138 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
6139 +/* 1 = bypass PLL */
6140 +#define CONFIG_PLL_BYPASS 0
6141 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
6142 +/* Values can range from 0-63 (where 0 means 64) */
6143 +#define CONFIG_VCO_MULT 20
6144 +/* CCLK_DIV controls the core clock divider */
6145 +/* Values can be 1, 2, 4, or 8 ONLY */
6146 +#define CONFIG_CCLK_DIV 1
6147 +/* SCLK_DIV controls the system clock divider */
6148 +/* Values can range from 1-15 */
6149 +#define CONFIG_SCLK_DIV 4
6155 +#define CONFIG_MEM_ADD_WDTH 9
6156 +#define CONFIG_MEM_SIZE 32
6158 +//#define CONFIG_EBIU_SDRRC_VAL 0x306
6159 +//#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
6160 +//#define CONFIG_EBIU_SDBCTL_VAL (EBSZ_64 | EBCAW_10 | EBE)
6162 +#define CONFIG_EBIU_AMGCTL_VAL 0xFF
6163 +//#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
6164 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
6166 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for monitor */
6167 +#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 384 kB for malloc() (video/spi are big) */
6168 +#define CFG_GBL_DATA_SIZE 0x4000
6172 + * Network Settings
6174 +#if SUPPORT_NETWORKING
6175 +#ifndef __ADSPBF534__
6176 +#define ADI_CMDS_NETWORK 1
6177 +#define CONFIG_BFIN_MAC
6178 +#define CONFIG_NETCONSOLE 1
6179 +#define CONFIG_NET_MULTI 1
6181 +#define ADI_CMDS_NETWORK 0
6184 +#define CONFIG_HOSTNAME bf537-stamp
6185 +/* Uncomment next line to use fixed MAC address */
6186 +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
6192 +#define CFG_FLASH_BASE 0x20000000
6193 +#define CFG_FLASH_CFI /* The flash is CFI compatible */
6194 +//#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
6195 +//#define CFG_FLASH_PROTECTION
6196 +#define CFG_MAX_FLASH_BANKS 1
6197 +#define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
6198 +#define FLASH_SIZE 0x800000
6199 +#define CFG_FLASH_SIZE 0x800000
6202 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
6203 +#define CFG_ENV_IS_IN_EEPROM 1
6204 +#define CFG_ENV_OFFSET 0x4000
6205 +#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
6207 +#define CFG_ENV_IS_IN_FLASH 1
6208 +#define CFG_ENV_ADDR 0x20004000
6209 +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
6211 +#define CFG_ENV_SIZE 0x2000
6212 +#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
6213 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
6214 +#define ENV_IS_EMBEDDED
6216 +#define ENV_IS_EMBEDDED_CUSTOM
6219 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
6220 +/* Values can range from 2-65535 */
6221 +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
6223 +#define CONFIG_SPI_BAUD 2
6224 +#define CONFIG_SPI_BAUD_INITBLOCK 3
6230 +#define CONFIG_HARD_I2C 1 /* I2C TWI */
6231 +#define CFG_I2C_SPEED 50000
6232 +#define CFG_I2C_SLAVE 0
6238 +/* #define CONFIG_BF537_NAND */
6239 +#ifdef CONFIG_BF537_NAND
6240 +# define ADD_NAND_CMD CFG_CMD_NAND
6242 +# define ADD_NAND_CMD 0
6245 +#define CFG_NAND_ADDR 0x20212000
6246 +#define CFG_NAND_BASE CFG_NAND_ADDR
6247 +#define CFG_MAX_NAND_DEVICE 1
6248 +#define SECTORSIZE 512
6249 +#define ADDR_COLUMN 1
6250 +#define ADDR_PAGE 2
6251 +#define ADDR_COLUMN_PAGE 3
6252 +#define NAND_ChipID_UNKNOWN 0x00
6253 +#define NAND_MAX_FLOORS 1
6254 +#define NAND_MAX_CHIPS 1
6255 +#define BFIN_NAND_READY PF3
6257 +#define NAND_WAIT_READY(nand) \
6259 + int timeout = 0; \
6260 + while(!(*pPORTFIO & PF3)) \
6261 + if (timeout++ > 100000) \
6265 +#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
6266 +#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
6268 +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
6269 +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
6270 +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
6271 +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
6275 + * CF-CARD IDE-HDD Support
6277 +/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
6278 +/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
6279 +/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
6281 +#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
6282 +# define CONFIG_BFIN_IDE 1
6283 +# define ADD_IDE_CMD CFG_CMD_IDE
6285 +# define ADD_IDE_CMD 0
6288 +#if defined(CONFIG_BFIN_IDE)
6290 +#define CONFIG_DOS_PARTITION 1
6294 +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
6295 +#undef CONFIG_IDE_LED /* no led for ide supported */
6296 +#undef CONFIG_IDE_RESET /* no reset for ide supported */
6298 +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
6299 +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
6301 +#undef CONFIG_EBIU_AMBCTL1_VAL
6302 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
6304 +#define CONFIG_CF_ATASEL_DIS 0x20311800
6305 +#define CONFIG_CF_ATASEL_ENA 0x20311802
6307 +#if defined(CONFIG_BFIN_TRUE_IDE)
6309 + * Note that these settings aren't for the most part used in include/ata.h
6310 + * when all of the ATA registers are setup
6312 +#define CFG_ATA_BASE_ADDR 0x2031C000
6313 +#define CFG_ATA_IDE0_OFFSET 0x0000
6314 +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
6315 +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
6316 +#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
6317 +#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
6318 +#endif /* CONFIG_BFIN_TRUE_IDE */
6320 +#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
6321 +#define CFG_ATA_BASE_ADDR 0x20211800
6322 +#define CFG_ATA_IDE0_OFFSET 0x0000
6323 +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
6324 +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
6325 +#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
6326 +#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
6327 +#endif /* CONFIG_BFIN_CF_IDE */
6329 +#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
6330 +#define CFG_ATA_BASE_ADDR 0x20314000
6331 +#define CFG_ATA_IDE0_OFFSET 0x0000
6332 +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
6333 +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
6334 +#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
6335 +#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
6337 +#undef CONFIG_SCLK_DIV
6338 +#define CONFIG_SCLK_DIV 8
6339 +#endif /* CONFIG_BFIN_HDD_IDE */
6341 +#endif /*CONFIG_BFIN_IDE */
6347 +#define CONFIG_MISC_INIT_R
6348 +//#define CONFIG_RTC_BFIN
6350 +/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
6352 +//#define ADI_CMDS_EXTRA (ADD_IDE_CMD | ADD_NAND_CMD)
6354 +#define CONFIG_BFIN_COMMANDS \
6355 + ( CFG_BFIN_CMD_BOOTLDR | \
6356 + CFG_BFIN_CMD_CPLBINFO )
6358 +/* Define if want to do post memory test */
6361 +#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
6362 +#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
6366 + * Pull in common ADI header for remaining command/environment setup
6368 +#include <configs/bfin_adi_common.h>
6370 +#include <asm/blackfin-config-post.h>
6372 +#include <asm/mem_init.h>
6375 +/* Overrides common ADI header's command/environment setup */
6377 +#ifdef CONFIG_BOOTDELAY
6378 +#undef CONFIG_BOOTDELAY
6380 +#define CONFIG_BOOTDELAY 10
6382 +#ifdef CONFIG_BOOTCOMMAND
6383 +#undef CONFIG_BOOTCOMMAND
6385 +#define CONFIG_BOOTCOMMAND "run flashboot"
6387 +#ifdef CONFIG_BOOTARGS
6388 +#undef CONFIG_BOOTARGS
6390 +#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m lpj=496640"
6392 +#ifdef CONFIG_EBIU_SDRRC_VAL
6393 +#undef CONFIG_EBIU_SDRRC_VAL
6395 +#define CONFIG_EBIU_SDRRC_VAL mem_SDRRC
6397 +#ifdef CONFIG_EBIU_SDGCTL_VAL
6398 +#undef CONFIG_EBIU_SDGCTL_VAL
6400 +#define CONFIG_EBIU_SDGCTL_VAL mem_SDGCTL
6402 +#ifdef CONFIG_EBIU_SDBCTL_VAL
6403 +#undef CONFIG_EBIU_SDBCTL_VAL
6405 +#define CONFIG_EBIU_SDBCTL_VAL mem_SDBCTL
6407 +#ifdef CONFIG_EBIU_AMBCTL0_VAL
6408 +#undef CONFIG_EBIU_AMBCTL0_VAL
6410 +#define CONFIG_EBIU_AMBCTL0_VAL flash_EBIU_AMBCTL0
6412 +#ifdef CFG_AUTOLOAD
6413 +#undef CFG_AUTOLOAD
6415 +#define CFG_AUTOLOAD ""
6417 + /* CONFIG_SERIAL_BF537 no longer used*/
6418 +//#define CONFIG_SERIAL_BF537 1
6420 +#ifdef CONFIG_POST_TEST
6421 +#undef CONFIG_POST_TEST
6424 +#define CONFIG_METROLOGIC_IO_INIT 1
6426 +#define CONFIG_CORE_VOLTAGE_MILLIVOLT 1250
6427 +#define CONFIG_DISABLE_CLKIN_OUTPUT 1
6429 +#define CONFIG_METROLOGIC_INTERFACE_DETECTION 1
6430 +#define CONFIG_SUPPORT_KBW 1
6431 +#define CONFIG_SUPPORT_IBM 1
6432 +#define CONFIG_SUPPORT_MULTIFUNC 1
6433 +#define CONFIG_SUPPORT_BLUETOOTH 1
6434 +//#define CONFIG_RTS_DEFAULT_ASSERTED 1
6436 +#define KBCLOCK_PIN 25
6438 +#define KBW_GATE_PIN 27
6439 +#define IBM_RS4680_RESET_PIN 27
6440 +#define FOCUS_KBWEN_PIN 24
6442 +#define BT_LDO_PIN 27
6443 +#define BT_RESET_PIN 26
6444 +#define BT_RDY_PIN 37
6445 +#define BT_CONN_PIN 35
6446 +#define BT_DSR_PIN 34
6447 +#define BT_SWITCH_PIN 2
6448 +#define TRIG_PIN 41
6449 +#define BLUE_LED_PIN 31
6450 +#define WHITE_LED_PIN 30
6451 +#define YELLOW_LED_PIN 29
6454 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
6455 +//#define CFG_AUTOLOAD "no"
6458 +/****************************************************************/
6461 diff --git a/u-boot-1.1.6/include/configs/IS4980.h b/u-boot-1.1.6/include/configs/IS4980.h
6462 new file mode 100644
6463 index 0000000..3861d38
6465 +++ b/u-boot-1.1.6/include/configs/IS4980.h
6468 + * U-boot - Configuration file for BF537 STAMP board
6471 +#ifndef __CONFIG_IS4980_H__
6472 +#define __CONFIG_IS4980_H__
6474 +#include <asm/blackfin-config-pre.h>
6477 +#ifndef __ADSPBF534__
6478 +#define __ADSPBF534__
6480 +#define METROLOGIC_PLATFORM "IS4980"
6481 +#define SUPPORT_NETWORKING 0
6482 +#define CONFIG_SILENT_CONSOLE 1
6483 +#define CONFIG_BAUDRATE 115200
6484 +#define CONFIG_LOADADDR 0x800000
6486 +#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
6487 + "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
6489 +#define CFG_PROMPT "bootldr> "
6490 +#define CONFIG_ZERO_BOOTDELAY_CHECK
6491 +#define CONFIG_AUTOBOOT_KEYED 1
6492 +#define CONFIG_AUTOBOOT_STOP_STR "\033"
6493 +#define CONFIG_MEM_MT48LC16M16A2TG_75 1
6494 +//#define CONFIG_MEM_IS42S16160B_7 1
6496 +//#define CONFIG_DEBUG_EARLY_SERIAL 1
6497 +//#define DEBUG_BOOTKEYS 1
6499 +//#define DEBUG_METRO_IO 1
6500 +//#define DEBUG_I2C 1
6502 +// We don't have a parallel flash chip there
6503 +#define CFG_NO_FLASH
6507 + * Processor Settings
6509 +#define CONFIG_BFIN_CPU bf534-0.2
6510 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
6515 + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
6516 + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
6518 +/* CONFIG_CLKIN_HZ is any value in Hz */
6519 +#define CONFIG_CLKIN_HZ 25000000
6520 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
6521 +/* 1 = CLKIN / 2 */
6522 +#define CONFIG_CLKIN_HALF 0
6523 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
6524 +/* 1 = bypass PLL */
6525 +#define CONFIG_PLL_BYPASS 0
6526 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
6527 +/* Values can range from 0-63 (where 0 means 64) */
6528 +#define CONFIG_VCO_MULT 20
6529 +/* CCLK_DIV controls the core clock divider */
6530 +/* Values can be 1, 2, 4, or 8 ONLY */
6531 +#define CONFIG_CCLK_DIV 1
6532 +/* SCLK_DIV controls the system clock divider */
6533 +/* Values can range from 1-15 */
6534 +#define CONFIG_SCLK_DIV 4
6540 +#define CONFIG_MEM_ADD_WDTH 9
6541 +#define CONFIG_MEM_SIZE 32
6543 +//#define CONFIG_EBIU_SDRRC_VAL 0x306
6544 +//#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
6545 +//#define CONFIG_EBIU_SDBCTL_VAL (EBSZ_64 | EBCAW_10 | EBE)
6547 +#define CONFIG_EBIU_AMGCTL_VAL 0xFF
6548 +//#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
6549 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
6551 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for monitor */
6552 +#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 384 kB for malloc() (video/spi are big) */
6553 +#define CFG_GBL_DATA_SIZE 0x4000
6557 + * Network Settings
6559 +#if SUPPORT_NETWORKING
6560 +#ifndef __ADSPBF534__
6561 +#define ADI_CMDS_NETWORK 1
6562 +#define CONFIG_BFIN_MAC
6563 +#define CONFIG_NETCONSOLE 1
6564 +#define CONFIG_NET_MULTI 1
6566 +#define ADI_CMDS_NETWORK 0
6569 +//#define CONFIG_HOSTNAME bf537-stamp
6570 +/* Uncomment next line to use fixed MAC address */
6571 +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
6577 +#define CFG_FLASH_BASE 0x20000000
6578 +#define CFG_FLASH_CFI /* The flash is CFI compatible */
6579 +//#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
6580 +//#define CFG_FLASH_PROTECTION
6581 +#define CFG_MAX_FLASH_BANKS 1
6582 +#define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
6583 +#define FLASH_SIZE 0x800000
6584 +#define CFG_FLASH_SIZE 0x800000
6586 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
6587 +#define CFG_ENV_IS_IN_EEPROM 1
6588 +#define CFG_ENV_OFFSET 0x4000
6589 +#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
6591 +#define CFG_ENV_IS_IN_FLASH 1
6592 +#define CFG_ENV_ADDR 0x20004000
6593 +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
6595 +#define CFG_ENV_SIZE 0x2000
6596 +#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
6597 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
6598 +#define ENV_IS_EMBEDDED
6600 +#define ENV_IS_EMBEDDED_CUSTOM
6603 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
6604 +/* Values can range from 2-65535 */
6605 +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
6607 +#define CONFIG_SPI_BAUD 2
6608 +#define CONFIG_SPI_BAUD_INITBLOCK 3
6614 +#define CONFIG_HARD_I2C 1 /* I2C TWI */
6615 +#define CFG_I2C_SPEED 50000
6616 +#define CFG_I2C_SLAVE 0
6622 +/* #define CONFIG_BF537_NAND */
6623 +#ifdef CONFIG_BF537_NAND
6624 +# define ADD_NAND_CMD CFG_CMD_NAND
6626 +# define ADD_NAND_CMD 0
6629 +#define CFG_NAND_ADDR 0x20212000
6630 +#define CFG_NAND_BASE CFG_NAND_ADDR
6631 +#define CFG_MAX_NAND_DEVICE 1
6632 +#define SECTORSIZE 512
6633 +#define ADDR_COLUMN 1
6634 +#define ADDR_PAGE 2
6635 +#define ADDR_COLUMN_PAGE 3
6636 +#define NAND_ChipID_UNKNOWN 0x00
6637 +#define NAND_MAX_FLOORS 1
6638 +#define NAND_MAX_CHIPS 1
6639 +#define BFIN_NAND_READY PF3
6641 +#define NAND_WAIT_READY(nand) \
6643 + int timeout = 0; \
6644 + while(!(*pPORTFIO & PF3)) \
6645 + if (timeout++ > 100000) \
6649 +#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
6650 +#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
6652 +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
6653 +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
6654 +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
6655 +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
6659 + * CF-CARD IDE-HDD Support
6661 +/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
6662 +/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
6663 +/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
6665 +#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
6666 +# define CONFIG_BFIN_IDE 1
6667 +# define ADD_IDE_CMD CFG_CMD_IDE
6669 +# define ADD_IDE_CMD 0
6672 +#if defined(CONFIG_BFIN_IDE)
6674 +#define CONFIG_DOS_PARTITION 1
6678 +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
6679 +#undef CONFIG_IDE_LED /* no led for ide supported */
6680 +#undef CONFIG_IDE_RESET /* no reset for ide supported */
6682 +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
6683 +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
6685 +#undef CONFIG_EBIU_AMBCTL1_VAL
6686 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
6688 +#define CONFIG_CF_ATASEL_DIS 0x20311800
6689 +#define CONFIG_CF_ATASEL_ENA 0x20311802
6691 +#if defined(CONFIG_BFIN_TRUE_IDE)
6693 + * Note that these settings aren't for the most part used in include/ata.h
6694 + * when all of the ATA registers are setup
6696 +#define CFG_ATA_BASE_ADDR 0x2031C000
6697 +#define CFG_ATA_IDE0_OFFSET 0x0000
6698 +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
6699 +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
6700 +#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
6701 +#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
6702 +#endif /* CONFIG_BFIN_TRUE_IDE */
6704 +#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
6705 +#define CFG_ATA_BASE_ADDR 0x20211800
6706 +#define CFG_ATA_IDE0_OFFSET 0x0000
6707 +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
6708 +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
6709 +#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
6710 +#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
6711 +#endif /* CONFIG_BFIN_CF_IDE */
6713 +#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
6714 +#define CFG_ATA_BASE_ADDR 0x20314000
6715 +#define CFG_ATA_IDE0_OFFSET 0x0000
6716 +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
6717 +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
6718 +#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
6719 +#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
6721 +#undef CONFIG_SCLK_DIV
6722 +#define CONFIG_SCLK_DIV 8
6723 +#endif /* CONFIG_BFIN_HDD_IDE */
6725 +#endif /*CONFIG_BFIN_IDE */
6731 +#define CONFIG_MISC_INIT_R
6732 +//#define CONFIG_RTC_BFIN
6734 +/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
6736 +//#define ADI_CMDS_EXTRA (ADD_IDE_CMD | ADD_NAND_CMD)
6737 +#define CONFIG_BFIN_COMMANDS \
6738 + ( CFG_BFIN_CMD_BOOTLDR | \
6739 + CFG_BFIN_CMD_CPLBINFO )
6741 +/* Define if want to do post memory test */
6744 +#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
6745 +#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
6750 + * Pull in common ADI header for remaining command/environment setup
6752 +#include <configs/bfin_adi_common.h>
6754 +#include <asm/blackfin-config-post.h>
6756 +#include <asm/mem_init.h>
6759 +/* Overrides common ADI header's command/environment setup */
6761 +#ifdef CONFIG_BOOTDELAY
6762 +#undef CONFIG_BOOTDELAY
6764 +#define CONFIG_BOOTDELAY 10
6766 +#ifdef CONFIG_BOOTCOMMAND
6767 +#undef CONFIG_BOOTCOMMAND
6769 +#define CONFIG_BOOTCOMMAND "run flashboot"
6771 +#ifdef CONFIG_BOOTARGS
6772 +#undef CONFIG_BOOTARGS
6774 +#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m lpj=496640"
6776 +#ifdef CONFIG_EBIU_SDRRC_VAL
6777 +#undef CONFIG_EBIU_SDRRC_VAL
6779 +#define CONFIG_EBIU_SDRRC_VAL mem_SDRRC
6781 +#ifdef CONFIG_EBIU_SDGCTL_VAL
6782 +#undef CONFIG_EBIU_SDGCTL_VAL
6784 +#define CONFIG_EBIU_SDGCTL_VAL mem_SDGCTL
6786 +#ifdef CONFIG_EBIU_SDBCTL_VAL
6787 +#undef CONFIG_EBIU_SDBCTL_VAL
6789 +#define CONFIG_EBIU_SDBCTL_VAL mem_SDBCTL
6791 +#ifdef CONFIG_EBIU_AMBCTL0_VAL
6792 +#undef CONFIG_EBIU_AMBCTL0_VAL
6794 +#define CONFIG_EBIU_AMBCTL0_VAL flash_EBIU_AMBCTL0
6796 +#ifdef CFG_AUTOLOAD
6797 +#undef CFG_AUTOLOAD
6799 +#define CFG_AUTOLOAD ""
6801 + /* CONFIG_SERIAL_BF537 no longer used*/
6802 +//#define CONFIG_SERIAL_BF537 1
6804 +#ifdef CONFIG_POST_TEST
6805 +#undef CONFIG_POST_TEST
6808 +#define CONFIG_METROLOGIC_IO_INIT 1
6810 +#define CONFIG_CORE_VOLTAGE_MILLIVOLT 1250
6811 +#define CONFIG_DISABLE_CLKIN_OUTPUT 1
6813 +//#define CONFIG_METROLOGIC_INTERFACE_DETECTION 1
6814 +//#define CONFIG_SUPPORT_KBW 1
6815 +//#define CONFIG_SUPPORT_IBM 1
6816 +//#define CONFIG_SUPPORT_MULTIFUNC 1
6817 +//#define CONFIG_SUPPORT_BLUETOOTH 1
6818 +//#define CONFIG_RTS_DEFAULT_ASSERTED 1
6820 +//#define KBCLOCK_PIN 25
6822 +//#define KBW_GATE_PIN 27
6823 +#define IBM_RS4680_RESET_PIN 27
6824 +#define FOCUS_KBWEN_PIN 24
6826 +//#define BT_LDO_PIN 27
6827 +//#define BT_RESET_PIN 26
6828 +//#define BT_RDY_PIN 37
6829 +//#define BT_CONN_PIN 35
6830 +//#define BT_DSR_PIN 34
6831 +//#define BT_SWITCH_PIN 2
6832 +//#define TRIG_PIN 41
6833 +//#define BLUE_LED_PIN 31
6834 +//#define WHITE_LED_PIN 30
6835 +//#define YELLOW_LED_PIN 29
6838 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
6839 +//#define CFG_AUTOLOAD "no"
6842 +/****************************************************************/
6845 diff --git a/u-boot-1.1.6/include/configs/Orbit3.h b/u-boot-1.1.6/include/configs/Orbit3.h
6846 new file mode 100644
6847 index 0000000..d7ea48a
6849 +++ b/u-boot-1.1.6/include/configs/Orbit3.h
6852 + * U-boot - Configuration file for BF537 STAMP board
6855 +#ifndef __CONFIG_ORBIT3_H__
6856 +#define __CONFIG_ORBIT3_H__
6858 +#include <asm/blackfin-config-pre.h>
6861 +#ifndef __ADSPBF534__
6862 +#define __ADSPBF534__
6864 +#define METROLOGIC_PLATFORM "Genesis"
6865 +#define SUPPORT_NETWORKING 0
6866 +#define CONFIG_SILENT_CONSOLE 1
6867 +#define CONFIG_BAUDRATE 115200
6868 +#define CONFIG_LOADADDR 0x800000
6870 +#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
6871 + "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
6873 +#define CFG_PROMPT "bootldr> "
6874 +#define CONFIG_ZERO_BOOTDELAY_CHECK
6875 +#define CONFIG_AUTOBOOT_KEYED 1
6876 +#define CONFIG_AUTOBOOT_STOP_STR "\033"
6877 +#define CONFIG_MEM_MT48LC16M16A2TG_75 1
6878 +//#define CONFIG_MEM_IS42S16160B_7 1
6880 +//#define CONFIG_DEBUG_EARLY_SERIAL 1
6881 +//#define DEBUG_BOOTKEYS 1
6883 +//#define DEBUG_METRO_IO 1
6884 +//#define DEBUG_I2C 1
6886 +// We don't have a parallel flash chip there
6887 +#define CFG_NO_FLASH
6891 + * Processor Settings
6893 +#define CONFIG_BFIN_CPU bf534-0.2
6894 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
6899 + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
6900 + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
6902 +/* CONFIG_CLKIN_HZ is any value in Hz */
6903 +#define CONFIG_CLKIN_HZ 25000000
6904 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
6905 +/* 1 = CLKIN / 2 */
6906 +#define CONFIG_CLKIN_HALF 0
6907 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
6908 +/* 1 = bypass PLL */
6909 +#define CONFIG_PLL_BYPASS 0
6910 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
6911 +/* Values can range from 0-63 (where 0 means 64) */
6912 +#define CONFIG_VCO_MULT 20
6913 +/* CCLK_DIV controls the core clock divider */
6914 +/* Values can be 1, 2, 4, or 8 ONLY */
6915 +#define CONFIG_CCLK_DIV 1
6916 +/* SCLK_DIV controls the system clock divider */
6917 +/* Values can range from 1-15 */
6918 +#define CONFIG_SCLK_DIV 4
6924 +#define CONFIG_MEM_ADD_WDTH 9
6925 +#define CONFIG_MEM_SIZE 32
6927 +//#define CONFIG_EBIU_SDRRC_VAL 0x306
6928 +//#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
6929 +//#define CONFIG_EBIU_SDBCTL_VAL (EBSZ_64 | EBCAW_10 | EBE)
6931 +#define CONFIG_EBIU_AMGCTL_VAL 0xFF
6932 +//#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
6933 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
6935 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for monitor */
6936 +#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 384 kB for malloc() (video/spi are big) */
6937 +#define CFG_GBL_DATA_SIZE 0x4000
6941 + * Network Settings
6943 +#if SUPPORT_NETWORKING
6944 +#ifndef __ADSPBF534__
6945 +#define ADI_CMDS_NETWORK 1
6946 +#define CONFIG_BFIN_MAC
6947 +#define CONFIG_NETCONSOLE 1
6948 +#define CONFIG_NET_MULTI 1
6950 +#define ADI_CMDS_NETWORK 0
6953 +//#define CONFIG_HOSTNAME bf537-stamp
6954 +/* Uncomment next line to use fixed MAC address */
6955 +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
6961 +#define CFG_FLASH_BASE 0x20000000
6962 +#define CFG_FLASH_CFI /* The flash is CFI compatible */
6963 +//#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
6964 +//#define CFG_FLASH_PROTECTION
6965 +#define CFG_MAX_FLASH_BANKS 1
6966 +#define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
6967 +#define FLASH_SIZE 0x800000
6968 +#define CFG_FLASH_SIZE 0x800000
6970 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
6971 +#define CFG_ENV_IS_IN_EEPROM 1
6972 +#define CFG_ENV_OFFSET 0x4000
6973 +#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
6975 +#define CFG_ENV_IS_IN_FLASH 1
6976 +#define CFG_ENV_ADDR 0x20004000
6977 +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
6979 +#define CFG_ENV_SIZE 0x2000
6980 +#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
6981 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
6982 +#define ENV_IS_EMBEDDED
6984 +#define ENV_IS_EMBEDDED_CUSTOM
6987 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
6988 +/* Values can range from 2-65535 */
6989 +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
6991 +#define CONFIG_SPI_BAUD 2
6992 +#define CONFIG_SPI_BAUD_INITBLOCK 3
6998 +#define CONFIG_HARD_I2C 1 /* I2C TWI */
6999 +#define CFG_I2C_SPEED 50000
7000 +#define CFG_I2C_SLAVE 0
7006 +/* #define CONFIG_BF537_NAND */
7007 +#ifdef CONFIG_BF537_NAND
7008 +# define ADD_NAND_CMD CFG_CMD_NAND
7010 +# define ADD_NAND_CMD 0
7013 +#define CFG_NAND_ADDR 0x20212000
7014 +#define CFG_NAND_BASE CFG_NAND_ADDR
7015 +#define CFG_MAX_NAND_DEVICE 1
7016 +#define SECTORSIZE 512
7017 +#define ADDR_COLUMN 1
7018 +#define ADDR_PAGE 2
7019 +#define ADDR_COLUMN_PAGE 3
7020 +#define NAND_ChipID_UNKNOWN 0x00
7021 +#define NAND_MAX_FLOORS 1
7022 +#define NAND_MAX_CHIPS 1
7023 +#define BFIN_NAND_READY PF3
7025 +#define NAND_WAIT_READY(nand) \
7027 + int timeout = 0; \
7028 + while(!(*pPORTFIO & PF3)) \
7029 + if (timeout++ > 100000) \
7033 +#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
7034 +#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
7036 +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
7037 +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
7038 +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
7039 +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
7043 + * CF-CARD IDE-HDD Support
7045 +/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
7046 +/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
7047 +/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
7049 +#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
7050 +# define CONFIG_BFIN_IDE 1
7051 +# define ADD_IDE_CMD CFG_CMD_IDE
7053 +# define ADD_IDE_CMD 0
7056 +#if defined(CONFIG_BFIN_IDE)
7058 +#define CONFIG_DOS_PARTITION 1
7062 +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
7063 +#undef CONFIG_IDE_LED /* no led for ide supported */
7064 +#undef CONFIG_IDE_RESET /* no reset for ide supported */
7066 +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
7067 +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
7069 +#undef CONFIG_EBIU_AMBCTL1_VAL
7070 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
7072 +#define CONFIG_CF_ATASEL_DIS 0x20311800
7073 +#define CONFIG_CF_ATASEL_ENA 0x20311802
7075 +#if defined(CONFIG_BFIN_TRUE_IDE)
7077 + * Note that these settings aren't for the most part used in include/ata.h
7078 + * when all of the ATA registers are setup
7080 +#define CFG_ATA_BASE_ADDR 0x2031C000
7081 +#define CFG_ATA_IDE0_OFFSET 0x0000
7082 +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
7083 +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
7084 +#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
7085 +#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
7086 +#endif /* CONFIG_BFIN_TRUE_IDE */
7088 +#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
7089 +#define CFG_ATA_BASE_ADDR 0x20211800
7090 +#define CFG_ATA_IDE0_OFFSET 0x0000
7091 +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
7092 +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
7093 +#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
7094 +#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
7095 +#endif /* CONFIG_BFIN_CF_IDE */
7097 +#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
7098 +#define CFG_ATA_BASE_ADDR 0x20314000
7099 +#define CFG_ATA_IDE0_OFFSET 0x0000
7100 +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
7101 +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
7102 +#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
7103 +#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
7105 +#undef CONFIG_SCLK_DIV
7106 +#define CONFIG_SCLK_DIV 8
7107 +#endif /* CONFIG_BFIN_HDD_IDE */
7109 +#endif /*CONFIG_BFIN_IDE */
7115 +#define CONFIG_MISC_INIT_R
7116 +//#define CONFIG_RTC_BFIN
7118 +/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
7120 +//#define ADI_CMDS_EXTRA (ADD_IDE_CMD | ADD_NAND_CMD)
7121 +#define CONFIG_BFIN_COMMANDS \
7122 + ( CFG_BFIN_CMD_BOOTLDR | \
7123 + CFG_BFIN_CMD_CPLBINFO )
7125 +/* Define if want to do post memory test */
7128 +#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
7129 +#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
7134 + * Pull in common ADI header for remaining command/environment setup
7136 +#include <configs/bfin_adi_common.h>
7138 +#include <asm/blackfin-config-post.h>
7140 +#include <asm/mem_init.h>
7143 +/* Overrides common ADI header's command/environment setup */
7145 +#ifdef CONFIG_BOOTDELAY
7146 +#undef CONFIG_BOOTDELAY
7148 +#define CONFIG_BOOTDELAY 10
7150 +#ifdef CONFIG_BOOTCOMMAND
7151 +#undef CONFIG_BOOTCOMMAND
7153 +#define CONFIG_BOOTCOMMAND "run flashboot"
7155 +#ifdef CONFIG_BOOTARGS
7156 +#undef CONFIG_BOOTARGS
7158 +#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m lpj=496640"
7160 +#ifdef CONFIG_EBIU_SDRRC_VAL
7161 +#undef CONFIG_EBIU_SDRRC_VAL
7163 +#define CONFIG_EBIU_SDRRC_VAL mem_SDRRC
7165 +#ifdef CONFIG_EBIU_SDGCTL_VAL
7166 +#undef CONFIG_EBIU_SDGCTL_VAL
7168 +#define CONFIG_EBIU_SDGCTL_VAL mem_SDGCTL
7170 +#ifdef CONFIG_EBIU_SDBCTL_VAL
7171 +#undef CONFIG_EBIU_SDBCTL_VAL
7173 +#define CONFIG_EBIU_SDBCTL_VAL mem_SDBCTL
7175 +#ifdef CONFIG_EBIU_AMBCTL0_VAL
7176 +#undef CONFIG_EBIU_AMBCTL0_VAL
7178 +#define CONFIG_EBIU_AMBCTL0_VAL flash_EBIU_AMBCTL0
7180 +#ifdef CFG_AUTOLOAD
7181 +#undef CFG_AUTOLOAD
7183 +#define CFG_AUTOLOAD ""
7185 + /* CONFIG_SERIAL_BF537 no longer used*/
7186 +//#define CONFIG_SERIAL_BF537 1
7188 +#ifdef CONFIG_POST_TEST
7189 +#undef CONFIG_POST_TEST
7192 +#define CONFIG_METROLOGIC_IO_INIT 1
7194 +#define CONFIG_CORE_VOLTAGE_MILLIVOLT 1250
7195 +#define CONFIG_DISABLE_CLKIN_OUTPUT 1
7197 +//#define CONFIG_METROLOGIC_INTERFACE_DETECTION 1
7198 +//#define CONFIG_SUPPORT_KBW 1
7199 +//#define CONFIG_SUPPORT_IBM 1
7200 +//#define CONFIG_SUPPORT_MULTIFUNC 1
7201 +//#define CONFIG_SUPPORT_BLUETOOTH 1
7202 +//#define CONFIG_RTS_DEFAULT_ASSERTED 1
7204 +//#define KBCLOCK_PIN 25
7206 +//#define KBW_GATE_PIN 27
7207 +#define IBM_RS4680_RESET_PIN 27
7208 +#define FOCUS_KBWEN_PIN 24
7210 +//#define BT_LDO_PIN 27
7211 +//#define BT_RESET_PIN 26
7212 +//#define BT_RDY_PIN 37
7213 +//#define BT_CONN_PIN 35
7214 +//#define BT_DSR_PIN 34
7215 +//#define BT_SWITCH_PIN 2
7216 +//#define TRIG_PIN 41
7217 +//#define BLUE_LED_PIN 31
7218 +//#define WHITE_LED_PIN 30
7219 +//#define YELLOW_LED_PIN 29
7222 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
7223 +//#define CFG_AUTOLOAD "no"
7226 +/****************************************************************/
7229 diff --git a/u-boot-1.1.6/include/configs/VuQuest2D.h b/u-boot-1.1.6/include/configs/VuQuest2D.h
7230 new file mode 100644
7231 index 0000000..2d9995f
7233 +++ b/u-boot-1.1.6/include/configs/VuQuest2D.h
7236 + * U-boot - Configuration file for BF533 STAMP board
7239 +#ifndef __CONFIG_VUQUEST2D_H__
7240 +#define __CONFIG_VUQUEST2D_H__
7242 +#include <asm/blackfin-config-pre.h>
7245 +#ifndef __ADSPBF531__
7246 +#define __ADSPBF531__
7248 +#define METROLOGIC_PLATFORM "VuQuest2D"
7249 +#define SUPPORT_NETWORKING 0
7250 +#define CONFIG_SILENT_CONSOLE 1
7251 +#define CONFIG_BAUDRATE 115200
7252 +#define CONFIG_LOADADDR 0x800000
7254 +//#define METROLOGIC_FLASH_BOOT_ENV_PARAM "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
7256 +#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
7257 + "flashboot=eeprom read 0x800000 0x60000 0xa0000; bootm 0x800000;\0"
7259 +#define CFG_PROMPT "bootldr> "
7260 +#define CONFIG_ZERO_BOOTDELAY_CHECK
7261 +#define CONFIG_AUTOBOOT_KEYED 1
7262 +#define CONFIG_AUTOBOOT_STOP_STR "\033"
7263 +#define CONFIG_MEM_MT48LC16M16A2TG_75 1
7264 +//#define CONFIG_MEM_IS42S16160B_7 1
7266 +//#define CONFIG_DEBUG_EARLY_SERIAL 1
7267 +//#define DEBUG_BOOTKEYS 1
7270 +// We don't have a parallel flash chip there
7271 +#define CFG_NO_FLASH
7275 + * Processor Settings
7277 +#define CONFIG_BFIN_CPU bf531-0.3
7278 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
7283 + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
7284 + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
7286 +/* CONFIG_CLKIN_HZ is any value in Hz */
7287 +#define CONFIG_CLKIN_HZ 25000000
7288 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
7289 +/* 1 = CLKIN / 2 */
7290 +#define CONFIG_CLKIN_HALF 0
7291 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
7292 +/* 1 = bypass PLL */
7293 +#define CONFIG_PLL_BYPASS 0
7294 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
7295 +/* Values can range from 0-63 (where 0 means 64) */
7296 +#define CONFIG_VCO_MULT 15
7297 +/* CCLK_DIV controls the core clock divider */
7298 +/* Values can be 1, 2, 4, or 8 ONLY */
7299 +#define CONFIG_CCLK_DIV 1
7300 +/* SCLK_DIV controls the system clock divider */
7301 +/* Values can range from 1-15 */
7302 +#define CONFIG_SCLK_DIV 3
7308 +#define CONFIG_MEM_ADD_WDTH 9
7309 +#define CONFIG_MEM_SIZE 32
7311 +#define CONFIG_EBIU_SDRRC_VAL 0x268
7312 +#define CONFIG_EBIU_SDGCTL_VAL 0x911109
7313 +#define CONFIG_EBIU_SDBCTL_VAL (EBSZ_128 | EBCAW_11 | EBE)
7315 +#define CONFIG_EBIU_AMGCTL_VAL 0xFF
7316 +#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
7317 +#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
7319 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for monitor */
7320 +#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 384 kB for malloc() (video/spi are big) */
7321 +#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */
7325 + * Network Settings
7328 +#if SUPPORT_NETWORKING
7330 +#define ADI_CMDS_NETWORK 0
7331 +#define CONFIG_DRIVER_SMC91111 0
7332 +#define CONFIG_SMC91111_BASE 0x20300300
7333 +#define SMC91111_EEPROM_INIT() { *pFIO_DIR = 0x01; *pFIO_FLAG_S = 0x01; SSYNC(); }
7335 +#endif /* SUPPORT_NETWORKING */
7337 +#define CONFIG_HOSTNAME bf533-stamp
7338 +/* To remove hardcoding and enable MAC storage in EEPROM */
7339 +/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
7345 +#define CFG_FLASH_CFI /* The flash is CFI compatible */
7346 +//#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
7347 +#define CFG_FLASH_CFI_AMD_RESET
7349 +#define CFG_FLASH_BASE 0x20000000
7350 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
7351 +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
7352 +#define FLASH_SIZE 0x800000
7353 +#define CFG_FLASH_SIZE 0x800000
7355 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
7356 +#define CFG_ENV_IS_IN_EEPROM 1
7357 +#define CFG_ENV_OFFSET 0x4000
7359 +#define CFG_ENV_IS_IN_FLASH 1
7360 +#define CFG_ENV_ADDR 0x20004000
7361 +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
7363 +#define CFG_ENV_SIZE 0x2000
7364 +#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
7365 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
7366 +#define ENV_IS_EMBEDDED
7368 +#define ENV_IS_EMBEDDED_CUSTOM
7371 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
7372 +/* Values can range from 2-65535 */
7373 +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
7375 +#define CONFIG_SPI_BAUD 2
7376 +#define CONFIG_SPI_BAUD_INITBLOCK 3
7377 +#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
7382 + * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
7384 +#define CONFIG_SOFT_I2C
7387 +#ifdef CONFIG_SOFT_I2C
7388 +#define I2C_INIT do { *pFIO_DIR |= PF_SCL; SSYNC(); } while (0)
7389 +#define I2C_ACTIVE do { *pFIO_DIR |= PF_SDA; *pFIO_INEN &= ~PF_SDA; SSYNC(); } while (0)
7390 +#define I2C_TRISTATE do { *pFIO_DIR &= ~PF_SDA; *pFIO_INEN |= PF_SDA; SSYNC(); } while (0)
7391 +#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0)
7392 +#define I2C_SDA(bit) \
7395 + *pFIO_FLAG_S = PF_SDA; \
7397 + *pFIO_FLAG_C = PF_SDA; \
7400 +#define I2C_SCL(bit) \
7403 + *pFIO_FLAG_S = PF_SCL; \
7405 + *pFIO_FLAG_C = PF_SCL; \
7408 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
7410 +#define CFG_I2C_SPEED 50000
7411 +#define CFG_I2C_SLAVE 0
7416 + * Compact Flash / IDE / ATA Settings
7419 +/* Enabled below option for CF support */
7420 +/* #define CONFIG_STAMP_CF */
7421 +#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
7422 +#define CONFIG_MISC_INIT_R
7423 +#define CONFIG_DOS_PARTITION 1
7424 +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
7425 +#undef CONFIG_IDE_LED /* no led for ide supported */
7426 +#undef CONFIG_IDE_RESET /* no reset for ide supported */
7428 +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
7429 +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
7431 +#define CFG_ATA_BASE_ADDR 0x20200000
7432 +#define CFG_ATA_IDE0_OFFSET 0x0000
7434 +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
7435 +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
7436 +#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
7438 +#define CFG_ATA_STRIDE 2
7440 +#undef CONFIG_EBIU_AMBCTL1_VAL
7441 +#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
7448 +// #define CONFIG_RTC_BFIN
7450 +#define CONFIG_BFIN_COMMANDS \
7451 + ( CFG_BFIN_CMD_CPLBINFO )
7453 +/* FLASH/ETHERNET uses the same async bank */
7454 +#define SHARED_RESOURCES 1
7456 +#ifdef CONFIG_POST_TEST
7457 +#undef CONFIG_POST_TEST
7460 +/* define to enable splash screen support */
7461 +/* #define CONFIG_VIDEO */
7464 + * Pull in common ADI header for remaining command/environment setup
7466 +#include <configs/bfin_adi_common.h>
7468 +#include <asm/blackfin-config-post.h>
7470 +#include <asm/mem_init.h>
7473 +/* Overrides common ADI header's command/environment setup */
7475 +#ifdef CONFIG_BOOTDELAY
7476 +#undef CONFIG_BOOTDELAY
7478 +#define CONFIG_BOOTDELAY 0
7480 +#ifdef CONFIG_BOOTCOMMAND
7481 +#undef CONFIG_BOOTCOMMAND
7483 +#define CONFIG_BOOTCOMMAND "run flashboot"
7485 +#ifdef CONFIG_BOOTARGS
7486 +#undef CONFIG_BOOTARGS
7488 +#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m lpj=396288"
7490 +#ifdef CONFIG_EBIU_SDRRC_VAL
7491 +#undef CONFIG_EBIU_SDRRC_VAL
7493 +#define CONFIG_EBIU_SDRRC_VAL mem_SDRRC
7495 +#ifdef CONFIG_EBIU_SDGCTL_VAL
7496 +#undef CONFIG_EBIU_SDGCTL_VAL
7498 +#define CONFIG_EBIU_SDGCTL_VAL mem_SDGCTL
7500 +#ifdef CONFIG_EBIU_SDBCTL_VAL
7501 +#undef CONFIG_EBIU_SDBCTL_VAL
7503 +#define CONFIG_EBIU_SDBCTL_VAL mem_SDBCTL
7505 +#ifdef CONFIG_EBIU_AMBCTL0_VAL
7506 +#undef CONFIG_EBIU_AMBCTL0_VAL
7508 +#define CONFIG_EBIU_AMBCTL0_VAL flash_EBIU_AMBCTL0
7510 +#ifdef CFG_AUTOLOAD
7511 +#undef CFG_AUTOLOAD
7513 +#define CFG_AUTOLOAD ""
7515 + /* CONFIG_SERIAL_BF537 no longer used*/
7516 +//#define CONFIG_SERIAL_BF537 1
7518 +#define CONFIG_METROLOGIC_IO_INIT 1
7520 +#define CONFIG_CORE_VOLTAGE_MILLIVOLT 1250
7521 +#define CONFIG_DISABLE_CLKIN_OUTPUT 1
7523 +#define CONFIG_METROLOGIC_INTERFACE_DETECTION 1
7524 +#define CONFIG_METROLOGIC_VQ2D_REV 2
7525 +//#define CONFIG_SUPPORT_KBW 1
7526 +//#define CONFIG_SUPPORT_IBM 1
7527 +//#define CONFIG_SUPPORT_MULTIFUNC 1
7528 +//#define CONFIG_SUPPORT_BLUETOOTH 1
7529 +//#define CONFIG_RTS_DEFAULT_ASSERTED 1
7531 +//#define KBCLOCK_PIN 25
7533 +//#define KBW_GATE_PIN 27
7534 +//#define IBM_RS4680_RESET_PIN 27
7535 +//#define FOCUS_KBWEN_PIN 24
7537 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
7538 +//#define CFG_AUTOLOAD "no"
7541 +/****************************************************************/
7544 diff --git a/u-boot-1.1.6/include/configs/bf533-stamp.h b/u-boot-1.1.6/include/configs/bf533-stamp.h
7545 index 2e6a51e..6b68418 100644
7546 --- a/u-boot-1.1.6/include/configs/bf533-stamp.h
7547 +++ b/u-boot-1.1.6/include/configs/bf533-stamp.h
7549 #include <asm/blackfin-config-pre.h>
7552 +#ifndef __ADSPBF533__
7553 +#define __ADSPBF533__
7555 +#define METROLOGIC_PLATFORM "ADI Eval Board"
7556 +#define SUPPORT_NETWORKING 0
7557 +#define CONFIG_SILENT_CONSOLE 1
7558 +#define CONFIG_BAUDRATE 115200
7559 +#define CONFIG_LOADADDR 0x800000
7560 +#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
7561 + "flashboot=bootm 0x20060000\0"
7562 +#define CFG_PROMPT "bootldr> "
7563 +#define CONFIG_ZERO_BOOTDELAY_CHECK
7564 +#define CONFIG_AUTOBOOT_KEYED 1
7565 +#define CONFIG_AUTOBOOT_STOP_STR "\033"
7568 * Processor Settings
7571 #define CONFIG_CCLK_DIV 1
7572 /* SCLK_DIV controls the system clock divider */
7573 /* Values can range from 1-15 */
7574 -#define CONFIG_SCLK_DIV 5
7576 +#define CONFIG_SCLK_DIV 4
7584 +#if SUPPORT_NETWORKING
7585 #define ADI_CMDS_NETWORK 1
7586 #define CONFIG_DRIVER_SMC91111 1
7587 #define CONFIG_SMC91111_BASE 0x20300300
7588 #define SMC91111_EEPROM_INIT() { *pFIO_DIR = 0x01; *pFIO_FLAG_S = 0x01; SSYNC(); }
7589 +#endif /* SUPPORT_NETWORKING */
7591 #define CONFIG_HOSTNAME bf533-stamp
7592 /* To remove hardcoding and enable MAC storage in EEPROM */
7593 /* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
7595 #define CFG_FLASH_BASE 0x20000000
7596 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
7597 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
7598 +#define FLASH_SIZE 0x800000
7599 +#define CFG_FLASH_SIZE 0x800000
7601 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
7602 #define CFG_ENV_IS_IN_EEPROM 1
7607 -#define CONFIG_RTC_BFIN
7608 +//#define CONFIG_RTC_BFIN
7610 #define CONFIG_BFIN_COMMANDS \
7611 ( CFG_BFIN_CMD_CPLBINFO )
7613 /* define to enable splash screen support */
7614 /* #define CONFIG_VIDEO */
7619 * Pull in common ADI header for remaining command/environment setup
7621 @@ -193,4 +210,24 @@
7623 #include <asm/blackfin-config-post.h>
7625 +#include <asm/mem_init.h>
7628 +/* Overrides common ADI header's command/environment setup */
7630 +#ifdef CONFIG_BOOTDELAY
7631 +#undef CONFIG_BOOTDELAY
7633 +#define CONFIG_BOOTDELAY 1
7635 +#ifdef CONFIG_BOOTCOMMAND
7636 +#undef CONFIG_BOOTCOMMAND
7638 +#define CONFIG_BOOTCOMMAND "run flashboot"
7640 +#ifdef CONFIG_BOOTARGS
7641 +#undef CONFIG_BOOTARGS
7643 +#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m"
7646 diff --git a/u-boot-1.1.6/include/configs/bf537-srv1.h b/u-boot-1.1.6/include/configs/bf537-srv1.h
7647 index f7d5bba..83c78c8 100644
7648 --- a/u-boot-1.1.6/include/configs/bf537-srv1.h
7649 +++ b/u-boot-1.1.6/include/configs/bf537-srv1.h
7650 @@ -155,28 +155,37 @@
7653 #ifdef CONFIG_BFIN_MAC
7654 -# define CONFIG_BFIN_CMD (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_DHCP)
7655 +# define CONFIG_BFIN_CMD (CONFIG_CMD_DFL | CFG_CMD_PING)
7657 # define CONFIG_BFIN_CMD (CONFIG_CMD_DFL & ~CFG_CMD_NET)
7660 -#ifdef CFG_NO_FLASH
7661 -# define CONFIG_BFIN_CMD2 (CONFIG_BFIN_CMD & ~(CFG_CMD_IMLS | CFG_CMD_FLASH))
7663 -# define CONFIG_BFIN_CMD2 (CONFIG_BFIN_CMD | CFG_CMD_JFFS2)
7664 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) || (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
7665 +#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \
7670 + CFG_CMD_EEPROM | \
7674 + CFG_CMD_POST_DIAG | \
7676 +#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
7677 +#define CONFIG_COMMANDS (( CONFIG_BFIN_CMD| \
7681 + /* CFG_CMD_JFFS2 | */ \
7682 + CFG_CMD_EEPROM | \
7683 + /* ADD_IDE_CMD | */ \
7686 + /* no image ls */ ~(CFG_CMD_IMLS | CFG_CMD_FLASH) \
7690 -#define CONFIG_COMMANDS \
7691 - (CONFIG_BFIN_CMD2 | \
7695 - CFG_CMD_EEPROM | \
7698 - CFG_CMD_POST_DIAG | \
7701 #define CONFIG_BFIN_COMMANDS \
7702 ( CFG_BFIN_CMD_BOOTLDR | \
7703 CFG_BFIN_CMD_CPLBINFO )
7705 "update=tftpboot $(loadaddr) u-boot.bin;" \
7706 "protect off 0x20000000 0x2003FFFF;" \
7707 "erase 0x20000000 0x2003FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0"
7708 -#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) || (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
7709 +#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
7710 # define BOOT_ENV_SETTINGS \
7711 "update=tftpboot $(loadaddr) u-boot.ldr;" \
7712 "eeprom write $(loadaddr) 0x0 $(filesize);\0" \
7713 @@ -243,18 +252,19 @@
7715 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
7716 #define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
7717 -#define CFG_MALLOC_LEN (384 << 10) /* Reserve 128 kB for malloc() */
7718 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
7719 #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
7720 #define CFG_GBL_DATA_SIZE 0x4000
7721 #define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
7722 #define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
7725 -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
7726 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) || (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
7727 +/* for bf537-stamp, UART boot mode still store env in flash */
7728 #define CFG_ENV_IS_IN_FLASH 1
7729 #define CFG_ENV_ADDR 0x20004000
7730 #define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
7731 -#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) || (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
7732 +#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
7733 #define CFG_ENV_IS_IN_EEPROM 1
7734 #define CFG_ENV_OFFSET 0x10000
7735 #define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
7736 diff --git a/u-boot-1.1.6/include/configs/bf537-stamp.h b/u-boot-1.1.6/include/configs/bf537-stamp.h
7737 index aa4925f..f98c145 100644
7738 --- a/u-boot-1.1.6/include/configs/bf537-stamp.h
7739 +++ b/u-boot-1.1.6/include/configs/bf537-stamp.h
7741 #include <asm/blackfin-config-pre.h>
7745 +#ifndef __ADSPBF537__
7746 +#define __ADSPBF537__
7748 +#define METROLOGIC_PLATFORM "ADI Eval Board"
7749 +#define SUPPORT_NETWORKING 1
7750 +#define CONFIG_SILENT_CONSOLE 1
7751 +#define CONFIG_BAUDRATE 115200
7752 +#define CONFIG_LOADADDR 0x800000
7753 +#define METROLOGIC_FLASH_BOOT_ENV_PARAM "silent=1\0" \
7754 + "flashboot=bootm 0x20060000\0"
7755 +#define CFG_PROMPT "bootldr> "
7756 +#define CONFIG_ZERO_BOOTDELAY_CHECK
7757 +#define CONFIG_AUTOBOOT_KEYED 1
7758 +#define CONFIG_AUTOBOOT_STOP_STR "\033"
7761 * Processor Settings
7763 #define CONFIG_BFIN_CPU bf537-0.2
7765 #define CONFIG_CCLK_DIV 1
7766 /* SCLK_DIV controls the system clock divider */
7767 /* Values can range from 1-15 */
7768 -#define CONFIG_SCLK_DIV 5
7769 +#define CONFIG_SCLK_DIV 4
7777 +#if SUPPORT_NETWORKING
7778 #ifndef __ADSPBF534__
7779 #define ADI_CMDS_NETWORK 1
7780 #define CONFIG_BFIN_MAC
7781 #define CONFIG_NETCONSOLE 1
7782 #define CONFIG_NET_MULTI 1
7784 +#define ADI_CMDS_NETWORK 0
7787 #define CONFIG_HOSTNAME bf537-stamp
7788 /* Uncomment next line to use fixed MAC address */
7790 #define CFG_FLASH_BASE 0x20000000
7791 #define CFG_FLASH_CFI /* The flash is CFI compatible */
7792 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
7793 -#define CFG_FLASH_PROTECTION
7794 +//#define CFG_FLASH_PROTECTION
7795 #define CFG_MAX_FLASH_BANKS 1
7796 #define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
7797 +#define FLASH_SIZE 0x800000
7798 +#define CFG_FLASH_SIZE 0x800000
7800 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
7801 #define CFG_ENV_IS_IN_EEPROM 1
7802 @@ -228,11 +249,11 @@
7805 #define CONFIG_MISC_INIT_R
7806 -#define CONFIG_RTC_BFIN
7807 +//#define CONFIG_RTC_BFIN
7809 /* #define CONFIG_BF537_STAMP_LEDCMD 1 */
7811 -#define ADI_CMDS_EXTRA (ADD_IDE_CMD | ADD_NAND_CMD)
7812 +//#define ADI_CMDS_EXTRA (ADD_IDE_CMD | ADD_NAND_CMD)
7813 #define CONFIG_BFIN_COMMANDS \
7814 ( CFG_BFIN_CMD_BOOTLDR | \
7815 CFG_BFIN_CMD_CPLBINFO )
7817 #define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
7822 * Pull in common ADI header for remaining command/environment setup
7824 @@ -252,4 +272,24 @@
7826 #include <asm/blackfin-config-post.h>
7828 +#include <asm/mem_init.h>
7831 +/* Overrides common ADI header's command/environment setup */
7833 +#ifdef CONFIG_BOOTDELAY
7834 +#undef CONFIG_BOOTDELAY
7836 +#define CONFIG_BOOTDELAY 1
7838 +#ifdef CONFIG_BOOTCOMMAND
7839 +#undef CONFIG_BOOTCOMMAND
7841 +#define CONFIG_BOOTCOMMAND "run flashboot"
7843 +#ifdef CONFIG_BOOTARGS
7844 +#undef CONFIG_BOOTARGS
7846 +#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2 max_mem=32m$# mem=28m"
7849 diff --git a/u-boot-1.1.6/include/configs/bfin_adi_common.h b/u-boot-1.1.6/include/configs/bfin_adi_common.h
7850 index 1b4b851..faddc0e 100644
7851 --- a/u-boot-1.1.6/include/configs/bfin_adi_common.h
7852 +++ b/u-boot-1.1.6/include/configs/bfin_adi_common.h
7856 #ifndef CONFIG_COMMANDS
7857 +# ifdef CFG_NO_FLASH
7858 +# define ADI_CMDS_BASE1 (CONFIG_CMD_DFL & ~(CFG_CMD_IMLS | CFG_CMD_FLASH))
7860 +# define ADI_CMDS_BASE1 (CONFIG_CMD_DFL)
7862 # if ADI_CMDS_NETWORK
7863 -# define ADI_CMDS_BASE (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_DHCP)
7864 +# define ADI_CMDS_BASE (ADI_CMDS_BASE1 | CFG_CMD_PING | CFG_CMD_DHCP)
7866 -# define ADI_CMDS_BASE (CONFIG_CMD_DFL & ~CFG_CMD_NET)
7867 +# define ADI_CMDS_BASE (ADI_CMDS_BASE1 & ~CFG_CMD_NET)
7869 # ifdef CONFIG_RTC_BFIN
7870 # define ADI_CMDS_DATE (CFG_CMD_DATE)
7871 @@ -144,9 +149,16 @@
7873 # define NETWORK_ENV_SETTINGS
7876 +#ifdef METROLOGIC_FLASH_BOOT_ENV_PARAM
7877 + #define EXTRA_ENV_SETTINGS METROLOGIC_FLASH_BOOT_ENV_PARAM
7879 + #define EXTRA_ENV_SETTINGS "flashboot=bootm 0x20060000\0"
7882 #define CONFIG_EXTRA_ENV_SETTINGS \
7883 NETWORK_ENV_SETTINGS \
7884 - "flashboot=bootm 0x20100000\0"
7885 + EXTRA_ENV_SETTINGS
7889 diff --git a/u-boot-1.1.6/include/flash.h b/u-boot-1.1.6/include/flash.h
7890 index c9129cd..c35d87e 100644
7891 --- a/u-boot-1.1.6/include/flash.h
7892 +++ b/u-boot-1.1.6/include/flash.h
7897 -#ifndef CFG_NO_FLASH
7898 /*-----------------------------------------------------------------------
7899 * FLASH Info: contains chip specific data, per FLASH bank
7901 @@ -49,6 +48,8 @@ typedef struct {
7905 +#ifndef CFG_NO_FLASH
7908 * Values for the width of the port
7910 diff --git a/u-boot-1.1.6/include/metro_pf.h b/u-boot-1.1.6/include/metro_pf.h
7911 new file mode 100644
7912 index 0000000..f274139
7914 +++ b/u-boot-1.1.6/include/metro_pf.h
7921 +#define PF_bit(pfx) ( 1 << (pfx & 0x0f) )
7925 +//#define CSYNC asm("csync;")
7929 +//#define SSYNC asm("ssync;")
7933 +#if (defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)) || \
7934 + defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
7936 +#define Metro_set_pfx_level(pf_num, level) \
7938 + if ((pf_num >= 0) && (pf_num < 48)) \
7942 + if (pf_num < 16) \
7943 + *pPORTFIO_SET = PF_bit(pf_num); \
7944 + else if (pf_num < 32) \
7945 + *pPORTGIO_SET = PF_bit(pf_num); \
7947 + *pPORTHIO_SET = PF_bit(pf_num); \
7951 + if (pf_num < 16) \
7952 + *pPORTFIO_CLEAR = PF_bit(pf_num); \
7953 + else if (pf_num < 32) \
7954 + *pPORTGIO_CLEAR = PF_bit(pf_num); \
7956 + *pPORTHIO_CLEAR = PF_bit(pf_num); \
7967 +#define Metro_get_pfx_level(pf_num) ( (pf_num < 16) ? \
7968 + ( ( (*pPORTFIO ^ *pPORTFIO_POLAR) & PF_bit(pf_num) ) ? 1 : 0) : \
7970 + ( ( (*pPORTGIO ^ *pPORTGIO_POLAR) & PF_bit(pf_num) ) ? 1 : 0) : \
7971 + ( ( (*pPORTHIO ^ *pPORTHIO_POLAR) & PF_bit(pf_num) ) ? 1 : 0) )
7973 +#elif (defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) || \
7974 +defined(__ADSPBF531__)) || defined(__ADSPBF532__) || defined(__ADSPBF533__)
7976 +#define Metro_set_pfx_level(pf_num, level) \
7978 + if ((pf_num >= 0) && (pf_num < 16)) \
7981 + *pFIO_FLAG_S = PF_bit(pf_num); \
7983 + *pFIO_FLAG_C = PF_bit(pf_num); \
7993 +#define Metro_get_pfx_level(pf_num) ( ( (*pFIO_FLAG_D ^ *pFIO_POLAR) & PF_bit(pf_num) ) ? 1 : 0)
7997 +#error "Platform not supported"
8003 +//#define GPDRX_OUT(gpio_pin) { Metro_set_pfx_dir(gpio_pin, 1, -1); }
8004 +//#define GPDRX_IN(gpio_pin) { Metro_set_pfx_dir(gpio_pin, 0, -1); }
8006 +//#define SET_PIN(gpio_pin) { Metro_set_pfx_level(gpio_pin, 1); }
8007 +//#define CLR_PIN(gpio_pin) { Metro_set_pfx_level(gpio_pin, 0); }
8008 +//#define GET_PIN_LEVEL(gpio_pin) ( Metro_get_pfx_level(gpio_pin) )
8010 +extern int Metro_set_pfx_dir(int pf_num, int dir, int initial_val);
8011 +extern int Metro_get_pfx_dir(int pf_num);
8013 +extern int set_pfx_dir(int pf_num, int dir);
8014 +extern int get_pfx_dir(int pf_num);
8015 +extern int get_pfx_level(int pf_num);
8016 +extern int set_pfx_level(int pf_num, int level);
8018 +#endif /* METRO_PF_H */
8019 diff --git a/u-boot-1.1.6/lib_blackfin/board.c b/u-boot-1.1.6/lib_blackfin/board.c
8020 index 942bfbc..5d32f12 100644
8021 --- a/u-boot-1.1.6/lib_blackfin/board.c
8022 +++ b/u-boot-1.1.6/lib_blackfin/board.c
8027 -const char version_string[] = U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ")";
8028 +#define VERSION_STRING_FORMAT "%s (%s - %s)\n%s\n%s (%s)\n"
8029 +#define METROLOGIC_NAME "Metrologic Instruments, Inc."
8030 +#define METROLOGIC_VERSION "Alex_2008R1_Ver1"
8031 +#ifndef METROLOGIC_PLATFORM
8032 +#define METROLOGIC_PLATFORM "UNKNOWN_PLATFORM"
8034 +const char version_string[] = U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ") " METROLOGIC_NAME " " METROLOGIC_PLATFORM " " METROLOGIC_VERSION ;
8036 +//const char version_string[] = U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ")";
8038 __attribute__((always_inline))
8039 static inline void serial_early_puts(const char *s)
8040 @@ -160,7 +168,9 @@ static void display_global_data(void)
8041 printf(" |-jt(%x): %x\n", gd->jt, *(gd->jt));
8042 printf(" \\-bd: %x\n", gd->bd);
8043 printf(" |-bi_baudrate: %x\n", bd->bi_baudrate);
8044 +#if (CONFIG_COMMANDS & CFG_CMD_NET)
8045 printf(" |-bi_ip_addr: %x\n", bd->bi_ip_addr);
8047 printf(" |-bi_enetaddr: %x %x %x %x %x %x\n",
8048 bd->bi_enetaddr[0], bd->bi_enetaddr[1],
8049 bd->bi_enetaddr[2], bd->bi_enetaddr[3],
8050 @@ -464,6 +474,24 @@ void board_init_r(gd_t * id, ulong dest_addr)
8051 post_run(NULL, POST_RAM | post_bootmode_get(0));
8054 +#if defined(CONFIG_METROLOGIC_IO_INIT)
8055 + /* miscellaneous platform dependent initialisations */
8056 +#if defined(DEBUG_METRO_IO)
8057 + printf("start metrologic_io_init()\r\n");
8059 + udelay(50 * 1000);
8060 + metrologic_io_init();
8061 +#if defined(DEBUG_METRO_IO)
8062 + printf("done metrologic_io_init()\r\n");
8066 +#if defined(CONFIG_CORE_VOLTAGE_MILLIVOLT)
8067 + program_vrctl(CONFIG_CORE_VOLTAGE_MILLIVOLT);
8068 +#elif defined(CONFIG_DISABLE_CLKIN_OUTPUT)
8070 +#endif // CONFIG_CORE_VOLTAGE_MILLIVOLT
8072 /* main_loop() can return to retry autoboot, if so just run it again. */
8075 diff --git a/u-boot-1.1.6/uses.mak b/u-boot-1.1.6/uses.mak
8076 new file mode 100644
8077 index 0000000..84483e4
8079 +++ b/u-boot-1.1.6/uses.mak
8081 +KERNEL_REV = 2007R1/Bfin_422
8082 +TOOLCHAIN_REV = Ver_2008R1.5
8085 +CROSS_COMPILE_PATH = /usr/src/blackfin/ADI_release/tools/$(TOOLCHAIN_REV)/bfin-uclinux/bin