1 Index: include/asm-blackfin/reboot.h
2 ===================================================================
3 --- include/asm-blackfin/reboot.h (revision 0)
4 +++ include/asm-blackfin/reboot.h (revision 0)
7 + * include/asm-blackfin/reboot.h - shutdown/reboot header
9 + * Copyright 2004-2007 Analog Devices Inc.
11 + * Licensed under the GPL-2 or later.
14 +#ifndef __ASM_REBOOT_H__
15 +#define __ASM_REBOOT_H__
17 +/* optional board specific hooks */
18 +extern void native_machine_restart(char *cmd);
19 +extern void native_machine_halt(void);
20 +extern void native_machine_power_off(void);
22 +/* common reboot workarounds */
23 +extern void bfin_gpio_reset_spi0_ssel1(void);
26 Index: arch/blackfin/kernel/process.c
27 ===================================================================
28 --- arch/blackfin/kernel/process.c (revision 3549)
29 +++ arch/blackfin/kernel/process.c (working copy)
34 -void machine_restart(char *__unused)
36 -#if defined(CONFIG_BFIN_ICACHE)
37 - bfin_write_IMEM_CONTROL(0x01);
41 - /* Dont do anything till the reset occurs */
47 -void machine_halt(void)
50 - asm volatile ("idle");
53 -void machine_power_off(void)
56 - asm volatile ("idle");
59 void show_regs(struct pt_regs *regs)
61 printk(KERN_NOTICE "\n");
62 Index: arch/blackfin/kernel/reboot.c
63 ===================================================================
64 --- arch/blackfin/kernel/reboot.c (revision 0)
65 +++ arch/blackfin/kernel/reboot.c (revision 0)
68 + * arch/blackfin/kernel/reboot.c - handle shutdown/reboot
70 + * Copyright 2004-2007 Analog Devices Inc.
72 + * Licensed under the GPL-2 or later.
75 +#include <linux/interrupt.h>
76 +#include <asm/bfin-global.h>
77 +#include <asm/reboot.h>
79 +static void bfin_spin_forever(void)
82 + asm volatile ("idle");
85 +/* A system soft reset makes external memory unusable
86 + * so force this function into L1.
88 +__attribute__((l1_text))
89 +void bfin_reset(void)
91 + /* force BMODE and disable Core B (as needed) */
92 + bfin_write_SYSCR(0x20);
94 + /* initiate system soft reset with magic 0x7 */
95 + bfin_write_SWRST(0x7);
97 + /* clear system soft reset */
98 + bfin_write_SWRST(0);
100 + /* issue core reset */
105 +__attribute__((weak))
106 +void native_machine_restart(char *cmd)
110 +void machine_restart(char *cmd)
112 + native_machine_restart(cmd);
113 + local_irq_disable();
117 +__attribute__((weak))
118 +void native_machine_halt(void)
120 + local_irq_disable();
121 + bfin_spin_forever();
124 +void machine_halt(void)
126 + native_machine_halt();
129 +__attribute__((weak))
130 +void native_machine_power_off(void)
132 + local_irq_disable();
133 + bfin_spin_forever();
136 +void machine_power_off(void)
138 + native_machine_power_off();
140 Index: arch/blackfin/kernel/bfin_gpio.c
141 ===================================================================
142 --- arch/blackfin/kernel/bfin_gpio.c (revision 3549)
143 +++ arch/blackfin/kernel/bfin_gpio.c (working copy)
148 +#include <linux/delay.h>
149 #include <linux/module.h>
150 #include <linux/err.h>
151 #include <asm/blackfin.h>
153 local_irq_restore(flags);
155 EXPORT_SYMBOL(gpio_direction_output);
157 +/* If we are booting from SPI and our board lacks a strong enough pull up,
158 + * the core can reset and execute the bootrom faster than the resistor can
159 + * pull the signal logically high. To work around this (common) error in
160 + * board design, we explicitly set the pin back to GPIO mode, force /CS
161 + * high, and wait for the electrons to do their thing.
163 + * This function only makes sense to be called from reset code, but it
164 + * lives here as we need to force all the GPIO states w/out going through
165 + * BUG() checks and such.
167 +void bfin_gpio_reset_spi0_ssel1(void)
169 + port_setup(P_SPI0_SSEL1, GPIO_USAGE);
170 + gpio_bankb[gpio_bank(P_SPI0_SSEL1)]->data_set = gpio_bit(P_SPI0_SSEL1);
173 Index: arch/blackfin/kernel/Makefile
174 ===================================================================
175 --- arch/blackfin/kernel/Makefile (revision 3549)
176 +++ arch/blackfin/kernel/Makefile (working copy)
179 entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
180 sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o \
181 - fixed_code.o cplbinit.o cacheinit.o
182 + fixed_code.o cplbinit.o cacheinit.o reboot.o
184 obj-$(CONFIG_BF53x) += bfin_gpio.o
185 obj-$(CONFIG_BF561) += bfin_gpio.o
186 Index: arch/blackfin/mach-bf533/head.S
187 ===================================================================
188 --- arch/blackfin/mach-bf533/head.S (revision 3549)
189 +++ arch/blackfin/mach-bf533/head.S (working copy)
191 ENDPROC(_start_dma_code)
192 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
195 - /* No more interrupts to be handled*/
199 -#if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
200 - p0.h = hi(FIO_INEN);
201 - p0.l = lo(FIO_INEN);
202 - r0.l = ~(1 << CONFIG_ENET_FLASH_PIN);
205 - p0.h = hi(FIO_DIR);
206 - p0.l = lo(FIO_DIR);
207 - r0.l = (1 << CONFIG_ENET_FLASH_PIN);
210 - p0.h = hi(FIO_FLAG_C);
211 - p0.l = lo(FIO_FLAG_C);
212 - r0.l = (1 << CONFIG_ENET_FLASH_PIN);
216 - /* Clear the IMASK register */
222 - /* Clear the ILAT register */
229 - /* make sure SYSCR is set to use BMODE */
236 - /* issue a system soft reset */
243 - /* clear system soft reset */
248 - /* issue core reset */
252 -ENDPROC(_bfin_reset)
254 #if CONFIG_DEBUG_KERNEL_START
255 debug_kernel_start_trap:
256 /* Set up a temp stack in L1 - SDRAM might not be working */
257 Index: arch/blackfin/mach-bf533/boards/stamp.c
258 ===================================================================
259 --- arch/blackfin/mach-bf533/boards/stamp.c (revision 3549)
260 +++ arch/blackfin/mach-bf533/boards/stamp.c (working copy)
262 #include <linux/irq.h>
264 #include <asm/bfin5xx_spi.h>
265 +#include <asm/reboot.h>
268 * Name the Board for the /proc/cpuinfo
272 arch_initcall(stamp_init);
274 +void native_machine_restart(char *cmd)
276 +#if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
277 +# define BIT_TO_SET (1 << CONFIG_ENET_FLASH_PIN)
278 + bfin_write_FIO_INEN(~BIT_TO_SET);
279 + bfin_write_FIO_DIR(BIT_TO_SET);
280 + bfin_write_FIO_FLAG_C(BIT_TO_SET);
283 Index: arch/blackfin/mach-bf561/head.S
284 ===================================================================
285 --- arch/blackfin/mach-bf561/head.S (revision 3549)
286 +++ arch/blackfin/mach-bf561/head.S (working copy)
288 ENDPROC(_start_dma_code)
289 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
292 - /* No more interrupts to be handled*/
296 -#if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
297 - p0.h = hi(FIO_INEN);
298 - p0.l = lo(FIO_INEN);
299 - r0.l = ~(PF1 | PF0);
302 - p0.h = hi(FIO_DIR);
303 - p0.l = lo(FIO_DIR);
304 - r0.l = (PF1 | PF0);
307 - p0.h = hi(FIO_FLAG_C);
308 - p0.l = lo(FIO_FLAG_C);
309 - r0.l = (PF1 | PF0);
313 - /* Clear the IMASK register */
319 - /* Clear the ILAT register */
326 - /* make sure SYSCR is set to use BMODE */
329 - R0.l = 0x20; /* on BF561, disable core b */
333 - /* issue a system soft reset */
340 - /* clear system soft reset */
345 - /* issue core reset */
349 -ENDPROC(_bfin_reset)
354 Index: arch/blackfin/mach-bf537/head.S
355 ===================================================================
356 --- arch/blackfin/mach-bf537/head.S (revision 3549)
357 +++ arch/blackfin/mach-bf537/head.S (working copy)
359 ENDPROC(_start_dma_code)
360 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
363 - /* No more interrupts to be handled*/
367 -#if defined(CONFIG_MTD_M25P80)
369 - * The following code fix the SPI flash reboot issue,
370 - * /CS signal of the chip which is using PF10 return to GPIO mode
372 - p0.h = hi(PORTF_FER);
373 - p0.l = lo(PORTF_FER);
378 - /* /CS return to high */
379 - p0.h = hi(PORTFIO);
380 - p0.l = lo(PORTFIO);
385 - /* Delay some time, This is necessary */
389 - lsetup (.L_delay_lab1, .L_delay_lab1_end) lc1 = p1;
394 - lsetup (.L_delay_lab0, .L_delay_lab0_end) lc0 = p0;
403 - /* Clear the IMASK register */
409 - /* Clear the ILAT register */
416 - /* make sure SYSCR is set to use BMODE */
423 - /* issue a system soft reset */
430 - /* clear system soft reset */
435 - /* issue core reset */
439 -ENDPROC(_bfin_reset)
444 Index: arch/blackfin/mach-bf537/boards/stamp.c
445 ===================================================================
446 --- arch/blackfin/mach-bf537/boards/stamp.c (revision 3549)
447 +++ arch/blackfin/mach-bf537/boards/stamp.c (working copy)
449 #include <linux/usb_sl811.h>
451 #include <asm/bfin5xx_spi.h>
452 +#include <asm/reboot.h>
453 #include <linux/spi/ad7877.h>
459 arch_initcall(stamp_init);
461 +void native_machine_restart(char *cmd)
463 + /* workaround reboot hang when booting from SPI */
464 + if ((bfin_read_SYSCR() & 0x7) == 0x3)
465 + bfin_gpio_reset_spi0_ssel1();
467 Index: arch/blackfin/mach-bf548/head.S
468 ===================================================================
469 --- arch/blackfin/mach-bf548/head.S (revision 3549)
470 +++ arch/blackfin/mach-bf548/head.S (working copy)
471 @@ -378,131 +378,6 @@
473 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
476 - /* No more interrupts to be handled*/
480 -#if 0 /* Need to determine later if this is here necessary for BF54x */
481 -#if defined(CONFIG_MTD_M25P80)
483 - * The following code fix the SPI flash reboot issue,
484 - * /CS signal of the chip which is using PF10 return to GPIO mode
486 - p0.h = hi(PORTF_FER);
487 - p0.l = lo(PORTF_FER);
492 -/* /CS return to high */
493 - p0.h = hi(PORTFIO);
494 - p0.l = lo(PORTFIO);
499 -/* Delay some time, This is necessary */
503 - lsetup (_delay_lab1,_delay_lab1_end ) lc1 = p1;
508 - lsetup (_delay_lab0,_delay_lab0_end ) lc0 = p0;
518 - /* Clear the bits 13-15 in SWRST if they werent cleared */
524 - /* Clear the IMASK register */
530 - /* Clear the ILAT register */
537 - /* Disable the WDOG TIMER */
538 - p0.h = hi(WDOG_CTL);
539 - p0.l = lo(WDOG_CTL);
544 - /* Clear the sticky bit incase it is already set */
545 - p0.h = hi(WDOG_CTL);
546 - p0.l = lo(WDOG_CTL);
551 - /* Program the count value */
554 - P0.h = hi(WDOG_CNT);
555 - P0.l = lo(WDOG_CNT);
559 - /* Program WDOG_STAT if necessary */
560 - P0.h = hi(WDOG_CTL);
561 - P0.l = lo(WDOG_CTL);
564 - if !CC JUMP .LWRITESTAT;
566 - if !CC JUMP .LWRITESTAT;
570 - /* When watch dog timer is enabled,
571 - * a write to STAT will load the contents of CNT to STAT
574 - P0.h = hi(WDOG_STAT);
575 - P0.l = lo(WDOG_STAT)
580 - /* Enable the reset event */
581 - P0.h = hi(WDOG_CTL);
582 - P0.l = lo(WDOG_CTL);
590 - /* Enable the wdog counter */